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Issue 3256004: [ARM] tegra: add nvos/nvrm/nvmap drivers (Closed) Base URL: ssh://git@gitrw.chromium.org/kernel.git
Patch Set: remove ap15 headers Created 10 years, 3 months ago
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1 /*
2 * Copyright (c) 2009 NVIDIA Corporation.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of the NVIDIA Corporation nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 */
32 #ifndef ___DEV_AP_PCIE2_PADS_H_INC_
33 #define ___DEV_AP_PCIE2_PADS_H_INC_
34
35 #define NV_PROJ__PCIE2_PADS 0x000000BC:0x00000098 /* RW--D */
36 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0 0x00000098 /* RW-4 R */
37 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT 31:0 /* RWIV F */
38 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_DEFAULT 0xFFFFFFFF /* RWI- V */
39 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_NO_LANES 0x00000000 /* RW-- V */
40 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_LANES_31_0 0xFFFFFFFF /* RW-- V */
41 #define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_MASK 0x0000001C /* RW-- V */
42 #define NV_PROJ__PCIE2_PADS_CTL_SEL_1 0x0000009C /* RW-4 R */
43 #define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT 31:0 /* RWIV F */
44 #define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_DEFAULT 0xFFFFFFFF /* RWI- V */
45 #define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_NO_LANES 0x00000000 /* RW-- V */
46 #define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_LANES_63_32 0xFFFFFFFF /* RW-- V */
47 #define NV_PROJ__PCIE2_PADS_CTL_1 0x000000A0 /* RW-4 R */
48 #define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L 0:0 /* RWIV F */
49 #define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L_DEFAULT 0x00000000 /* RWI- V */
50 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P 1:1 /* RWIV F */
51 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_DEFAULT 0x00000000 /* RWI- V */
52 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_PD 0x00000001 /* RW-- V */
53 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_NOT_PD 0x00000000 /* RW-- V */
54 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P 3:3 /* RWIV F */
55 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DEFAULT 0x00000000 /* RWI- V */
56 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_ENABLE 0x00000001 /* RW-- V */
57 #define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DISABLE 0x00000000 /* RW-- V */
58 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L 5:4 /* RWIV F */
59 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DEFAULT 0x00000003 /* RWI- V */
60 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_ACTIVE 0x00000000 /* RW-- V */
61 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_PARTIAL 0x00000001 /* RW-- V */
62 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_SLUMBER 0x00000002 /* RW-- V */
63 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DISABLED 0x00000003 /* RW-- V */
64 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L 6:6 /* RWIV F */
65 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DEFAULT 0x00000000 /* RWI- V */
66 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_ENABLE 0x00000001 /* RW-- V */
67 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DISABLE 0x00000000 /* RW-- V */
68 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L 7:7 /* RWIV F */
69 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DEFAULT 0x00000000 /* RWI- V */
70 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_ENABLE 0x00000001 /* RW-- V */
71 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DISABLE 0x00000000 /* RW-- V */
72 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L 9:8 /* RWIV F */
73 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DEFAULT 0x00000003 /* RWI- V */
74 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_ACTIVE 0x00000000 /* RW-- V */
75 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_PARTIAL 0x00000001 /* RW-- V */
76 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_SLUMBER 0x00000002 /* RW-- V */
77 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DISABLED 0x00000003 /* RW-- V */
78 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L 10:10 /* RWIV F */
79 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DEFAULT 0x00000000 /* RWI- V */
80 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_ENABLE 0x00000001 /* RW-- V */
81 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DISABLE 0x00000000 /* RW-- V */
82 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L 11:11 /* RWIV F */
83 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DEFAULT 0x00000000 /* RWI- V */
84 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_ENABLE 0x00000001 /* RW-- V */
85 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DISABLE 0x00000000 /* RW-- V */
86 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L 13:12 /* RWIV F */
87 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_DEFAULT 0x00000001 /* RWI- V */
88 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_05X 0x00000000 /* RW-- V */
89 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_1X 0x00000001 /* RW-- V */
90 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_2X 0x00000003 /* RW-- V */
91 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L 15:14 /* RWIV F */
92 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_DEFAULT 0x00000001 /* RWI- V */
93 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_05X 0x00000000 /* RW-- V */
94 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_1X 0x00000001 /* RW-- V */
95 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_2X 0x00000003 /* RW-- V */
96 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L 16:16 /* R--V F */
97 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_IDLE 0x00000001 /* R--- V */
98 #define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_SIG_PRESENT 0x00000000 /* R--- V */
99 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L 17:17 /* R--V F */
100 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_PRSNT 0x00000001 /* R--- V */
101 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_ABSNT 0x00000000 /* R--- V */
102 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS 19:19 /* RWIV F */
103 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DEFAULT 0x00000000 /* RWI- V */
104 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_ENABLE 0x00000001 /* RW-- V */
105 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DISABLE 0x00000000 /* RW-- V */
106 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P 21:20 /* RWIV F */
107 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_DEFAULT 0x00000000 /* RWI- V */
108 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2REGOUT 0x00000003 /* RW-- V */
109 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2REGOUT 0x00000002 /* RW-- V */
110 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2RXOUT 0x00000001 /* RW-- V */
111 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2RXOUT 0x00000000 /* RW-- V */
112 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS 22:22 /* RWIV F */
113 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DEFAULT 0x00000000 /* RWI- V */
114 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_ENABLE 0x00000001 /* RW-- V */
115 #define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DISABLE 0x00000000 /* RW-- V */
116 #define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS 23:23 /* RWIV F */
117 #define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DEFAULT 0x00000000 /* RWI- V */
118 #define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_ENABLE 0x00000001 /* RW-- V */
119 #define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DISABLE 0x00000000 /* RW-- V */
120 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P 26:24 /* RWIV F */
121 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_DEFAULT 0x00000000 /* RWI- V */
122 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_CLK 0x00000003 /* RW-- V */
123 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_DATA 0x00000002 /* RW-- V */
124 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_IDLE_DET 0x00000001 /* RW-- V */
125 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_RX_AMP 0x00000000 /* RW-- V */
126 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS 27:27 /* RWIV F */
127 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DEFAULT 0x00000000 /* RWI- V */
128 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_ENABLE 0x00000001 /* RW-- V */
129 #define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DISABLE 0x00000000 /* RW-- V */
130 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS 30:28 /* R WIVF */
131 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_DEFAULT 0x00000000 /* R WI-V */
132 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_17C 0x00000005 /* R W--V */
133 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_01F 0x00000004 /* R W--V */
134 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_333 0x00000003 /* R W--V */
135 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_155 0x00000002 /* R W--V */
136 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_PRBS_27_1 0x00000001 /* R W--V */
137 #define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_NORMAL 0x00000000 /* R W--V */
138 #define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS 31:31 /* RWIV F */
139 #define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DEFAULT 0x00000000 /* RWI- V */
140 #define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_ENABLE 0x00000001 /* RW-- V */
141 #define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DISABLE 0x00000000 /* RW-- V */
142 #define NV_PROJ__PCIE2_PADS_CTL_2 0x000000A4 /* RW-4 R */
143 #define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P 7:0 /* RWIV F */
144 #define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P_DEFAULT 0x00000010 /* RWI- V */
145 #define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P 11:8 /* RWIV F */
146 #define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P_DEFAULT 0x00000000 /* RWI- V */
147 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P 13:12 /* RWIV F */
148 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P_DEFAULT 0x00000000 /* RWI- V */
149 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P 15:14 /* RWIV F */
150 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_DEFAULT 0x00000000 /* RWI- V */
151 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_70_MVPPD 0x00000002 /* RW-- V */
152 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_120_MVPPD 0x00000001 /* RW-- V */
153 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_100_MVPPD 0x00000000 /* RW-- V */
154 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L 17:16 /* RWIV F */
155 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_DEFAULT 0x00000000 /* RWI- V */
156 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_NORMAL 0x00000000 /* RW-- V */
157 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L 19:18 /* RWIV F */
158 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_DEFAULT 0x00000000 /* RWI- V */
159 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_NORMAL 0x00000000 /* RW-- V */
160 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L 20:20 /* RWIV F */
161 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L_DEFAULT 0x00000000 /* RWI- V */
162 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_IN_1L 21:21 /* R--V F */
163 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L 22:22 /* RWIV F */
164 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L_DEFAULT 0x00000000 /* RWI- V */
165 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L 23:23 /* RWIV F */
166 #define NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L_DEFAULT 0x00000000 /* RWI- V */
167 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L 24:24 /* RWIV F */
168 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L_DEFAULT 0x00000000 /* RWI- V */
169 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_IN_1L 25:25 /* R--V F */
170 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L 26:26 /* RWIV F */
171 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L_DEFAULT 0x00000000 /* RWI- V */
172 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L 27:27 /* RWIV F */
173 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L_DEFAULT 0x00000000 /* RWI- V */
174 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L 28:28 /* RWIV F */
175 #define NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L_DEFAULT 0x00000000 /* RWI- V */
176 #define NV_PROJ__PCIE2_PADS_CTL_4 0x000000A8 /* RW-4 R */
177 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS 0:0 /* RWIV F */
178 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_DEFAULT 0x00000000 /* RWI- V */
179 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_BYPASS 0x00000001 /* RW-- V */
180 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_NORMAL 0x00000000 /* RW-- V */
181 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS 1:1 /* RWIV F */
182 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_DEFAULT 0x00000000 /* RWI- V */
183 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_BYPASS 0x00000001 /* RW-- V */
184 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_NORMAL 0x00000000 /* RW-- V */
185 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P 6:4 /* RWIV F */
186 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_DEFAULT 0x00000002 /* RWI- V */
187 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MIN 0x00000000 /* RW-- V */
188 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_CENTERED 0x00000002 /* RW-- V */
189 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MAX 0x00000004 /* RW-- V */
190 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS 7:7 /* RWIV F */
191 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DEFAULT 0x00000000 /* RWI- V */
192 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_ENABLE 0x00000001 /* RW-- V */
193 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DISABLE 0x00000000 /* RW-- V */
194 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS 8:8 /* RWIV F */
195 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DEFAULT 0x00000000 /* RWI- V */
196 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_ENABLE 0x00000001 /* RW-- V */
197 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DISABLE 0x00000000 /* RW-- V */
198 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS 12:12 /* RWIV F */
199 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DEFAULT 0x00000000 /* RWI- V */
200 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_ENABLE 0x00000001 /* RW-- V */
201 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DISABLE 0x00000000 /* RW-- V */
202 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L 13:13 /* R--V F */
203 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_ERROR 0x00000001 /* R--- V */
204 #define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_NO_ERROR 0x00000000 /* R--- V */
205 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS 19:16 /* RWIV F */
206 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DEFAULT 0x00000000 /* RWI- V */
207 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_ENABLE 0x00000001 /* RW-- V */
208 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DISABLE 0x00000000 /* RW-- V */
209 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P 23:20 /* RWIV F */
210 #define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P_DEFAULT 0x00000000 /* RWI- V */
211 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P 24:24 /* RWIV F */
212 #define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P_DEFAULT 0x00000000 /* RWI- V */
213 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P 25:25 /* RWIV F */
214 #define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P_DEFAULT 0x00000000 /* RWI- V */
215 #define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS 29:28 /* RWIV F */
216 #define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS_DEFAULT 0x00000000 /* RWI- V */
217 #define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_OUT_1L 31:30 /* R--V F */
218 #define NV_PROJ__PCIE2_PADS_CTL_5 0x000000AC /* RW-4 R */
219 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C 5:0 /* RWIV F */
220 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_DEFAULT 0x00000020 /* RWI- V */
221 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1150_MVPPD 0x00000026 /* RW-- V */
222 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1000_MVPPD 0x00000020 /* RW-- V */
223 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__500_MVPPD 0x0000000C /* RW-- V */
224 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__200_MVPPD 0x00000000 /* RW-- V */
225 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C 11:8 /* RWIV F */
226 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C_DEFAULT 0x00000000 /* RWI- V */
227 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C 16:12 /* RWIV F */
228 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DEFAULT 0x0000000E /* RWI- V */
229 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DISABLE 0x00000000 /* RW-- V */
230 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_37DB 0x0000000E /* RW-- V */
231 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_60DB 0x00000014 /* RW-- V */
232 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C 19:17 /* RWIV F */
233 #define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C_DEFAULT 0x00000000 /* RWI- V */
234 #define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C 30:28 /* RWIV F */
235 #define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_DEFAULT 0x00000000 /* RWI- V */
236 #define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_NO_EQ 0x00000000 /* RW-- V */
237 #define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_MAX_EQ 0x00000007 /* RW-- V */
238 #define NV_PROJ__PCIE2_PADS_CTL_6 0x000000B0 /* RW-4 R */
239 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C 5:0 /* RWIV F */
240 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_DEFAULT 0x00000020 /* RWI- V */
241 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1150_MVPPD 0x00000026 /* RW-- V */
242 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1000_MVPPD 0x00000020 /* RW-- V */
243 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__500_MVPPD 0x0000000C /* RW-- V */
244 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__200_MVPPD 0x00000000 /* RW-- V */
245 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C 11:8 /* RWIV F */
246 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C_DEFAULT 0x00000000 /* RWI- V */
247 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C 16:12 /* RWIV F */
248 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DEFAULT 0x0000000E /* RWI- V */
249 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DISABLE 0x00000000 /* RW-- V */
250 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_37DB 0x0000000E /* RW-- V */
251 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_60DB 0x00000014 /* RW-- V */
252 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C 19:17 /* R WIVF */
253 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C_DEFAULT 0x00000000 /* R WI-V */
254 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C 24:20 /* RWIV F */
255 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DEFAULT 0x00000014 /* RWI- V */
256 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DISABLE 0x00000000 /* RW-- V */
257 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_37DB 0x0000000E /* RW-- V */
258 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_60DB 0x00000014 /* RW-- V */
259 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C 27:25 /* R WIVF */
260 #define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C_DEFAULT 0x00000000 /* R WI-V */
261 #define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C 30:28 /* RWIV F */
262 #define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_DEFAULT 0x00000000 /* RWI- V */
263 #define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_NO_EQ 0x00000000 /* RW-- V */
264 #define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_MAX_EQ 0x00000007 /* RW-- V */
265 #define NV_PROJ__PCIE2_PADS_PLL_SEL 0x000000B4 /* RW-4 R */
266 #define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT 31:0 /* RWIV F */
267 #define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_DEFAULT 0xFFFFFFFF /* RWI- V */
268 #define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_NO_PLLS 0x00000000 /* RW-- V */
269 #define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_PLLS_31_0 0xFFFFFFFF /* RW-- V */
270 #define NV_PROJ__PCIE2_PADS_PLL_CTL1 0x000000B8 /* R W-4R */
271 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM 0:0 /* R WIUF */
272 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DEFAULT 0x00000000 /* R WI-V */
273 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_ENABLED 0x00000001 /* R W--V */
274 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DISABLED 0x00000000 /* R W--V */
275 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM 1:1 /* R WIUF */
276 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEFAULT 0x00000000 /* R WI-V */
277 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_ASSERT 0x00000000 /* R W--V */
278 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEASSERT 0x00000001 /* R W--V */
279 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST 2:2 /* R WIUF */
280 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_DEFAULT 0x00000000 /* R WI-V */
281 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_HOLD 0x00000000 /* R W--V */
282 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_RELEASE 0x00000001 /* R W--V */
283 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R 4:4 /* R WIUF */
284 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DEFAULT 0x00000000 /* R WI-V */
285 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DISABLED 0x00000000 /* R W--V */
286 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_ENABLED 0x00000001 /* R W--V */
287 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L 5:5 /* R WIUF */
288 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DEFAULT 0x00000000 /* R WI-V */
289 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DISABLED 0x00000000 /* R W--V */
290 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_ENABLED 0x00000001 /* R W--V */
291 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M 6:6 /* R WIUF */
292 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_DEFAULT 0x00000000 /* R WI-V */
293 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_INDEPENDENT 0x00000000 /* R W--V */
294 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_SHARED 0x00000001 /* R W--V */
295 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD 7:7 /* R WIUF */
296 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DEFAULT 0x00000000 /* R WI-V */
297 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DISABLED 0x00000000 /* R W--V */
298 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_ENABLED 0x00000001 /* R W--V */
299 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET 8:8 /* R --VF */
300 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_NOT_LOCKED 0x00000000 /* R ---V */
301 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_LOCKED 0x00000001 /* R ---V */
302 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL 14:12 /* R WIUF */
303 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DEFAULT 0x00000000 /* R WI-V */
304 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV10 0x00000000 /* R W--V */
305 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV9 0x00000001 /* R W--V */
306 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV8 0x00000002 /* R W--V */
307 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV7 0x00000003 /* R W--V */
308 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV3 0x00000007 /* R W--V */
309 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN 15:15 /* R WIUF */
310 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DEFAULT 0x00000001 /* R WI-V */
311 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DISABLED 0x00000000 /* R W--V */
312 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_ENABLED 0x00000001 /* R W--V */
313 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL 17:16 /* R WIUF */
314 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_DEFAULT 0x00000000 /* RWI-V */
315 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CML 0x00000000 /* RW--V */
316 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CMOS 0x00000001 /* RW--V */
317 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_EXTERNAL 0x00000002 /* RW--V */
318 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV 19:18 /* R WIUF */
319 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_DEFAULT 0x00000002 /* R WI-V */
320 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_10X 0x00000000 /* R W--V */
321 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_20X 0x00000001 /* R W--V */
322 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_25X 0x00000002 /* R W--V */
323 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_30X 0x00000003 /* R W--V */
324 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL 20:20 /* R WIUF */
325 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DEFAULT 0x00000001 /* R WI-V */
326 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV10 0x00000000 /* R W--V */
327 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV5 0x00000001 /* R W--V */
328 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN 21:21 /* R WIUF */
329 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DEFAULT 0x00000001 /* R WI-V */
330 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DISABLED 0x00000000 /* R W--V */
331 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_ENABLED 0x00000001 /* R W--V */
332 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN 22:22 /* R WIUF */
333 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DEFAULT 0x00000001 /* R WI-V */
334 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DISABLED 0x00000000 /* R W--V */
335 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_ENABLED 0x00000001 /* R W--V */
336 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN 23:23 /* R WIUF */
337 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DEFAULT 0x00000001 /* R WI-V */
338 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DISABLED 0x00000000 /* R W--V */
339 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_ENABLED 0x00000001 /* R W--V */
340 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL 26:24 /* R WIUF */
341 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DEFAULT 0x00000000 /* R WI-V */
342 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV10 0x00000000 /* R W--V */
343 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV5 0x00000001 /* R W--V */
344 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_XDIGCLK 0x00000002 /* R W--V */
345 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_REFCLK 0x00000003 /* R W--V */
346 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_LFBCLK 0x00000007 /* R W--V */
347 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN 27:27 /* R WIUF */
348 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DEFAULT 0x00000000 /* R WI-V */
349 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DISABLED 0x00000000 /* R W--V */
350 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_ENABLED 0x00000001 /* R W--V */
351 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100 28:28 /* R WIUF */
352 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DEFAULT 0x00000000 /* R WI-V */
353 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DISABLED 0x00000000 /* R W--V */
354 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_ENABLED 0x00000001 /* R W--V */
355 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON 29:29 /* R WIUF */
356 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DEFAULT 0x00000000 /* R WI-V */
357 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DISABLED 0x00000000 /* R W--V */
358 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_ENABLED 0x00000001 /* R W--V */
359 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN 31:31 /* R WIUF */
360 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DEFAULT 0x00000000 /* R WI-V */
361 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DISABLED 0x00000000 /* R W--V */
362 #define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_ENABLED 0x00000001 /* R W--V */
363 #define NV_PROJ__PCIE2_PADS_PLL_CTL2 0x000000BC /* R W-4R */
364 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE 4:0 /* R WIUF */
365 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_DEFAULT 0x0000000E /* R WI-V */
366 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MAX_R 0x00000000 /* R W--V */
367 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_NOMINAL_R 0x0000000E /* R W--V */
368 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MIN_R 0x0000001F /* R W--V */
369 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS 7:7 /* R WIUF */
370 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DEFAULT 0x00000001 /* R WI-V */
371 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DISABLED 0x00000000 /* R W--V */
372 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_ENABLED 0x00000001 /* R W--V */
373 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL 12:8 /* R --VF */
374 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MAX_R 0x00000000 /* R ---V */
375 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MIN_R 0x0000001F /* R ---V */
376 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET 14:14 /* R WIUF */
377 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DEFAULT 0x00000000 /* R WI-V */
378 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DISABLED 0x00000000 /* R W--V */
379 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_ENABLED 0x00000001 /* R W--V */
380 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE 15:15 /* R --VF */
381 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_FALSE 0x00000000 /* R ---V */
382 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_TRUE 0x00000001 /* R ---V */
383 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL 17:16 /* R WIUF */
384 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_DEFAULT 0x00000000 /* R WI-V */
385 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL 0x00000000 /* R W--V */
386 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_POS_COEFF 0x00000001 /* R W--V */
387 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NEG_COEFF 0x00000002 /* R W--V */
388 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL_PLUS 0x00000003 /* R W--V */
389 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL 22:20 /* R WIUF */
390 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_DEFAULT 0x00000004 /* R WI-V */
391 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_15UA 0x00000000 /* R W--V */
392 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_17P5UA 0x00000001 /* R W--V */
393 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_20UA 0x00000002 /* R W--V */
394 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_22P5UA 0x00000003 /* R W--V */
395 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_25UA 0x00000005 /* R W--V */
396 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_27P5UA 0x00000006 /* R W--V */
397 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_30UA 0x00000007 /* R W--V */
398 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL 27:24 /* R WIUF */
399 #define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL_DEFAULT 0x00000000 /* R WI-V */
400 #define NV_PROJ__PCIE2_PADS_PLL_CTL3 0x000000C0 /* R W-4R */
401 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ 0:0 /* R WIUF */
402 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DEFAULT 0x00000000 /* R WI-V */
403 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DISABLED 0x00000000 /* R W--V */
404 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_ENABLED 0x00000001 /* R W--V */
405 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST 1:1 /* R WIUF */
406 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEFAULT 0x00000000 /* R WI-V */
407 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_ASSERT 0x00000000 /* R W--V */
408 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEASSERT 0x00000001 /* R W--V */
409 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE 4:4 /* R WIUF */
410 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DEFAULT 0x00000000 /* R WI-V */
411 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_PCIE 0x00000000 /* R W--V */
412 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DISPLAY 0x00000001 /* R W--V */
413 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET 8:8 /* R --VF */
414 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_NOT_LOCKED 0x00000000 /* R ---V */
415 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_LOCKED 0x00000001 /* R ---V */
416 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL 26:24 /* R WIUF */
417 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DEFAULT 0x00000000 /* R WI-V */
418 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV5 0x00000000 /* R W--V */
419 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV10 0x00000001 /* R W--V */
420 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_REFCLK 0x00000002 /* R W--V */
421 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_LFBCLK 0x00000003 /* R W--V */
422 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TXCLKREF 0x00000006 /* R W--V */
423 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TKOUT_IN 0x00000007 /* R W--V */
424 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN 27:27 /* R WIUF */
425 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DEFAULT 0x00000000 /* R WI-V */
426 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DISABLED 0x00000000 /* R W--V */
427 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_ENABLED 0x00000001 /* R W--V */
428 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN 31:31 /* R WIUF */
429 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DEFAULT 0x00000000 /* R WI-V */
430 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DISABLED 0x00000000 /* R W--V */
431 #define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_ENABLED 0x00000001 /* R W--V */
432 #define NV_PROJ__PCIE2_PADS_PLL_CTL4 0x000000C4 /* R W-4R */
433 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ 0:0 /* R WIUF */
434 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DEFAULT 0x00000000 /* R WI-V */
435 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DISABLED 0x00000000 /* R W--V */
436 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_ENABLED 0x00000001 /* R W--V */
437 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST 1:1 /* R WIUF */
438 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEFAULT 0x00000000 /* R WI-V */
439 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_ASSERT 0x00000000 /* R W--V */
440 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEASSERT 0x00000001 /* R W--V */
441 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE 4:4 /* R WIUF */
442 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DEFAULT 0x00000000 /* R WI-V */
443 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_PCIE 0x00000000 /* R W--V */
444 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DISPLAY 0x00000001 /* R W--V */
445 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET 8:8 /* R --VF */
446 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_NOT_LOCKED 0x00000000 /* R ---V */
447 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_LOCKED 0x00000001 /* R ---V */
448 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL 26:24 /* R WIUF */
449 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DEFAULT 0x00000000 /* R WI-V */
450 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV5 0x00000000 /* R W--V */
451 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV10 0x00000001 /* R W--V */
452 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_REFCLK 0x00000002 /* R W--V */
453 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_LFBCLK 0x00000003 /* R W--V */
454 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TXCLKREF 0x00000006 /* R W--V */
455 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TKOUT_IN 0x00000007 /* R W--V */
456 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN 27:27 /* R WIUF */
457 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DEFAULT 0x00000000 /* R WI-V */
458 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DISABLED 0x00000000 /* R W--V */
459 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_ENABLED 0x00000001 /* R W--V */
460 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN 31:31 /* R WIUF */
461 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DEFAULT 0x00000000 /* R WI-V */
462 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DISABLED 0x00000000 /* R W--V */
463 #define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_ENABLED 0x00000001 /* R W--V */
464
465 #endif // ifndef ___DEV_AP_PCIE2_PADS_H_INC_
466
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