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| 1 /* |
| 2 * Copyright (c) 2009 NVIDIA Corporation. |
| 3 * All rights reserved. |
| 4 * |
| 5 * Redistribution and use in source and binary forms, with or without |
| 6 * modification, are permitted provided that the following conditions are met: |
| 7 * |
| 8 * Redistributions of source code must retain the above copyright notice, |
| 9 * this list of conditions and the following disclaimer. |
| 10 * |
| 11 * Redistributions in binary form must reproduce the above copyright notice, |
| 12 * this list of conditions and the following disclaimer in the documentation |
| 13 * and/or other materials provided with the distribution. |
| 14 * |
| 15 * Neither the name of the NVIDIA Corporation nor the names of its contributors |
| 16 * may be used to endorse or promote products derived from this software |
| 17 * without specific prior written permission. |
| 18 * |
| 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 * POSSIBILITY OF SUCH DAMAGE. |
| 30 * |
| 31 */ |
| 32 // |
| 33 // DO NOT EDIT - generated by simspec! |
| 34 // |
| 35 |
| 36 #ifndef ___ARSCU_H_INC_ |
| 37 #define ___ARSCU_H_INC_ |
| 38 |
| 39 // Register SCU_CONTROL_0 |
| 40 #define SCU_CONTROL_0 _MK_ADDR_CONST(0x0) |
| 41 #define SCU_CONTROL_0_SECURE 0x0 |
| 42 #define SCU_CONTROL_0_WORD_COUNT 0x1 |
| 43 #define SCU_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 44 #define SCU_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7) |
| 45 #define SCU_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) |
| 46 #define SCU_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) |
| 47 #define SCU_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7) |
| 48 #define SCU_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x7) |
| 49 #define SCU_CONTROL_0_SCU_ENABLE_SHIFT _MK_SHIFT_CONST(0) |
| 50 #define SCU_CONTROL_0_SCU_ENABLE_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONTROL_0_SCU_ENABLE_SHIFT) |
| 51 #define SCU_CONTROL_0_SCU_ENABLE_RANGE 0:0 |
| 52 #define SCU_CONTROL_0_SCU_ENABLE_WOFFSET 0x0 |
| 53 #define SCU_CONTROL_0_SCU_ENABLE_DEFAULT _MK_MASK_CONST(0
x0) |
| 54 #define SCU_CONTROL_0_SCU_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 55 #define SCU_CONTROL_0_SCU_ENABLE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 56 #define SCU_CONTROL_0_SCU_ENABLE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 57 |
| 58 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SHIFT _MK_SHIFT_CONST(
1) |
| 59 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_FIELD (_MK_MASK_CONST(
0x1) << SCU_CONTROL_0_ADDR_FILTER_ENABLE_SHIFT) |
| 60 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_RANGE 1:1 |
| 61 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_WOFFSET 0x0 |
| 62 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_DEFAULT _MK_MASK
_CONST(0x0) |
| 63 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 64 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 65 #define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 66 |
| 67 #define SCU_CONTROL_0_PARITY_ON_SHIFT _MK_SHIFT_CONST(2) |
| 68 #define SCU_CONTROL_0_PARITY_ON_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONTROL_0_PARITY_ON_SHIFT) |
| 69 #define SCU_CONTROL_0_PARITY_ON_RANGE 2:2 |
| 70 #define SCU_CONTROL_0_PARITY_ON_WOFFSET 0x0 |
| 71 #define SCU_CONTROL_0_PARITY_ON_DEFAULT _MK_MASK_CONST(0x0) |
| 72 #define SCU_CONTROL_0_PARITY_ON_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 73 #define SCU_CONTROL_0_PARITY_ON_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 74 #define SCU_CONTROL_0_PARITY_ON_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 75 |
| 76 |
| 77 // Register SCU_CONFIG_0 |
| 78 #define SCU_CONFIG_0 _MK_ADDR_CONST(0x4) |
| 79 #define SCU_CONFIG_0_SECURE 0x0 |
| 80 #define SCU_CONFIG_0_WORD_COUNT 0x1 |
| 81 #define SCU_CONFIG_0_RESET_VAL _MK_MASK_CONST(0xff00) |
| 82 #define SCU_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xfff3) |
| 83 #define SCU_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) |
| 84 #define SCU_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) |
| 85 #define SCU_CONFIG_0_READ_MASK _MK_MASK_CONST(0xfff3) |
| 86 #define SCU_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 87 #define SCU_CONFIG_0_CPU_NUM_SHIFT _MK_SHIFT_CONST(0) |
| 88 #define SCU_CONFIG_0_CPU_NUM_FIELD (_MK_MASK_CONST(0x3) <<
SCU_CONFIG_0_CPU_NUM_SHIFT) |
| 89 #define SCU_CONFIG_0_CPU_NUM_RANGE 1:0 |
| 90 #define SCU_CONFIG_0_CPU_NUM_WOFFSET 0x0 |
| 91 #define SCU_CONFIG_0_CPU_NUM_DEFAULT _MK_MASK_CONST(0x0) |
| 92 #define SCU_CONFIG_0_CPU_NUM_DEFAULT_MASK _MK_MASK_CONST(0
x3) |
| 93 #define SCU_CONFIG_0_CPU_NUM_SW_DEFAULT _MK_MASK_CONST(0x0) |
| 94 #define SCU_CONFIG_0_CPU_NUM_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 95 #define SCU_CONFIG_0_CPU_NUM_INIT_ENUM ONE |
| 96 #define SCU_CONFIG_0_CPU_NUM_ONE _MK_ENUM_CONST(0) |
| 97 #define SCU_CONFIG_0_CPU_NUM_TWO _MK_ENUM_CONST(1) |
| 98 #define SCU_CONFIG_0_CPU_NUM_THREE _MK_ENUM_CONST(2) |
| 99 #define SCU_CONFIG_0_CPU_NUM_FOUR _MK_ENUM_CONST(3) |
| 100 |
| 101 // define SMP mode for core 0 |
| 102 #define SCU_CONFIG_0_CPU0_SMP_SHIFT _MK_SHIFT_CONST(4) |
| 103 #define SCU_CONFIG_0_CPU0_SMP_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONFIG_0_CPU0_SMP_SHIFT) |
| 104 #define SCU_CONFIG_0_CPU0_SMP_RANGE 4:4 |
| 105 #define SCU_CONFIG_0_CPU0_SMP_WOFFSET 0x0 |
| 106 #define SCU_CONFIG_0_CPU0_SMP_DEFAULT _MK_MASK_CONST(0x0) |
| 107 #define SCU_CONFIG_0_CPU0_SMP_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 108 #define SCU_CONFIG_0_CPU0_SMP_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 109 #define SCU_CONFIG_0_CPU0_SMP_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 110 |
| 111 // core 1 |
| 112 #define SCU_CONFIG_0_CPU1_SMP_SHIFT _MK_SHIFT_CONST(5) |
| 113 #define SCU_CONFIG_0_CPU1_SMP_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONFIG_0_CPU1_SMP_SHIFT) |
| 114 #define SCU_CONFIG_0_CPU1_SMP_RANGE 5:5 |
| 115 #define SCU_CONFIG_0_CPU1_SMP_WOFFSET 0x0 |
| 116 #define SCU_CONFIG_0_CPU1_SMP_DEFAULT _MK_MASK_CONST(0x0) |
| 117 #define SCU_CONFIG_0_CPU1_SMP_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 118 #define SCU_CONFIG_0_CPU1_SMP_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 119 #define SCU_CONFIG_0_CPU1_SMP_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 120 |
| 121 // core 2 |
| 122 #define SCU_CONFIG_0_CPU2_SMP_SHIFT _MK_SHIFT_CONST(6) |
| 123 #define SCU_CONFIG_0_CPU2_SMP_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONFIG_0_CPU2_SMP_SHIFT) |
| 124 #define SCU_CONFIG_0_CPU2_SMP_RANGE 6:6 |
| 125 #define SCU_CONFIG_0_CPU2_SMP_WOFFSET 0x0 |
| 126 #define SCU_CONFIG_0_CPU2_SMP_DEFAULT _MK_MASK_CONST(0x0) |
| 127 #define SCU_CONFIG_0_CPU2_SMP_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 128 #define SCU_CONFIG_0_CPU2_SMP_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 129 #define SCU_CONFIG_0_CPU2_SMP_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 130 |
| 131 // core 3 |
| 132 #define SCU_CONFIG_0_CPU3_SMP_SHIFT _MK_SHIFT_CONST(7) |
| 133 #define SCU_CONFIG_0_CPU3_SMP_FIELD (_MK_MASK_CONST(0x1) <<
SCU_CONFIG_0_CPU3_SMP_SHIFT) |
| 134 #define SCU_CONFIG_0_CPU3_SMP_RANGE 7:7 |
| 135 #define SCU_CONFIG_0_CPU3_SMP_WOFFSET 0x0 |
| 136 #define SCU_CONFIG_0_CPU3_SMP_DEFAULT _MK_MASK_CONST(0x0) |
| 137 #define SCU_CONFIG_0_CPU3_SMP_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 138 #define SCU_CONFIG_0_CPU3_SMP_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 139 #define SCU_CONFIG_0_CPU3_SMP_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 140 |
| 141 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SHIFT _MK_SHIFT_CONST(
8) |
| 142 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_FIELD (_MK_MASK_CONST(
0x3) << SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SHIFT) |
| 143 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_RANGE 9:8 |
| 144 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_WOFFSET 0x0 |
| 145 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_DEFAULT _MK_MASK_CONST(0
x3) |
| 146 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 147 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 148 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 149 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_INIT_ENUM T64KB |
| 150 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T16KB _MK_ENUM_CONST(0
) |
| 151 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T32KB _MK_ENUM_CONST(1
) |
| 152 #define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T64KB _MK_ENUM_CONST(3
) |
| 153 |
| 154 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SHIFT _MK_SHIFT_CONST(
10) |
| 155 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_FIELD (_MK_MASK_CONST(
0x3) << SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SHIFT) |
| 156 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_RANGE 11:10 |
| 157 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_WOFFSET 0x0 |
| 158 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_DEFAULT _MK_MASK_CONST(0
x3) |
| 159 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 160 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 161 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 162 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_INIT_ENUM T64KB |
| 163 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T16KB _MK_ENUM_CONST(0
) |
| 164 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T32KB _MK_ENUM_CONST(1
) |
| 165 #define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T64KB _MK_ENUM_CONST(3
) |
| 166 |
| 167 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SHIFT _MK_SHIFT_CONST(
12) |
| 168 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_FIELD (_MK_MASK_CONST(
0x3) << SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SHIFT) |
| 169 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_RANGE 13:12 |
| 170 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_WOFFSET 0x0 |
| 171 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_DEFAULT _MK_MASK_CONST(0
x3) |
| 172 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 173 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 174 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 175 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_INIT_ENUM T64KB |
| 176 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T16KB _MK_ENUM_CONST(0
) |
| 177 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T32KB _MK_ENUM_CONST(1
) |
| 178 #define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T64KB _MK_ENUM_CONST(3
) |
| 179 |
| 180 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SHIFT _MK_SHIFT_CONST(
14) |
| 181 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_FIELD (_MK_MASK_CONST(
0x3) << SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SHIFT) |
| 182 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_RANGE 15:14 |
| 183 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_WOFFSET 0x0 |
| 184 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_DEFAULT _MK_MASK_CONST(0
x3) |
| 185 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 186 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 187 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 188 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_INIT_ENUM T64KB |
| 189 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T16KB _MK_ENUM_CONST(0
) |
| 190 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T32KB _MK_ENUM_CONST(1
) |
| 191 #define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T64KB _MK_ENUM_CONST(3
) |
| 192 |
| 193 |
| 194 // Register SCU_POWER_STATUS_0 |
| 195 #define SCU_POWER_STATUS_0 _MK_ADDR_CONST(0x8) |
| 196 #define SCU_POWER_STATUS_0_SECURE 0x0 |
| 197 #define SCU_POWER_STATUS_0_WORD_COUNT 0x1 |
| 198 #define SCU_POWER_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 199 #define SCU_POWER_STATUS_0_RESET_MASK _MK_MASK_CONST(0x3030303
) |
| 200 #define SCU_POWER_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 201 #define SCU_POWER_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 202 #define SCU_POWER_STATUS_0_READ_MASK _MK_MASK_CONST(0x3030303
) |
| 203 #define SCU_POWER_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x3030303
) |
| 204 #define SCU_POWER_STATUS_0_CPU0_STATUS_SHIFT _MK_SHIFT_CONST(
0) |
| 205 #define SCU_POWER_STATUS_0_CPU0_STATUS_FIELD (_MK_MASK_CONST(
0x3) << SCU_POWER_STATUS_0_CPU0_STATUS_SHIFT) |
| 206 #define SCU_POWER_STATUS_0_CPU0_STATUS_RANGE 1:0 |
| 207 #define SCU_POWER_STATUS_0_CPU0_STATUS_WOFFSET 0x0 |
| 208 #define SCU_POWER_STATUS_0_CPU0_STATUS_DEFAULT _MK_MASK_CONST(0
x0) |
| 209 #define SCU_POWER_STATUS_0_CPU0_STATUS_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 210 #define SCU_POWER_STATUS_0_CPU0_STATUS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 211 #define SCU_POWER_STATUS_0_CPU0_STATUS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 212 #define SCU_POWER_STATUS_0_CPU0_STATUS_INIT_ENUM NORMAL |
| 213 #define SCU_POWER_STATUS_0_CPU0_STATUS_NORMAL _MK_ENUM_CONST(0
) |
| 214 #define SCU_POWER_STATUS_0_CPU0_STATUS_DORMANT _MK_ENUM_CONST(2
) |
| 215 #define SCU_POWER_STATUS_0_CPU0_STATUS_PWROFF _MK_ENUM_CONST(3
) |
| 216 |
| 217 #define SCU_POWER_STATUS_0_CPU1_STATUS_SHIFT _MK_SHIFT_CONST(
8) |
| 218 #define SCU_POWER_STATUS_0_CPU1_STATUS_FIELD (_MK_MASK_CONST(
0x3) << SCU_POWER_STATUS_0_CPU1_STATUS_SHIFT) |
| 219 #define SCU_POWER_STATUS_0_CPU1_STATUS_RANGE 9:8 |
| 220 #define SCU_POWER_STATUS_0_CPU1_STATUS_WOFFSET 0x0 |
| 221 #define SCU_POWER_STATUS_0_CPU1_STATUS_DEFAULT _MK_MASK_CONST(0
x0) |
| 222 #define SCU_POWER_STATUS_0_CPU1_STATUS_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 223 #define SCU_POWER_STATUS_0_CPU1_STATUS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 224 #define SCU_POWER_STATUS_0_CPU1_STATUS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 225 #define SCU_POWER_STATUS_0_CPU1_STATUS_INIT_ENUM NORMAL |
| 226 #define SCU_POWER_STATUS_0_CPU1_STATUS_NORMAL _MK_ENUM_CONST(0
) |
| 227 #define SCU_POWER_STATUS_0_CPU1_STATUS_DORMANT _MK_ENUM_CONST(2
) |
| 228 #define SCU_POWER_STATUS_0_CPU1_STATUS_PWROFF _MK_ENUM_CONST(3
) |
| 229 |
| 230 #define SCU_POWER_STATUS_0_CPU2_STATUS_SHIFT _MK_SHIFT_CONST(
16) |
| 231 #define SCU_POWER_STATUS_0_CPU2_STATUS_FIELD (_MK_MASK_CONST(
0x3) << SCU_POWER_STATUS_0_CPU2_STATUS_SHIFT) |
| 232 #define SCU_POWER_STATUS_0_CPU2_STATUS_RANGE 17:16 |
| 233 #define SCU_POWER_STATUS_0_CPU2_STATUS_WOFFSET 0x0 |
| 234 #define SCU_POWER_STATUS_0_CPU2_STATUS_DEFAULT _MK_MASK_CONST(0
x0) |
| 235 #define SCU_POWER_STATUS_0_CPU2_STATUS_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 236 #define SCU_POWER_STATUS_0_CPU2_STATUS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 237 #define SCU_POWER_STATUS_0_CPU2_STATUS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 238 #define SCU_POWER_STATUS_0_CPU2_STATUS_INIT_ENUM NORMAL |
| 239 #define SCU_POWER_STATUS_0_CPU2_STATUS_NORMAL _MK_ENUM_CONST(0
) |
| 240 #define SCU_POWER_STATUS_0_CPU2_STATUS_DORMANT _MK_ENUM_CONST(2
) |
| 241 #define SCU_POWER_STATUS_0_CPU2_STATUS_PWROFF _MK_ENUM_CONST(3
) |
| 242 |
| 243 #define SCU_POWER_STATUS_0_CPU3_STATUS_SHIFT _MK_SHIFT_CONST(
24) |
| 244 #define SCU_POWER_STATUS_0_CPU3_STATUS_FIELD (_MK_MASK_CONST(
0x3) << SCU_POWER_STATUS_0_CPU3_STATUS_SHIFT) |
| 245 #define SCU_POWER_STATUS_0_CPU3_STATUS_RANGE 25:24 |
| 246 #define SCU_POWER_STATUS_0_CPU3_STATUS_WOFFSET 0x0 |
| 247 #define SCU_POWER_STATUS_0_CPU3_STATUS_DEFAULT _MK_MASK_CONST(0
x0) |
| 248 #define SCU_POWER_STATUS_0_CPU3_STATUS_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 249 #define SCU_POWER_STATUS_0_CPU3_STATUS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 250 #define SCU_POWER_STATUS_0_CPU3_STATUS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 251 #define SCU_POWER_STATUS_0_CPU3_STATUS_INIT_ENUM NORMAL |
| 252 #define SCU_POWER_STATUS_0_CPU3_STATUS_NORMAL _MK_ENUM_CONST(0
) |
| 253 #define SCU_POWER_STATUS_0_CPU3_STATUS_DORMANT _MK_ENUM_CONST(2
) |
| 254 #define SCU_POWER_STATUS_0_CPU3_STATUS_PWROFF _MK_ENUM_CONST(3
) |
| 255 |
| 256 |
| 257 // Register SCU_INVALID_ALL_0 |
| 258 #define SCU_INVALID_ALL_0 _MK_ADDR_CONST(0xc) |
| 259 #define SCU_INVALID_ALL_0_SECURE 0x0 |
| 260 #define SCU_INVALID_ALL_0_WORD_COUNT 0x1 |
| 261 #define SCU_INVALID_ALL_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 262 #define SCU_INVALID_ALL_0_RESET_MASK _MK_MASK_CONST(0xffff) |
| 263 #define SCU_INVALID_ALL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 264 #define SCU_INVALID_ALL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 265 #define SCU_INVALID_ALL_0_READ_MASK _MK_MASK_CONST(0xffff) |
| 266 #define SCU_INVALID_ALL_0_WRITE_MASK _MK_MASK_CONST(0xffff) |
| 267 #define SCU_INVALID_ALL_0_CPU0_WAYS_SHIFT _MK_SHIFT_CONST(
0) |
| 268 #define SCU_INVALID_ALL_0_CPU0_WAYS_FIELD (_MK_MASK_CONST(
0xf) << SCU_INVALID_ALL_0_CPU0_WAYS_SHIFT) |
| 269 #define SCU_INVALID_ALL_0_CPU0_WAYS_RANGE 3:0 |
| 270 #define SCU_INVALID_ALL_0_CPU0_WAYS_WOFFSET 0x0 |
| 271 #define SCU_INVALID_ALL_0_CPU0_WAYS_DEFAULT _MK_MASK_CONST(0
x0) |
| 272 #define SCU_INVALID_ALL_0_CPU0_WAYS_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 273 #define SCU_INVALID_ALL_0_CPU0_WAYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 274 #define SCU_INVALID_ALL_0_CPU0_WAYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 275 |
| 276 #define SCU_INVALID_ALL_0_CPU1_WAYS_SHIFT _MK_SHIFT_CONST(
4) |
| 277 #define SCU_INVALID_ALL_0_CPU1_WAYS_FIELD (_MK_MASK_CONST(
0xf) << SCU_INVALID_ALL_0_CPU1_WAYS_SHIFT) |
| 278 #define SCU_INVALID_ALL_0_CPU1_WAYS_RANGE 7:4 |
| 279 #define SCU_INVALID_ALL_0_CPU1_WAYS_WOFFSET 0x0 |
| 280 #define SCU_INVALID_ALL_0_CPU1_WAYS_DEFAULT _MK_MASK_CONST(0
x0) |
| 281 #define SCU_INVALID_ALL_0_CPU1_WAYS_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 282 #define SCU_INVALID_ALL_0_CPU1_WAYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 283 #define SCU_INVALID_ALL_0_CPU1_WAYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 284 |
| 285 #define SCU_INVALID_ALL_0_CPU2_WAYS_SHIFT _MK_SHIFT_CONST(
8) |
| 286 #define SCU_INVALID_ALL_0_CPU2_WAYS_FIELD (_MK_MASK_CONST(
0xf) << SCU_INVALID_ALL_0_CPU2_WAYS_SHIFT) |
| 287 #define SCU_INVALID_ALL_0_CPU2_WAYS_RANGE 11:8 |
| 288 #define SCU_INVALID_ALL_0_CPU2_WAYS_WOFFSET 0x0 |
| 289 #define SCU_INVALID_ALL_0_CPU2_WAYS_DEFAULT _MK_MASK_CONST(0
x0) |
| 290 #define SCU_INVALID_ALL_0_CPU2_WAYS_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 291 #define SCU_INVALID_ALL_0_CPU2_WAYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 292 #define SCU_INVALID_ALL_0_CPU2_WAYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 293 |
| 294 #define SCU_INVALID_ALL_0_CPU3_WAYS_SHIFT _MK_SHIFT_CONST(
12) |
| 295 #define SCU_INVALID_ALL_0_CPU3_WAYS_FIELD (_MK_MASK_CONST(
0xf) << SCU_INVALID_ALL_0_CPU3_WAYS_SHIFT) |
| 296 #define SCU_INVALID_ALL_0_CPU3_WAYS_RANGE 15:12 |
| 297 #define SCU_INVALID_ALL_0_CPU3_WAYS_WOFFSET 0x0 |
| 298 #define SCU_INVALID_ALL_0_CPU3_WAYS_DEFAULT _MK_MASK_CONST(0
x0) |
| 299 #define SCU_INVALID_ALL_0_CPU3_WAYS_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 300 #define SCU_INVALID_ALL_0_CPU3_WAYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 301 #define SCU_INVALID_ALL_0_CPU3_WAYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 302 |
| 303 |
| 304 // Reserved address 16 [0x10] |
| 305 |
| 306 // Reserved address 20 [0x14] |
| 307 |
| 308 // Reserved address 24 [0x18] |
| 309 |
| 310 // Reserved address 28 [0x1c] |
| 311 |
| 312 // Reserved address 32 [0x20] |
| 313 |
| 314 // Reserved address 36 [0x24] |
| 315 |
| 316 // Reserved address 40 [0x28] |
| 317 |
| 318 // Reserved address 44 [0x2c] |
| 319 |
| 320 // Reserved address 48 [0x30] |
| 321 |
| 322 // Reserved address 52 [0x34] |
| 323 |
| 324 // Reserved address 56 [0x38] |
| 325 |
| 326 // Reserved address 60 [0x3c] |
| 327 |
| 328 // Register SCU_FILTER_START_0 |
| 329 #define SCU_FILTER_START_0 _MK_ADDR_CONST(0x40) |
| 330 #define SCU_FILTER_START_0_SECURE 0x0 |
| 331 #define SCU_FILTER_START_0_WORD_COUNT 0x1 |
| 332 #define SCU_FILTER_START_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 333 #define SCU_FILTER_START_0_RESET_MASK _MK_MASK_CONST(0xfff0000
0) |
| 334 #define SCU_FILTER_START_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 335 #define SCU_FILTER_START_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 336 #define SCU_FILTER_START_0_READ_MASK _MK_MASK_CONST(0xfff0000
0) |
| 337 #define SCU_FILTER_START_0_WRITE_MASK _MK_MASK_CONST(0xfff0000
0) |
| 338 #define SCU_FILTER_START_0_ADDR_SHIFT _MK_SHIFT_CONST(20) |
| 339 #define SCU_FILTER_START_0_ADDR_FIELD (_MK_MASK_CONST(0xfff) <
< SCU_FILTER_START_0_ADDR_SHIFT) |
| 340 #define SCU_FILTER_START_0_ADDR_RANGE 31:20 |
| 341 #define SCU_FILTER_START_0_ADDR_WOFFSET 0x0 |
| 342 #define SCU_FILTER_START_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) |
| 343 #define SCU_FILTER_START_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0
xfff) |
| 344 #define SCU_FILTER_START_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 345 #define SCU_FILTER_START_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 346 |
| 347 |
| 348 // Register SCU_FILTER_END_0 |
| 349 #define SCU_FILTER_END_0 _MK_ADDR_CONST(0x44) |
| 350 #define SCU_FILTER_END_0_SECURE 0x0 |
| 351 #define SCU_FILTER_END_0_WORD_COUNT 0x1 |
| 352 #define SCU_FILTER_END_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 353 #define SCU_FILTER_END_0_RESET_MASK _MK_MASK_CONST(0xfff0000
0) |
| 354 #define SCU_FILTER_END_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 355 #define SCU_FILTER_END_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 356 #define SCU_FILTER_END_0_READ_MASK _MK_MASK_CONST(0xfff0000
0) |
| 357 #define SCU_FILTER_END_0_WRITE_MASK _MK_MASK_CONST(0xfff0000
0) |
| 358 #define SCU_FILTER_END_0_ADDR_SHIFT _MK_SHIFT_CONST(20) |
| 359 #define SCU_FILTER_END_0_ADDR_FIELD (_MK_MASK_CONST(0xfff) <
< SCU_FILTER_END_0_ADDR_SHIFT) |
| 360 #define SCU_FILTER_END_0_ADDR_RANGE 31:20 |
| 361 #define SCU_FILTER_END_0_ADDR_WOFFSET 0x0 |
| 362 #define SCU_FILTER_END_0_ADDR_DEFAULT _MK_MASK_CONST(0x0) |
| 363 #define SCU_FILTER_END_0_ADDR_DEFAULT_MASK _MK_MASK_CONST(0
xfff) |
| 364 #define SCU_FILTER_END_0_ADDR_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 365 #define SCU_FILTER_END_0_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 366 |
| 367 |
| 368 // Reserved address 72 [0x48] |
| 369 |
| 370 // Reserved address 76 [0x4c] |
| 371 |
| 372 // Register SCU_ACCESS_CONTROL_0 |
| 373 #define SCU_ACCESS_CONTROL_0 _MK_ADDR_CONST(0x50) |
| 374 #define SCU_ACCESS_CONTROL_0_SECURE 0x0 |
| 375 #define SCU_ACCESS_CONTROL_0_WORD_COUNT 0x1 |
| 376 #define SCU_ACCESS_CONTROL_0_RESET_VAL _MK_MASK_CONST(0xf) |
| 377 #define SCU_ACCESS_CONTROL_0_RESET_MASK _MK_MASK_CONST(0
xf) |
| 378 #define SCU_ACCESS_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 379 #define SCU_ACCESS_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 380 #define SCU_ACCESS_CONTROL_0_READ_MASK _MK_MASK_CONST(0xf) |
| 381 #define SCU_ACCESS_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0
xf) |
| 382 // 1: access_allowed |
| 383 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT _MK_SHIFT_CONST(
0) |
| 384 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_FIELD (_MK_MASK_CONST(
0x1) << SCU_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT) |
| 385 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_RANGE 0:0 |
| 386 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_WOFFSET 0x0 |
| 387 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT _MK_MASK_CONST(0
x1) |
| 388 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 389 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 390 #define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 391 |
| 392 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT _MK_SHIFT_CONST(
1) |
| 393 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_FIELD (_MK_MASK_CONST(
0x1) << SCU_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT) |
| 394 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_RANGE 1:1 |
| 395 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_WOFFSET 0x0 |
| 396 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT _MK_MASK_CONST(0
x1) |
| 397 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 398 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 399 #define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 400 |
| 401 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT _MK_SHIFT_CONST(
2) |
| 402 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_FIELD (_MK_MASK_CONST(
0x1) << SCU_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT) |
| 403 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_RANGE 2:2 |
| 404 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_WOFFSET 0x0 |
| 405 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT _MK_MASK_CONST(0
x1) |
| 406 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 407 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 408 #define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 409 |
| 410 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT _MK_SHIFT_CONST(
3) |
| 411 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_FIELD (_MK_MASK_CONST(
0x1) << SCU_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT) |
| 412 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_RANGE 3:3 |
| 413 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_WOFFSET 0x0 |
| 414 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT _MK_MASK_CONST(0
x1) |
| 415 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 416 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 417 #define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 418 |
| 419 |
| 420 // Register SCU_SECURE_ACCESS_CONTROL_0 |
| 421 #define SCU_SECURE_ACCESS_CONTROL_0 _MK_ADDR_CONST(0x54) |
| 422 #define SCU_SECURE_ACCESS_CONTROL_0_SECURE 0x0 |
| 423 #define SCU_SECURE_ACCESS_CONTROL_0_WORD_COUNT 0x1 |
| 424 #define SCU_SECURE_ACCESS_CONTROL_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 425 #define SCU_SECURE_ACCESS_CONTROL_0_RESET_MASK _MK_MASK_CONST(0
xfff) |
| 426 #define SCU_SECURE_ACCESS_CONTROL_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 427 #define SCU_SECURE_ACCESS_CONTROL_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 428 #define SCU_SECURE_ACCESS_CONTROL_0_READ_MASK _MK_MASK_CONST(0
xfff) |
| 429 #define SCU_SECURE_ACCESS_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0
xfff) |
| 430 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT _MK_SHIF
T_CONST(0) |
| 431 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT) |
| 432 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_RANGE 0:0 |
| 433 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_WOFFSET 0x0 |
| 434 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT _MK_MASK
_CONST(0x0) |
| 435 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 436 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 437 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 438 |
| 439 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT _MK_SHIF
T_CONST(1) |
| 440 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT) |
| 441 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_RANGE 1:1 |
| 442 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_WOFFSET 0x0 |
| 443 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT _MK_MASK
_CONST(0x0) |
| 444 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 445 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 446 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 447 |
| 448 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT _MK_SHIF
T_CONST(2) |
| 449 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT) |
| 450 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_RANGE 2:2 |
| 451 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_WOFFSET 0x0 |
| 452 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT _MK_MASK
_CONST(0x0) |
| 453 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 454 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 455 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 456 |
| 457 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT _MK_SHIF
T_CONST(3) |
| 458 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT) |
| 459 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_RANGE 3:3 |
| 460 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_WOFFSET 0x0 |
| 461 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT _MK_MASK
_CONST(0x0) |
| 462 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 463 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 464 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 465 |
| 466 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SHIFT _MK_SHIF
T_CONST(4) |
| 467 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SHIFT) |
| 468 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_RANGE 4:4 |
| 469 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_WOFFSET 0x0 |
| 470 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_DEFAULT _MK_MASK
_CONST(0x0) |
| 471 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 472 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 473 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 474 |
| 475 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SHIFT _MK_SHIF
T_CONST(5) |
| 476 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SHIFT) |
| 477 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_RANGE 5:5 |
| 478 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_WOFFSET 0x0 |
| 479 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_DEFAULT _MK_MASK
_CONST(0x0) |
| 480 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 481 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 482 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 483 |
| 484 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SHIFT _MK_SHIF
T_CONST(6) |
| 485 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SHIFT) |
| 486 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_RANGE 6:6 |
| 487 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_WOFFSET 0x0 |
| 488 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_DEFAULT _MK_MASK
_CONST(0x0) |
| 489 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 490 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 491 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 492 |
| 493 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SHIFT _MK_SHIF
T_CONST(7) |
| 494 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_FIELD (_MK_MAS
K_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SHIFT) |
| 495 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_RANGE 7:7 |
| 496 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_WOFFSET 0x0 |
| 497 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_DEFAULT _MK_MASK
_CONST(0x0) |
| 498 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 499 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 500 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 501 |
| 502 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SHIFT
_MK_SHIFT_CONST(8) |
| 503 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_FIELD
(_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SHIFT) |
| 504 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_RANGE
8:8 |
| 505 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_WOFFSET
0x0 |
| 506 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_DEFAULT
_MK_MASK_CONST(0x0) |
| 507 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 508 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 509 #define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 510 |
| 511 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SHIFT
_MK_SHIFT_CONST(9) |
| 512 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_FIELD
(_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SHIFT) |
| 513 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_RANGE
9:9 |
| 514 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_WOFFSET
0x0 |
| 515 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_DEFAULT
_MK_MASK_CONST(0x0) |
| 516 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 517 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 518 #define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 519 |
| 520 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SHIFT
_MK_SHIFT_CONST(10) |
| 521 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_FIELD
(_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SHIFT) |
| 522 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_RANGE
10:10 |
| 523 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_WOFFSET
0x0 |
| 524 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_DEFAULT
_MK_MASK_CONST(0x0) |
| 525 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 526 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 527 #define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 528 |
| 529 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SHIFT
_MK_SHIFT_CONST(11) |
| 530 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_FIELD
(_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SHIFT) |
| 531 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_RANGE
11:11 |
| 532 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_WOFFSET
0x0 |
| 533 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_DEFAULT
_MK_MASK_CONST(0x0) |
| 534 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 535 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 536 #define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 537 |
| 538 |
| 539 // |
| 540 // REGISTER LIST |
| 541 // |
| 542 #define LIST_ARSCU_REGS(_op_) \ |
| 543 _op_(SCU_CONTROL_0) \ |
| 544 _op_(SCU_CONFIG_0) \ |
| 545 _op_(SCU_POWER_STATUS_0) \ |
| 546 _op_(SCU_INVALID_ALL_0) \ |
| 547 _op_(SCU_FILTER_START_0) \ |
| 548 _op_(SCU_FILTER_END_0) \ |
| 549 _op_(SCU_ACCESS_CONTROL_0) \ |
| 550 _op_(SCU_SECURE_ACCESS_CONTROL_0) |
| 551 |
| 552 |
| 553 // |
| 554 // ADDRESS SPACES |
| 555 // |
| 556 |
| 557 #define BASE_ADDRESS_SCU 0x00000000 |
| 558 |
| 559 // |
| 560 // ARSCU REGISTER BANKS |
| 561 // |
| 562 |
| 563 #define SCU0_FIRST_REG 0x0000 // SCU_CONTROL_0 |
| 564 #define SCU0_LAST_REG 0x000c // SCU_INVALID_ALL_0 |
| 565 #define SCU1_FIRST_REG 0x0040 // SCU_FILTER_START_0 |
| 566 #define SCU1_LAST_REG 0x0044 // SCU_FILTER_END_0 |
| 567 #define SCU2_FIRST_REG 0x0050 // SCU_ACCESS_CONTROL_0 |
| 568 #define SCU2_LAST_REG 0x0054 // SCU_SECURE_ACCESS_CONTROL_0 |
| 569 |
| 570 #ifndef _MK_SHIFT_CONST |
| 571 #define _MK_SHIFT_CONST(_constant_) _constant_ |
| 572 #endif |
| 573 #ifndef _MK_MASK_CONST |
| 574 #define _MK_MASK_CONST(_constant_) _constant_ |
| 575 #endif |
| 576 #ifndef _MK_ENUM_CONST |
| 577 #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) |
| 578 #endif |
| 579 #ifndef _MK_ADDR_CONST |
| 580 #define _MK_ADDR_CONST(_constant_) _constant_ |
| 581 #endif |
| 582 |
| 583 #endif // ifndef ___ARSCU_H_INC_ |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 3256004:
[ARM] tegra: add nvos/nvrm/nvmap drivers (Closed)
Base URL: ssh://git@gitrw.chromium.org/kernel.git