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| 1 /* |
| 2 * Copyright (c) 2009 NVIDIA Corporation. |
| 3 * All rights reserved. |
| 4 * |
| 5 * Redistribution and use in source and binary forms, with or without |
| 6 * modification, are permitted provided that the following conditions are met: |
| 7 * |
| 8 * Redistributions of source code must retain the above copyright notice, |
| 9 * this list of conditions and the following disclaimer. |
| 10 * |
| 11 * Redistributions in binary form must reproduce the above copyright notice, |
| 12 * this list of conditions and the following disclaimer in the documentation |
| 13 * and/or other materials provided with the distribution. |
| 14 * |
| 15 * Neither the name of the NVIDIA Corporation nor the names of its contributors |
| 16 * may be used to endorse or promote products derived from this software |
| 17 * without specific prior written permission. |
| 18 * |
| 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 * POSSIBILITY OF SUCH DAMAGE. |
| 30 * |
| 31 */ |
| 32 // |
| 33 // DO NOT EDIT - generated by simspec! |
| 34 // |
| 35 |
| 36 #ifndef ___ARFLOW_CTLR_H_INC_ |
| 37 #define ___ARFLOW_CTLR_H_INC_ |
| 38 |
| 39 // Register FLOW_CTLR_HALT_CPU_EVENTS_0 |
| 40 #define FLOW_CTLR_HALT_CPU_EVENTS_0 _MK_ADDR_CONST(0x0) |
| 41 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SECURE 0x0 |
| 42 #define FLOW_CTLR_HALT_CPU_EVENTS_0_WORD_COUNT 0x1 |
| 43 #define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 44 #define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 45 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 46 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 47 #define FLOW_CTLR_HALT_CPU_EVENTS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 48 #define FLOW_CTLR_HALT_CPU_EVENTS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 49 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT _MK_SHIFT_CONST(
29) |
| 50 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FIELD (_MK_MASK_CONST(
0x7) << FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT) |
| 51 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_RANGE 31:29 |
| 52 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_WOFFSET 0x0 |
| 53 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT _MK_MASK
_CONST(0x0) |
| 54 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT_MASK _MK_MASK
_CONST(0x7) |
| 55 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 56 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 57 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_NONE _MK_ENUM
_CONST(0) |
| 58 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT
_MK_ENUM_CONST(1) |
| 59 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT
_MK_ENUM_CONST(2) |
| 60 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT
_MK_ENUM_CONST(3) |
| 61 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ
_MK_ENUM_CONST(4) |
| 62 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT
_MK_ENUM_CONST(5) |
| 63 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ
_MK_ENUM_CONST(6) |
| 64 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM
_CONST(2) |
| 65 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT
_MK_ENUM_CONST(3) |
| 66 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT
_MK_ENUM_CONST(4) |
| 67 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT
_MK_ENUM_CONST(5) |
| 68 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT
_MK_ENUM_CONST(6) |
| 69 |
| 70 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT _MK_SHIFT_CONST(
28) |
| 71 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT) |
| 72 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_RANGE 28:28 |
| 73 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_WOFFSET 0x0 |
| 74 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT _MK_MASK
_CONST(0x0) |
| 75 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 76 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 77 #define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 78 |
| 79 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT _MK_SHIFT_CONST(
27) |
| 80 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT) |
| 81 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_RANGE 27:27 |
| 82 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_WOFFSET 0x0 |
| 83 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT _MK_MASK
_CONST(0x0) |
| 84 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 85 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 86 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 87 |
| 88 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT _MK_SHIFT_CONST(
26) |
| 89 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT) |
| 90 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_RANGE 26:26 |
| 91 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_WOFFSET 0x0 |
| 92 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT _MK_MASK
_CONST(0x0) |
| 93 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 94 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 95 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 96 |
| 97 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT _MK_SHIFT_CONST(
25) |
| 98 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT) |
| 99 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_RANGE 25:25 |
| 100 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_WOFFSET 0x0 |
| 101 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 102 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 103 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 104 #define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 105 |
| 106 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT _MK_SHIFT_CONST(
24) |
| 107 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT) |
| 108 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_RANGE 24:24 |
| 109 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_WOFFSET 0x0 |
| 110 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 111 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 112 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 113 #define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 114 |
| 115 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT _MK_SHIFT_CONST(
23) |
| 116 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT) |
| 117 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_RANGE 23:23 |
| 118 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_WOFFSET 0x0 |
| 119 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT _MK_MASK_CONST(0
x0) |
| 120 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 121 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 122 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 123 |
| 124 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT _MK_SHIFT_CONST(
22) |
| 125 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT) |
| 126 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_RANGE 22:22 |
| 127 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_WOFFSET 0x0 |
| 128 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT _MK_MASK
_CONST(0x0) |
| 129 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 130 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 131 #define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 132 |
| 133 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT _MK_SHIFT_CONST(
21) |
| 134 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT) |
| 135 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_RANGE 21:21 |
| 136 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_WOFFSET 0x0 |
| 137 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT _MK_MASK
_CONST(0x0) |
| 138 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 139 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 140 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 141 |
| 142 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT _MK_SHIFT_CONST(
20) |
| 143 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT) |
| 144 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_RANGE 20:20 |
| 145 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_WOFFSET 0x0 |
| 146 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT _MK_MASK
_CONST(0x0) |
| 147 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 148 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 149 #define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 150 |
| 151 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT _MK_SHIFT_CONST(
19) |
| 152 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT) |
| 153 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_RANGE 19:19 |
| 154 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_WOFFSET 0x0 |
| 155 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT _MK_MASK
_CONST(0x0) |
| 156 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 157 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 158 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 159 |
| 160 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT _MK_SHIFT_CONST(
18) |
| 161 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT) |
| 162 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_RANGE 18:18 |
| 163 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_WOFFSET 0x0 |
| 164 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT _MK_MASK
_CONST(0x0) |
| 165 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 166 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 167 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 168 |
| 169 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT _MK_SHIFT_CONST(
17) |
| 170 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT) |
| 171 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_RANGE 17:17 |
| 172 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_WOFFSET 0x0 |
| 173 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT _MK_MASK
_CONST(0x0) |
| 174 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 175 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 176 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 177 |
| 178 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT _MK_SHIFT_CONST(
16) |
| 179 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT) |
| 180 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_RANGE 16:16 |
| 181 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_WOFFSET 0x0 |
| 182 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT _MK_MASK
_CONST(0x0) |
| 183 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 184 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 185 #define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 186 |
| 187 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT _MK_SHIFT_CONST(
15) |
| 188 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT) |
| 189 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_RANGE 15:15 |
| 190 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_WOFFSET 0x0 |
| 191 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT _MK_MASK_CONST(0
x0) |
| 192 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 193 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 194 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 195 |
| 196 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT _MK_SHIFT_CONST(
14) |
| 197 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT) |
| 198 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_RANGE 14:14 |
| 199 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_WOFFSET 0x0 |
| 200 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT _MK_MASK_CONST(0
x0) |
| 201 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 202 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 203 #define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 204 |
| 205 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT _MK_SHIFT_CONST(
13) |
| 206 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT) |
| 207 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_RANGE 13:13 |
| 208 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_WOFFSET 0x0 |
| 209 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT _MK_MASK_CONST(0
x0) |
| 210 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 211 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 212 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 213 |
| 214 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT _MK_SHIFT_CONST(
12) |
| 215 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT) |
| 216 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_RANGE 12:12 |
| 217 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_WOFFSET 0x0 |
| 218 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT _MK_MASK_CONST(0
x0) |
| 219 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 220 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 221 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 222 |
| 223 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT _MK_SHIFT_CONST(
11) |
| 224 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT) |
| 225 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_RANGE 11:11 |
| 226 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_WOFFSET 0x0 |
| 227 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 228 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 229 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 230 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 231 |
| 232 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT _MK_SHIFT_CONST(
10) |
| 233 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT) |
| 234 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_RANGE 10:10 |
| 235 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_WOFFSET 0x0 |
| 236 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 237 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 238 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 239 #define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 240 |
| 241 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT _MK_SHIFT_CONST(
9) |
| 242 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT) |
| 243 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_RANGE 9:9 |
| 244 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_WOFFSET 0x0 |
| 245 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 246 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 247 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 248 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 249 |
| 250 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT _MK_SHIFT_CONST(
8) |
| 251 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT) |
| 252 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_RANGE 8:8 |
| 253 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_WOFFSET 0x0 |
| 254 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 255 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 256 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 257 #define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 258 |
| 259 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT _MK_SHIFT_CONST(
0) |
| 260 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_FIELD (_MK_MASK_CONST(
0xff) << FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT) |
| 261 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_RANGE 7:0 |
| 262 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_WOFFSET 0x0 |
| 263 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT _MK_MASK
_CONST(0x0) |
| 264 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 265 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 266 #define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 267 |
| 268 |
| 269 // Register FLOW_CTLR_HALT_COP_EVENTS_0 |
| 270 #define FLOW_CTLR_HALT_COP_EVENTS_0 _MK_ADDR_CONST(0x4) |
| 271 #define FLOW_CTLR_HALT_COP_EVENTS_0_SECURE 0x0 |
| 272 #define FLOW_CTLR_HALT_COP_EVENTS_0_WORD_COUNT 0x1 |
| 273 #define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 274 #define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 275 #define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 276 #define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 277 #define FLOW_CTLR_HALT_COP_EVENTS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 278 #define FLOW_CTLR_HALT_COP_EVENTS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 279 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT _MK_SHIFT_CONST(
29) |
| 280 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FIELD (_MK_MASK_CONST(
0x7) << FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT) |
| 281 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_RANGE 31:29 |
| 282 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_WOFFSET 0x0 |
| 283 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT _MK_MASK
_CONST(0x0) |
| 284 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT_MASK _MK_MASK
_CONST(0x7) |
| 285 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 286 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 287 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_NONE _MK_ENUM
_CONST(0) |
| 288 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT
_MK_ENUM_CONST(1) |
| 289 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT
_MK_ENUM_CONST(2) |
| 290 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT
_MK_ENUM_CONST(3) |
| 291 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ
_MK_ENUM_CONST(4) |
| 292 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT
_MK_ENUM_CONST(5) |
| 293 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ
_MK_ENUM_CONST(6) |
| 294 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP _MK_ENUM
_CONST(2) |
| 295 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT
_MK_ENUM_CONST(3) |
| 296 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT
_MK_ENUM_CONST(4) |
| 297 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT
_MK_ENUM_CONST(5) |
| 298 #define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT
_MK_ENUM_CONST(6) |
| 299 |
| 300 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT _MK_SHIFT_CONST(
28) |
| 301 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT) |
| 302 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_RANGE 28:28 |
| 303 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_WOFFSET 0x0 |
| 304 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT _MK_MASK
_CONST(0x0) |
| 305 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 306 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 307 #define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 308 |
| 309 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT _MK_SHIFT_CONST(
27) |
| 310 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT) |
| 311 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_RANGE 27:27 |
| 312 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_WOFFSET 0x0 |
| 313 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT _MK_MASK
_CONST(0x0) |
| 314 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 315 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 316 #define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 317 |
| 318 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT _MK_SHIFT_CONST(
26) |
| 319 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT) |
| 320 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_RANGE 26:26 |
| 321 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_WOFFSET 0x0 |
| 322 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT _MK_MASK
_CONST(0x0) |
| 323 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 324 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 325 #define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 326 |
| 327 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT _MK_SHIFT_CONST(
25) |
| 328 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT) |
| 329 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_RANGE 25:25 |
| 330 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_WOFFSET 0x0 |
| 331 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 332 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 333 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 334 #define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 335 |
| 336 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT _MK_SHIFT_CONST(
24) |
| 337 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT) |
| 338 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_RANGE 24:24 |
| 339 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_WOFFSET 0x0 |
| 340 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 341 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 342 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 343 #define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 344 |
| 345 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT _MK_SHIFT_CONST(
23) |
| 346 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT) |
| 347 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_RANGE 23:23 |
| 348 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_WOFFSET 0x0 |
| 349 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT _MK_MASK_CONST(0
x0) |
| 350 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 351 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 352 #define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 353 |
| 354 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT _MK_SHIFT_CONST(
22) |
| 355 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT) |
| 356 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_RANGE 22:22 |
| 357 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_WOFFSET 0x0 |
| 358 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT _MK_MASK
_CONST(0x0) |
| 359 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 360 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 361 #define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 362 |
| 363 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT _MK_SHIFT_CONST(
21) |
| 364 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT) |
| 365 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_RANGE 21:21 |
| 366 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_WOFFSET 0x0 |
| 367 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT _MK_MASK
_CONST(0x0) |
| 368 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 369 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 370 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 371 |
| 372 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT _MK_SHIFT_CONST(
20) |
| 373 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT) |
| 374 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_RANGE 20:20 |
| 375 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_WOFFSET 0x0 |
| 376 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT _MK_MASK
_CONST(0x0) |
| 377 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 378 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 379 #define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 380 |
| 381 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT _MK_SHIFT_CONST(
19) |
| 382 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT) |
| 383 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_RANGE 19:19 |
| 384 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_WOFFSET 0x0 |
| 385 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT _MK_MASK
_CONST(0x0) |
| 386 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 387 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 388 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 389 |
| 390 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT _MK_SHIFT_CONST(
18) |
| 391 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT) |
| 392 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_RANGE 18:18 |
| 393 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_WOFFSET 0x0 |
| 394 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT _MK_MASK
_CONST(0x0) |
| 395 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 396 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 397 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 398 |
| 399 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT _MK_SHIFT_CONST(
17) |
| 400 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT) |
| 401 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_RANGE 17:17 |
| 402 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_WOFFSET 0x0 |
| 403 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT _MK_MASK
_CONST(0x0) |
| 404 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 405 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 406 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 407 |
| 408 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT _MK_SHIFT_CONST(
16) |
| 409 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT) |
| 410 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_RANGE 16:16 |
| 411 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_WOFFSET 0x0 |
| 412 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT _MK_MASK
_CONST(0x0) |
| 413 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 414 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 415 #define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 416 |
| 417 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT _MK_SHIFT_CONST(
15) |
| 418 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT) |
| 419 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_RANGE 15:15 |
| 420 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_WOFFSET 0x0 |
| 421 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT _MK_MASK_CONST(0
x0) |
| 422 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 423 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 424 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 425 |
| 426 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT _MK_SHIFT_CONST(
14) |
| 427 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT) |
| 428 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_RANGE 14:14 |
| 429 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_WOFFSET 0x0 |
| 430 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT _MK_MASK_CONST(0
x0) |
| 431 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 432 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 433 #define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 434 |
| 435 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT _MK_SHIFT_CONST(
13) |
| 436 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT) |
| 437 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_RANGE 13:13 |
| 438 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_WOFFSET 0x0 |
| 439 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT _MK_MASK_CONST(0
x0) |
| 440 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 441 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 442 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 443 |
| 444 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT _MK_SHIFT_CONST(
12) |
| 445 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT) |
| 446 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_RANGE 12:12 |
| 447 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_WOFFSET 0x0 |
| 448 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT _MK_MASK_CONST(0
x0) |
| 449 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 450 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 451 #define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 452 |
| 453 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT _MK_SHIFT_CONST(
11) |
| 454 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT) |
| 455 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_RANGE 11:11 |
| 456 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_WOFFSET 0x0 |
| 457 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 458 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 459 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 460 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 461 |
| 462 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT _MK_SHIFT_CONST(
10) |
| 463 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT) |
| 464 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_RANGE 10:10 |
| 465 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_WOFFSET 0x0 |
| 466 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 467 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 468 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 469 #define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 470 |
| 471 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT _MK_SHIFT_CONST(
9) |
| 472 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT) |
| 473 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_RANGE 9:9 |
| 474 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_WOFFSET 0x0 |
| 475 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 476 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 477 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 478 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 479 |
| 480 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT _MK_SHIFT_CONST(
8) |
| 481 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT) |
| 482 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_RANGE 8:8 |
| 483 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_WOFFSET 0x0 |
| 484 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 485 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 486 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 487 #define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 488 |
| 489 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT _MK_SHIFT_CONST(
0) |
| 490 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_FIELD (_MK_MASK_CONST(
0xff) << FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT) |
| 491 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_RANGE 7:0 |
| 492 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_WOFFSET 0x0 |
| 493 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT _MK_MASK
_CONST(0x0) |
| 494 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 495 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 496 #define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 497 |
| 498 |
| 499 // Register FLOW_CTLR_CPU_CSR_0 |
| 500 #define FLOW_CTLR_CPU_CSR_0 _MK_ADDR_CONST(0x8) |
| 501 #define FLOW_CTLR_CPU_CSR_0_SECURE 0x0 |
| 502 #define FLOW_CTLR_CPU_CSR_0_WORD_COUNT 0x1 |
| 503 #define FLOW_CTLR_CPU_CSR_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 504 #define FLOW_CTLR_CPU_CSR_0_RESET_MASK _MK_MASK_CONST(0xffbc033
) |
| 505 #define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 506 #define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 507 #define FLOW_CTLR_CPU_CSR_0_READ_MASK _MK_MASK_CONST(0xffbc033
) |
| 508 #define FLOW_CTLR_CPU_CSR_0_WRITE_MASK _MK_MASK_CONST(0xc033) |
| 509 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT _MK_SHIFT_CONST(
24) |
| 510 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_FIELD (_MK_MASK_CONST(
0xf) << FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT) |
| 511 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_RANGE 27:24 |
| 512 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_WOFFSET 0x0 |
| 513 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT _MK_MASK_CONST(0
x0) |
| 514 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 515 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 516 #define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 517 |
| 518 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT _MK_SHIFT_CONST(
23) |
| 519 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT) |
| 520 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_RANGE 23:23 |
| 521 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_WOFFSET 0x0 |
| 522 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT _MK_MASK_CONST(0
x0) |
| 523 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 524 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 525 #define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 526 |
| 527 #define FLOW_CTLR_CPU_CSR_0_HALT_SHIFT _MK_SHIFT_CONST(22) |
| 528 #define FLOW_CTLR_CPU_CSR_0_HALT_FIELD (_MK_MASK_CONST(0x1) <<
FLOW_CTLR_CPU_CSR_0_HALT_SHIFT) |
| 529 #define FLOW_CTLR_CPU_CSR_0_HALT_RANGE 22:22 |
| 530 #define FLOW_CTLR_CPU_CSR_0_HALT_WOFFSET 0x0 |
| 531 #define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT _MK_MASK_CONST(0
x0) |
| 532 #define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 533 #define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 534 #define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 535 |
| 536 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT _MK_SHIFT_CONST(
21) |
| 537 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT) |
| 538 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_RANGE 21:21 |
| 539 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_WOFFSET 0x0 |
| 540 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT _MK_MASK_CONST(0
x0) |
| 541 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 542 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 543 #define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 544 |
| 545 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT _MK_SHIFT_CONST(
20) |
| 546 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT) |
| 547 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_RANGE 20:20 |
| 548 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_WOFFSET 0x0 |
| 549 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT _MK_MASK_CONST(0
x0) |
| 550 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 551 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 552 #define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 553 |
| 554 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT _MK_SHIFT_CONST(
19) |
| 555 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT) |
| 556 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_RANGE 19:19 |
| 557 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_WOFFSET 0x0 |
| 558 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT _MK_MASK_CONST(0
x0) |
| 559 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 560 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 561 #define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 562 |
| 563 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT _MK_SHIF
T_CONST(17) |
| 564 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT) |
| 565 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_RANGE 17:17 |
| 566 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_WOFFSET 0x0 |
| 567 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT _MK_MASK
_CONST(0x0) |
| 568 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 569 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 570 #define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 571 |
| 572 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT _MK_SHIFT_CONST(
16) |
| 573 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT) |
| 574 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_RANGE 16:16 |
| 575 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_WOFFSET 0x0 |
| 576 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT _MK_MASK_CONST(0
x0) |
| 577 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 578 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 579 #define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 580 |
| 581 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT _MK_SHIFT_CONST(
15) |
| 582 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT) |
| 583 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_RANGE 15:15 |
| 584 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_WOFFSET 0x0 |
| 585 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT _MK_MASK_CONST(0
x0) |
| 586 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 587 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 588 #define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 589 |
| 590 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SHIFT _MK_SHIFT_CONST(
14) |
| 591 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SHIFT) |
| 592 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_RANGE 14:14 |
| 593 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_WOFFSET 0x0 |
| 594 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_DEFAULT _MK_MASK_CONST(0
x0) |
| 595 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 596 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 597 #define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 598 |
| 599 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SHIFT _MK_SHIF
T_CONST(4) |
| 600 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_FIELD (_MK_MAS
K_CONST(0x3) << FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SHIFT) |
| 601 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_RANGE 5:4 |
| 602 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_WOFFSET 0x0 |
| 603 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_DEFAULT _MK_MASK
_CONST(0x0) |
| 604 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_DEFAULT_MASK
_MK_MASK_CONST(0x3) |
| 605 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 606 #define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 607 |
| 608 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SHIFT _MK_SHIFT_CONST(
1) |
| 609 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SHIFT) |
| 610 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_RANGE 1:1 |
| 611 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_WOFFSET 0x0 |
| 612 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_DEFAULT _MK_MASK
_CONST(0x0) |
| 613 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 614 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 615 #define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 616 |
| 617 #define FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT _MK_SHIFT_CONST(
0) |
| 618 #define FLOW_CTLR_CPU_CSR_0_ENABLE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT) |
| 619 #define FLOW_CTLR_CPU_CSR_0_ENABLE_RANGE 0:0 |
| 620 #define FLOW_CTLR_CPU_CSR_0_ENABLE_WOFFSET 0x0 |
| 621 #define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT _MK_MASK_CONST(0
x0) |
| 622 #define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 623 #define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 624 #define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 625 |
| 626 |
| 627 // Register FLOW_CTLR_COP_CSR_0 |
| 628 #define FLOW_CTLR_COP_CSR_0 _MK_ADDR_CONST(0xc) |
| 629 #define FLOW_CTLR_COP_CSR_0_SECURE 0x0 |
| 630 #define FLOW_CTLR_COP_CSR_0_WORD_COUNT 0x1 |
| 631 #define FLOW_CTLR_COP_CSR_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 632 #define FLOW_CTLR_COP_CSR_0_RESET_MASK _MK_MASK_CONST(0x8000) |
| 633 #define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 634 #define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 635 #define FLOW_CTLR_COP_CSR_0_READ_MASK _MK_MASK_CONST(0x8000) |
| 636 #define FLOW_CTLR_COP_CSR_0_WRITE_MASK _MK_MASK_CONST(0x8000) |
| 637 // TRUE when Interrupt is Active -- Write-1-to-Clear |
| 638 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT _MK_SHIFT_CONST(
15) |
| 639 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT) |
| 640 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_RANGE 15:15 |
| 641 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_WOFFSET 0x0 |
| 642 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT _MK_MASK_CONST(0
x0) |
| 643 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 644 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 645 #define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 646 |
| 647 |
| 648 // Register FLOW_CTLR_XRQ_EVENTS_0 |
| 649 #define FLOW_CTLR_XRQ_EVENTS_0 _MK_ADDR_CONST(0x10) |
| 650 #define FLOW_CTLR_XRQ_EVENTS_0_SECURE 0x0 |
| 651 #define FLOW_CTLR_XRQ_EVENTS_0_WORD_COUNT 0x1 |
| 652 #define FLOW_CTLR_XRQ_EVENTS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 653 #define FLOW_CTLR_XRQ_EVENTS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 654 #define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 655 #define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 656 #define FLOW_CTLR_XRQ_EVENTS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 657 #define FLOW_CTLR_XRQ_EVENTS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 658 // Setting a bit to 1 enables event triggering for the corresponding bit in GPI
O port D. The assertion level is determined by GPIO_INT.LVL.D. If more than one
XRQ.D bit is set, the events are ORed together. The resultant event is enabled
by setting the XRQ.D bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers. |
| 659 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT _MK_SHIF
T_CONST(24) |
| 660 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_FIELD (_MK_MAS
K_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT) |
| 661 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_RANGE 31:24 |
| 662 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_WOFFSET 0x0 |
| 663 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT _MK_MASK
_CONST(0x0) |
| 664 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT_MASK
_MK_MASK_CONST(0xff) |
| 665 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 666 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 667 |
| 668 // Setting a bit to 1 enables event triggering for the corresponding bit in GPI
O port C. The assertion level is determined by GPIO_INT.LVL.C. If more than one
XRQ.C bit is set, the events are ORed together. The resultant event is enabled
by setting the XRQ.C bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers. |
| 669 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT _MK_SHIF
T_CONST(16) |
| 670 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_FIELD (_MK_MAS
K_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT) |
| 671 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_RANGE 23:16 |
| 672 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_WOFFSET 0x0 |
| 673 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT _MK_MASK
_CONST(0x0) |
| 674 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT_MASK
_MK_MASK_CONST(0xff) |
| 675 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 676 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 677 |
| 678 // Setting a bit to 1 enables event triggering for the corresponding bit in GPI
O port B. The assertion level is determined by GPIO_INT.LVL.B. If more than one
XRQ.B bit is set, the events are ORed together. The resultant event is enabled
by setting the XRQ.B bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers. |
| 679 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT _MK_SHIF
T_CONST(8) |
| 680 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_FIELD (_MK_MAS
K_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT) |
| 681 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_RANGE 15:8 |
| 682 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_WOFFSET 0x0 |
| 683 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT _MK_MASK
_CONST(0x0) |
| 684 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT_MASK
_MK_MASK_CONST(0xff) |
| 685 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 686 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 687 |
| 688 // Setting a bit to 1 enables event triggering for the corresponding bit in GPI
O port A. The assertion level is determined by GPIO_INT.LVL.A. If more than one
XRQ.A bit is set, the events are ORed together. The resultant event is enabled
by setting the XRQ.A bit in the HALT_CPU.EVENTS or HALT_COP.EVENTS registers. |
| 689 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT _MK_SHIF
T_CONST(0) |
| 690 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_FIELD (_MK_MAS
K_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT) |
| 691 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_RANGE 7:0 |
| 692 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_WOFFSET 0x0 |
| 693 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT _MK_MASK
_CONST(0x0) |
| 694 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT_MASK
_MK_MASK_CONST(0xff) |
| 695 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 696 #define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 697 |
| 698 |
| 699 // Register FLOW_CTLR_HALT_CPU1_EVENTS_0 |
| 700 #define FLOW_CTLR_HALT_CPU1_EVENTS_0 _MK_ADDR_CONST(0x14) |
| 701 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SECURE 0x0 |
| 702 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_WORD_COUNT 0x1 |
| 703 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 704 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 705 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 706 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 707 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 708 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 709 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SHIFT _MK_SHIFT_CONST(
29) |
| 710 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FIELD (_MK_MASK_CONST(
0x7) << FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SHIFT) |
| 711 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_RANGE 31:29 |
| 712 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_WOFFSET 0x0 |
| 713 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_DEFAULT _MK_MASK
_CONST(0x0) |
| 714 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_DEFAULT_MASK _MK_MASK
_CONST(0x7) |
| 715 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 716 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 717 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_NONE
_MK_ENUM_CONST(0) |
| 718 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT
_MK_ENUM_CONST(1) |
| 719 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_WAITEVENT
_MK_ENUM_CONST(2) |
| 720 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT
_MK_ENUM_CONST(3) |
| 721 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ
_MK_ENUM_CONST(4) |
| 722 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT
_MK_ENUM_CONST(5) |
| 723 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ
_MK_ENUM_CONST(6) |
| 724 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP
_MK_ENUM_CONST(2) |
| 725 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT
_MK_ENUM_CONST(3) |
| 726 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT
_MK_ENUM_CONST(4) |
| 727 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT
_MK_ENUM_CONST(5) |
| 728 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT
_MK_ENUM_CONST(6) |
| 729 |
| 730 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SHIFT _MK_SHIFT_CONST(
28) |
| 731 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SHIFT) |
| 732 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_RANGE 28:28 |
| 733 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_WOFFSET 0x0 |
| 734 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_DEFAULT _MK_MASK
_CONST(0x0) |
| 735 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 736 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 737 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 738 |
| 739 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SHIFT _MK_SHIFT_CONST(
27) |
| 740 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SHIFT) |
| 741 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_RANGE 27:27 |
| 742 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_WOFFSET 0x0 |
| 743 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_DEFAULT _MK_MASK
_CONST(0x0) |
| 744 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 745 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 746 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 747 |
| 748 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SHIFT _MK_SHIFT_CONST(
26) |
| 749 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SHIFT) |
| 750 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_RANGE 26:26 |
| 751 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_WOFFSET 0x0 |
| 752 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_DEFAULT _MK_MASK
_CONST(0x0) |
| 753 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 754 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 755 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 756 |
| 757 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SHIFT _MK_SHIFT_CONST(
25) |
| 758 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SHIFT) |
| 759 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_RANGE 25:25 |
| 760 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_WOFFSET 0x0 |
| 761 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 762 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 763 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 764 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 765 |
| 766 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SHIFT _MK_SHIFT_CONST(
24) |
| 767 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SHIFT) |
| 768 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_RANGE 24:24 |
| 769 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_WOFFSET 0x0 |
| 770 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 771 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 772 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 773 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 774 |
| 775 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SHIFT _MK_SHIFT_CONST(
23) |
| 776 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SHIFT) |
| 777 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_RANGE 23:23 |
| 778 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_WOFFSET 0x0 |
| 779 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_DEFAULT _MK_MASK
_CONST(0x0) |
| 780 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 781 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 782 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 783 |
| 784 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SHIFT _MK_SHIF
T_CONST(22) |
| 785 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SHIFT) |
| 786 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_RANGE 22:22 |
| 787 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_WOFFSET 0x0 |
| 788 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_DEFAULT _MK_MASK
_CONST(0x0) |
| 789 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 790 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 791 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 792 |
| 793 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SHIFT _MK_SHIF
T_CONST(21) |
| 794 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SHIFT) |
| 795 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_RANGE 21:21 |
| 796 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_WOFFSET 0x0 |
| 797 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_DEFAULT _MK_MASK
_CONST(0x0) |
| 798 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 799 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 800 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 801 |
| 802 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SHIFT _MK_SHIF
T_CONST(20) |
| 803 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SHIFT) |
| 804 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_RANGE 20:20 |
| 805 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_WOFFSET 0x0 |
| 806 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_DEFAULT _MK_MASK
_CONST(0x0) |
| 807 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 808 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 809 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 810 |
| 811 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SHIFT _MK_SHIF
T_CONST(19) |
| 812 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SHIFT) |
| 813 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_RANGE 19:19 |
| 814 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_WOFFSET 0x0 |
| 815 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_DEFAULT _MK_MASK
_CONST(0x0) |
| 816 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 817 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 818 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 819 |
| 820 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SHIFT _MK_SHIF
T_CONST(18) |
| 821 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SHIFT) |
| 822 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_RANGE 18:18 |
| 823 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_WOFFSET 0x0 |
| 824 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_DEFAULT _MK_MASK
_CONST(0x0) |
| 825 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 826 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 827 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 828 |
| 829 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SHIFT _MK_SHIF
T_CONST(17) |
| 830 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SHIFT) |
| 831 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_RANGE 17:17 |
| 832 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_WOFFSET 0x0 |
| 833 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_DEFAULT _MK_MASK
_CONST(0x0) |
| 834 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 835 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 836 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 837 |
| 838 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SHIFT _MK_SHIF
T_CONST(16) |
| 839 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SHIFT) |
| 840 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_RANGE 16:16 |
| 841 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_WOFFSET 0x0 |
| 842 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_DEFAULT _MK_MASK
_CONST(0x0) |
| 843 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 844 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 845 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 846 |
| 847 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SHIFT _MK_SHIFT_CONST(
15) |
| 848 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SHIFT) |
| 849 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_RANGE 15:15 |
| 850 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_WOFFSET 0x0 |
| 851 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_DEFAULT _MK_MASK
_CONST(0x0) |
| 852 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 853 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 854 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 855 |
| 856 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SHIFT _MK_SHIFT_CONST(
14) |
| 857 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SHIFT) |
| 858 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_RANGE 14:14 |
| 859 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_WOFFSET 0x0 |
| 860 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_DEFAULT _MK_MASK
_CONST(0x0) |
| 861 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 862 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 863 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 864 |
| 865 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SHIFT _MK_SHIFT_CONST(
13) |
| 866 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SHIFT) |
| 867 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_RANGE 13:13 |
| 868 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_WOFFSET 0x0 |
| 869 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_DEFAULT _MK_MASK
_CONST(0x0) |
| 870 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 871 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 872 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 873 |
| 874 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SHIFT _MK_SHIFT_CONST(
12) |
| 875 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SHIFT) |
| 876 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_RANGE 12:12 |
| 877 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_WOFFSET 0x0 |
| 878 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_DEFAULT _MK_MASK
_CONST(0x0) |
| 879 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 880 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 881 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 882 |
| 883 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SHIFT _MK_SHIF
T_CONST(11) |
| 884 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SHIFT) |
| 885 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_RANGE 11:11 |
| 886 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_WOFFSET 0x0 |
| 887 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 888 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 889 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 890 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 891 |
| 892 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SHIFT _MK_SHIF
T_CONST(10) |
| 893 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SHIFT) |
| 894 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_RANGE 10:10 |
| 895 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_WOFFSET 0x0 |
| 896 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 897 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 898 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 899 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 900 |
| 901 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SHIFT _MK_SHIF
T_CONST(9) |
| 902 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SHIFT) |
| 903 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_RANGE 9:9 |
| 904 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_WOFFSET 0x0 |
| 905 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_DEFAULT _MK_MASK
_CONST(0x0) |
| 906 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 907 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 908 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 909 |
| 910 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SHIFT _MK_SHIF
T_CONST(8) |
| 911 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SHIFT) |
| 912 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_RANGE 8:8 |
| 913 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_WOFFSET 0x0 |
| 914 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_DEFAULT _MK_MASK
_CONST(0x0) |
| 915 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 916 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 917 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 918 |
| 919 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SHIFT _MK_SHIFT_CONST(
0) |
| 920 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_FIELD (_MK_MASK_CONST(
0xff) << FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SHIFT) |
| 921 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_RANGE 7:0 |
| 922 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_WOFFSET 0x0 |
| 923 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_DEFAULT _MK_MASK
_CONST(0x0) |
| 924 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 925 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 926 #define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 927 |
| 928 |
| 929 // Register FLOW_CTLR_CPU1_CSR_0 |
| 930 #define FLOW_CTLR_CPU1_CSR_0 _MK_ADDR_CONST(0x18) |
| 931 #define FLOW_CTLR_CPU1_CSR_0_SECURE 0x0 |
| 932 #define FLOW_CTLR_CPU1_CSR_0_WORD_COUNT 0x1 |
| 933 #define FLOW_CTLR_CPU1_CSR_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 934 #define FLOW_CTLR_CPU1_CSR_0_RESET_MASK _MK_MASK_CONST(0
xffbc033) |
| 935 #define FLOW_CTLR_CPU1_CSR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 936 #define FLOW_CTLR_CPU1_CSR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 937 #define FLOW_CTLR_CPU1_CSR_0_READ_MASK _MK_MASK_CONST(0xffbc033
) |
| 938 #define FLOW_CTLR_CPU1_CSR_0_WRITE_MASK _MK_MASK_CONST(0
xc033) |
| 939 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SHIFT _MK_SHIFT_CONST(
24) |
| 940 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_FIELD (_MK_MASK_CONST(
0xf) << FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SHIFT) |
| 941 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_RANGE 27:24 |
| 942 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_WOFFSET 0x0 |
| 943 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_DEFAULT _MK_MASK_CONST(0
x0) |
| 944 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 945 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 946 #define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 947 |
| 948 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SHIFT _MK_SHIFT_CONST(
23) |
| 949 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SHIFT) |
| 950 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_RANGE 23:23 |
| 951 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_WOFFSET 0x0 |
| 952 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_DEFAULT _MK_MASK_CONST(0
x0) |
| 953 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 954 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 955 #define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 956 |
| 957 #define FLOW_CTLR_CPU1_CSR_0_HALT_SHIFT _MK_SHIFT_CONST(22) |
| 958 #define FLOW_CTLR_CPU1_CSR_0_HALT_FIELD (_MK_MASK_CONST(0x1) <<
FLOW_CTLR_CPU1_CSR_0_HALT_SHIFT) |
| 959 #define FLOW_CTLR_CPU1_CSR_0_HALT_RANGE 22:22 |
| 960 #define FLOW_CTLR_CPU1_CSR_0_HALT_WOFFSET 0x0 |
| 961 #define FLOW_CTLR_CPU1_CSR_0_HALT_DEFAULT _MK_MASK_CONST(0
x0) |
| 962 #define FLOW_CTLR_CPU1_CSR_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 963 #define FLOW_CTLR_CPU1_CSR_0_HALT_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 964 #define FLOW_CTLR_CPU1_CSR_0_HALT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 965 |
| 966 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SHIFT _MK_SHIFT_CONST(
21) |
| 967 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SHIFT) |
| 968 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_RANGE 21:21 |
| 969 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_WOFFSET 0x0 |
| 970 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_DEFAULT _MK_MASK_CONST(0
x0) |
| 971 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 972 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 973 #define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 974 |
| 975 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SHIFT _MK_SHIFT_CONST(
20) |
| 976 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SHIFT) |
| 977 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_RANGE 20:20 |
| 978 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_WOFFSET 0x0 |
| 979 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_DEFAULT _MK_MASK_CONST(0
x0) |
| 980 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 981 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 982 #define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 983 |
| 984 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SHIFT _MK_SHIFT_CONST(
19) |
| 985 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SHIFT) |
| 986 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_RANGE 19:19 |
| 987 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_WOFFSET 0x0 |
| 988 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_DEFAULT _MK_MASK_CONST(0
x0) |
| 989 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 990 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 991 #define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 992 |
| 993 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SHIFT _MK_SHIF
T_CONST(17) |
| 994 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_FIELD (_MK_MAS
K_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SHIFT) |
| 995 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_RANGE 17:17 |
| 996 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_WOFFSET 0x0 |
| 997 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_DEFAULT _MK_MASK
_CONST(0x0) |
| 998 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 999 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1000 #define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1001 |
| 1002 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SHIFT _MK_SHIFT_CONST(
16) |
| 1003 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SHIFT) |
| 1004 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_RANGE 16:16 |
| 1005 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_WOFFSET 0x0 |
| 1006 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_DEFAULT _MK_MASK
_CONST(0x0) |
| 1007 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1008 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1009 #define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1010 |
| 1011 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SHIFT _MK_SHIFT_CONST(
15) |
| 1012 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SHIFT) |
| 1013 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_RANGE 15:15 |
| 1014 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_WOFFSET 0x0 |
| 1015 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_DEFAULT _MK_MASK_CONST(0
x0) |
| 1016 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1017 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1018 #define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1019 |
| 1020 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SHIFT _MK_SHIFT_CONST(
14) |
| 1021 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SHIFT) |
| 1022 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_RANGE 14:14 |
| 1023 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_WOFFSET 0x0 |
| 1024 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_DEFAULT _MK_MASK_CONST(0
x0) |
| 1025 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1026 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1027 #define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1028 |
| 1029 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SHIFT _MK_SHIF
T_CONST(4) |
| 1030 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_FIELD (_MK_MAS
K_CONST(0x3) << FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SHIFT) |
| 1031 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_RANGE 5:4 |
| 1032 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_WOFFSET 0x0 |
| 1033 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_DEFAULT _MK_MASK
_CONST(0x0) |
| 1034 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_DEFAULT_MASK
_MK_MASK_CONST(0x3) |
| 1035 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1036 #define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1037 |
| 1038 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SHIFT _MK_SHIFT_CONST(
1) |
| 1039 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SHIFT) |
| 1040 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_RANGE 1:1 |
| 1041 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_WOFFSET 0x0 |
| 1042 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_DEFAULT _MK_MASK
_CONST(0x0) |
| 1043 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1044 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1045 #define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1046 |
| 1047 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_SHIFT _MK_SHIFT_CONST(
0) |
| 1048 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_FIELD (_MK_MASK_CONST(
0x1) << FLOW_CTLR_CPU1_CSR_0_ENABLE_SHIFT) |
| 1049 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_RANGE 0:0 |
| 1050 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_WOFFSET 0x0 |
| 1051 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_DEFAULT _MK_MASK_CONST(0
x0) |
| 1052 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1053 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1054 #define FLOW_CTLR_CPU1_CSR_0_ENABLE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1055 |
| 1056 |
| 1057 // |
| 1058 // REGISTER LIST |
| 1059 // |
| 1060 #define LIST_ARFLOW_CTLR_REGS(_op_) \ |
| 1061 _op_(FLOW_CTLR_HALT_CPU_EVENTS_0) \ |
| 1062 _op_(FLOW_CTLR_HALT_COP_EVENTS_0) \ |
| 1063 _op_(FLOW_CTLR_CPU_CSR_0) \ |
| 1064 _op_(FLOW_CTLR_COP_CSR_0) \ |
| 1065 _op_(FLOW_CTLR_XRQ_EVENTS_0) \ |
| 1066 _op_(FLOW_CTLR_HALT_CPU1_EVENTS_0) \ |
| 1067 _op_(FLOW_CTLR_CPU1_CSR_0) |
| 1068 |
| 1069 |
| 1070 // |
| 1071 // ADDRESS SPACES |
| 1072 // |
| 1073 |
| 1074 #define BASE_ADDRESS_FLOW_CTLR 0x00000000 |
| 1075 |
| 1076 // |
| 1077 // ARFLOW_CTLR REGISTER BANKS |
| 1078 // |
| 1079 |
| 1080 #define FLOW_CTLR0_FIRST_REG 0x0000 // FLOW_CTLR_HALT_CPU_EVENTS_0 |
| 1081 #define FLOW_CTLR0_LAST_REG 0x0018 // FLOW_CTLR_CPU1_CSR_0 |
| 1082 |
| 1083 #ifndef _MK_SHIFT_CONST |
| 1084 #define _MK_SHIFT_CONST(_constant_) _constant_ |
| 1085 #endif |
| 1086 #ifndef _MK_MASK_CONST |
| 1087 #define _MK_MASK_CONST(_constant_) _constant_ |
| 1088 #endif |
| 1089 #ifndef _MK_ENUM_CONST |
| 1090 #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) |
| 1091 #endif |
| 1092 #ifndef _MK_ADDR_CONST |
| 1093 #define _MK_ADDR_CONST(_constant_) _constant_ |
| 1094 #endif |
| 1095 |
| 1096 #endif // ifndef ___ARFLOW_CTLR_H_INC_ |
| OLD | NEW |
|---|
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