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| 1 /* |
| 2 * Copyright (c) 2009 NVIDIA Corporation. |
| 3 * All rights reserved. |
| 4 * |
| 5 * Redistribution and use in source and binary forms, with or without |
| 6 * modification, are permitted provided that the following conditions are met: |
| 7 * |
| 8 * Redistributions of source code must retain the above copyright notice, |
| 9 * this list of conditions and the following disclaimer. |
| 10 * |
| 11 * Redistributions in binary form must reproduce the above copyright notice, |
| 12 * this list of conditions and the following disclaimer in the documentation |
| 13 * and/or other materials provided with the distribution. |
| 14 * |
| 15 * Neither the name of the NVIDIA Corporation nor the names of its contributors |
| 16 * may be used to endorse or promote products derived from this software |
| 17 * without specific prior written permission. |
| 18 * |
| 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 * POSSIBILITY OF SUCH DAMAGE. |
| 30 * |
| 31 */ |
| 32 // |
| 33 // DO NOT EDIT - generated by simspec! |
| 34 // |
| 35 |
| 36 #ifndef ___AREVP_H_INC_ |
| 37 #define ___AREVP_H_INC_ |
| 38 |
| 39 // Register EVP_RESET_VECTOR_0 |
| 40 #define EVP_RESET_VECTOR_0 _MK_ADDR_CONST(0x0) |
| 41 #define EVP_RESET_VECTOR_0_SECURE 0x0 |
| 42 #define EVP_RESET_VECTOR_0_WORD_COUNT 0x1 |
| 43 #define EVP_RESET_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
0) |
| 44 #define EVP_RESET_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 45 #define EVP_RESET_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 46 #define EVP_RESET_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 47 #define EVP_RESET_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 48 #define EVP_RESET_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 49 // RESET Exception Vector Pointer |
| 50 #define EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 51 #define EVP_RESET_VECTOR_0_RESET_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT) |
| 52 #define EVP_RESET_VECTOR_0_RESET_VECTOR_RANGE 31:0 |
| 53 #define EVP_RESET_VECTOR_0_RESET_VECTOR_WOFFSET 0x0 |
| 54 #define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00000) |
| 55 #define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 56 #define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 57 #define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 58 #define EVP_RESET_VECTOR_0_RESET_VECTOR_INIT_ENUM -1048576 |
| 59 |
| 60 |
| 61 // Register EVP_UNDEF_VECTOR_0 |
| 62 #define EVP_UNDEF_VECTOR_0 _MK_ADDR_CONST(0x4) |
| 63 #define EVP_UNDEF_VECTOR_0_SECURE 0x0 |
| 64 #define EVP_UNDEF_VECTOR_0_WORD_COUNT 0x1 |
| 65 #define EVP_UNDEF_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
4) |
| 66 #define EVP_UNDEF_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 67 #define EVP_UNDEF_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 68 #define EVP_UNDEF_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 69 #define EVP_UNDEF_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 70 #define EVP_UNDEF_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 71 // Undefined Exception Vector Pointer |
| 72 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 73 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT) |
| 74 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_RANGE 31:0 |
| 75 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_WOFFSET 0x0 |
| 76 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00004) |
| 77 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 78 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 79 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 80 #define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_INIT_ENUM -1048572 |
| 81 |
| 82 |
| 83 // Register EVP_SWI_VECTOR_0 |
| 84 #define EVP_SWI_VECTOR_0 _MK_ADDR_CONST(0x8) |
| 85 #define EVP_SWI_VECTOR_0_SECURE 0x0 |
| 86 #define EVP_SWI_VECTOR_0_WORD_COUNT 0x1 |
| 87 #define EVP_SWI_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
8) |
| 88 #define EVP_SWI_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 89 #define EVP_SWI_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 90 #define EVP_SWI_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 91 #define EVP_SWI_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 92 #define EVP_SWI_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 93 // Software Interrupt Vector Pointer |
| 94 #define EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 95 #define EVP_SWI_VECTOR_0_SWI_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT) |
| 96 #define EVP_SWI_VECTOR_0_SWI_VECTOR_RANGE 31:0 |
| 97 #define EVP_SWI_VECTOR_0_SWI_VECTOR_WOFFSET 0x0 |
| 98 #define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00008) |
| 99 #define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 100 #define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 101 #define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 102 #define EVP_SWI_VECTOR_0_SWI_VECTOR_INIT_ENUM -1048568 |
| 103 |
| 104 |
| 105 // Register EVP_PREFETCH_ABORT_VECTOR_0 |
| 106 #define EVP_PREFETCH_ABORT_VECTOR_0 _MK_ADDR_CONST(0xc) |
| 107 #define EVP_PREFETCH_ABORT_VECTOR_0_SECURE 0x0 |
| 108 #define EVP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 109 #define EVP_PREFETCH_ABORT_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff0000c) |
| 110 #define EVP_PREFETCH_ABORT_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 111 #define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 112 #define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 113 #define EVP_PREFETCH_ABORT_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 114 #define EVP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
x0) |
| 115 // Code Prefetch ABORT Vector Pointer |
| 116 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIFT
_MK_SHIFT_CONST(0) |
| 117 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_FIELD
(_MK_MASK_CONST(0xffffffff) << EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIF
T) |
| 118 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_RANGE
31:0 |
| 119 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_WOFFSET
0x0 |
| 120 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff0000c) |
| 121 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 122 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 123 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 124 #define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_INIT_ENUM
-1048564 |
| 125 |
| 126 |
| 127 // Register EVP_DATA_ABORT_VECTOR_0 |
| 128 #define EVP_DATA_ABORT_VECTOR_0 _MK_ADDR_CONST(0x10) |
| 129 #define EVP_DATA_ABORT_VECTOR_0_SECURE 0x0 |
| 130 #define EVP_DATA_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 131 #define EVP_DATA_ABORT_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00010) |
| 132 #define EVP_DATA_ABORT_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 133 #define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 134 #define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 135 #define EVP_DATA_ABORT_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 136 #define EVP_DATA_ABORT_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
x0) |
| 137 // Data ABORT Vector Pointer |
| 138 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 139 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT) |
| 140 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_RANGE 31:0 |
| 141 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_WOFFSET
0x0 |
| 142 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff00010) |
| 143 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 144 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 145 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 146 #define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_INIT_ENUM
-1048560 |
| 147 |
| 148 |
| 149 // Register EVP_RSVD_VECTOR_0 |
| 150 #define EVP_RSVD_VECTOR_0 _MK_ADDR_CONST(0x14) |
| 151 #define EVP_RSVD_VECTOR_0_SECURE 0x0 |
| 152 #define EVP_RSVD_VECTOR_0_WORD_COUNT 0x1 |
| 153 #define EVP_RSVD_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
4) |
| 154 #define EVP_RSVD_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 155 #define EVP_RSVD_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 156 #define EVP_RSVD_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 157 #define EVP_RSVD_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 158 #define EVP_RSVD_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 159 // Reserved Exception Vector Pointer |
| 160 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 161 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT) |
| 162 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_RANGE 31:0 |
| 163 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_WOFFSET 0x0 |
| 164 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00014) |
| 165 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 166 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 167 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 168 #define EVP_RSVD_VECTOR_0_RSVD_VECTOR_INIT_ENUM -1048556 |
| 169 |
| 170 |
| 171 // Register EVP_IRQ_VECTOR_0 |
| 172 #define EVP_IRQ_VECTOR_0 _MK_ADDR_CONST(0x18) |
| 173 #define EVP_IRQ_VECTOR_0_SECURE 0x0 |
| 174 #define EVP_IRQ_VECTOR_0_WORD_COUNT 0x1 |
| 175 #define EVP_IRQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
8) |
| 176 #define EVP_IRQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 177 #define EVP_IRQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 178 #define EVP_IRQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 179 #define EVP_IRQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 180 #define EVP_IRQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 181 // IRQ Vector Pointer |
| 182 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 183 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT) |
| 184 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_RANGE 31:0 |
| 185 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_WOFFSET 0x0 |
| 186 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00018) |
| 187 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 188 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 189 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 190 #define EVP_IRQ_VECTOR_0_IRQ_VECTOR_INIT_ENUM -1048552 |
| 191 |
| 192 |
| 193 // Register EVP_FIQ_VECTOR_0 |
| 194 #define EVP_FIQ_VECTOR_0 _MK_ADDR_CONST(0x1c) |
| 195 #define EVP_FIQ_VECTOR_0_SECURE 0x0 |
| 196 #define EVP_FIQ_VECTOR_0_WORD_COUNT 0x1 |
| 197 #define EVP_FIQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
0) |
| 198 #define EVP_FIQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 199 #define EVP_FIQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 200 #define EVP_FIQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 201 #define EVP_FIQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 202 #define EVP_FIQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 203 // FIQ Vector Pointer |
| 204 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT _MK_SHIFT_CONST(
0) |
| 205 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT) |
| 206 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_RANGE 31:0 |
| 207 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_WOFFSET 0x0 |
| 208 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT _MK_MASK_CONST(0
xfff00000) |
| 209 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 210 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 211 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 212 #define EVP_FIQ_VECTOR_0_FIQ_VECTOR_INIT_ENUM -1048576 |
| 213 |
| 214 |
| 215 // Register EVP_IRQ_STS_0 |
| 216 #define EVP_IRQ_STS_0 _MK_ADDR_CONST(0x20) |
| 217 #define EVP_IRQ_STS_0_SECURE 0x0 |
| 218 #define EVP_IRQ_STS_0_WORD_COUNT 0x1 |
| 219 #define EVP_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 220 #define EVP_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 221 #define EVP_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) |
| 222 #define EVP_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) |
| 223 #define EVP_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 224 #define EVP_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 225 // FFS (from lsb) IRQ index (0x80 indicates no active IRQ) |
| 226 #define EVP_IRQ_STS_0_IRQ_STS_SHIFT _MK_SHIFT_CONST(0) |
| 227 #define EVP_IRQ_STS_0_IRQ_STS_FIELD (_MK_MASK_CONST(0xffffff
ff) << EVP_IRQ_STS_0_IRQ_STS_SHIFT) |
| 228 #define EVP_IRQ_STS_0_IRQ_STS_RANGE 31:0 |
| 229 #define EVP_IRQ_STS_0_IRQ_STS_WOFFSET 0x0 |
| 230 #define EVP_IRQ_STS_0_IRQ_STS_DEFAULT _MK_MASK_CONST(0x80) |
| 231 #define EVP_IRQ_STS_0_IRQ_STS_DEFAULT_MASK _MK_MASK_CONST(0
xffffffff) |
| 232 #define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 233 #define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 234 |
| 235 |
| 236 // Register EVP_PRI_IRQ_STS_0 |
| 237 #define EVP_PRI_IRQ_STS_0 _MK_ADDR_CONST(0x24) |
| 238 #define EVP_PRI_IRQ_STS_0_SECURE 0x0 |
| 239 #define EVP_PRI_IRQ_STS_0_WORD_COUNT 0x1 |
| 240 #define EVP_PRI_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 241 #define EVP_PRI_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 242 #define EVP_PRI_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 243 #define EVP_PRI_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 244 #define EVP_PRI_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 245 #define EVP_PRI_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 246 // Current highest priority active IRQ (0x80 indicates no active priority IRQ) |
| 247 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 248 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT) |
| 249 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_RANGE 31:0 |
| 250 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_WOFFSET 0x0 |
| 251 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 252 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 253 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 254 #define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 255 |
| 256 |
| 257 // Register EVP_FIQ_STS_0 |
| 258 #define EVP_FIQ_STS_0 _MK_ADDR_CONST(0x28) |
| 259 #define EVP_FIQ_STS_0_SECURE 0x0 |
| 260 #define EVP_FIQ_STS_0_WORD_COUNT 0x1 |
| 261 #define EVP_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 262 #define EVP_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 263 #define EVP_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) |
| 264 #define EVP_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) |
| 265 #define EVP_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 266 #define EVP_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 267 // FFS (from lsb) FIQ index (0x80 indicates no active FIQ) |
| 268 #define EVP_FIQ_STS_0_FIQ_STS_SHIFT _MK_SHIFT_CONST(0) |
| 269 #define EVP_FIQ_STS_0_FIQ_STS_FIELD (_MK_MASK_CONST(0xffffff
ff) << EVP_FIQ_STS_0_FIQ_STS_SHIFT) |
| 270 #define EVP_FIQ_STS_0_FIQ_STS_RANGE 31:0 |
| 271 #define EVP_FIQ_STS_0_FIQ_STS_WOFFSET 0x0 |
| 272 #define EVP_FIQ_STS_0_FIQ_STS_DEFAULT _MK_MASK_CONST(0x80) |
| 273 #define EVP_FIQ_STS_0_FIQ_STS_DEFAULT_MASK _MK_MASK_CONST(0
xffffffff) |
| 274 #define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 275 #define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 276 |
| 277 |
| 278 // Register EVP_PRI_FIQ_STS_0 |
| 279 #define EVP_PRI_FIQ_STS_0 _MK_ADDR_CONST(0x2c) |
| 280 #define EVP_PRI_FIQ_STS_0_SECURE 0x0 |
| 281 #define EVP_PRI_FIQ_STS_0_WORD_COUNT 0x1 |
| 282 #define EVP_PRI_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 283 #define EVP_PRI_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 284 #define EVP_PRI_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 285 #define EVP_PRI_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 286 #define EVP_PRI_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 287 #define EVP_PRI_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 288 // Current highest priority active FIQ (0x80 indicates no active priority FIQ) |
| 289 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 290 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT) |
| 291 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_RANGE 31:0 |
| 292 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_WOFFSET 0x0 |
| 293 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 294 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 295 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 296 #define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 297 |
| 298 |
| 299 // Register EVP_PRI_IRQ_NUM_0_0 |
| 300 #define EVP_PRI_IRQ_NUM_0_0 _MK_ADDR_CONST(0x40) |
| 301 #define EVP_PRI_IRQ_NUM_0_0_SECURE 0x0 |
| 302 #define EVP_PRI_IRQ_NUM_0_0_WORD_COUNT 0x1 |
| 303 #define EVP_PRI_IRQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 304 #define EVP_PRI_IRQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 305 #define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 306 #define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 307 #define EVP_PRI_IRQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 308 #define EVP_PRI_IRQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 309 // Number for the Interrupt associated with this entry |
| 310 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT _MK_SHIFT_CONST(
0) |
| 311 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT) |
| 312 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE 31:0 |
| 313 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET 0x0 |
| 314 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 315 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 316 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 317 #define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 318 |
| 319 |
| 320 // Register EVP_PRI_IRQ_VEC_0_0 |
| 321 #define EVP_PRI_IRQ_VEC_0_0 _MK_ADDR_CONST(0x44) |
| 322 #define EVP_PRI_IRQ_VEC_0_0_SECURE 0x0 |
| 323 #define EVP_PRI_IRQ_VEC_0_0_WORD_COUNT 0x1 |
| 324 #define EVP_PRI_IRQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 325 #define EVP_PRI_IRQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 326 #define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 327 #define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 328 #define EVP_PRI_IRQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 329 #define EVP_PRI_IRQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 330 // Pointer to the interrupt handler for the above interrupt |
| 331 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT _MK_SHIFT_CONST(
0) |
| 332 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT) |
| 333 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE 31:0 |
| 334 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET 0x0 |
| 335 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 336 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 337 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 338 #define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 339 |
| 340 |
| 341 // Register EVP_PRI_IRQ_NUM_1_0 |
| 342 #define EVP_PRI_IRQ_NUM_1_0 _MK_ADDR_CONST(0x48) |
| 343 #define EVP_PRI_IRQ_NUM_1_0_SECURE 0x0 |
| 344 #define EVP_PRI_IRQ_NUM_1_0_WORD_COUNT 0x1 |
| 345 #define EVP_PRI_IRQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 346 #define EVP_PRI_IRQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 347 #define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 348 #define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 349 #define EVP_PRI_IRQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 350 #define EVP_PRI_IRQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 351 // Number for the Interrupt associated with this entry |
| 352 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT _MK_SHIFT_CONST(
0) |
| 353 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT) |
| 354 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE 31:0 |
| 355 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET 0x0 |
| 356 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 357 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 358 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 359 #define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 360 |
| 361 |
| 362 // Register EVP_PRI_IRQ_VEC_1_0 |
| 363 #define EVP_PRI_IRQ_VEC_1_0 _MK_ADDR_CONST(0x4c) |
| 364 #define EVP_PRI_IRQ_VEC_1_0_SECURE 0x0 |
| 365 #define EVP_PRI_IRQ_VEC_1_0_WORD_COUNT 0x1 |
| 366 #define EVP_PRI_IRQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 367 #define EVP_PRI_IRQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 368 #define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 369 #define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 370 #define EVP_PRI_IRQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 371 #define EVP_PRI_IRQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 372 // Pointer to the interrupt handler for the above interrupt |
| 373 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT _MK_SHIFT_CONST(
0) |
| 374 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT) |
| 375 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE 31:0 |
| 376 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET 0x0 |
| 377 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 378 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 379 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 380 #define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 381 |
| 382 |
| 383 // Register EVP_PRI_IRQ_NUM_2_0 |
| 384 #define EVP_PRI_IRQ_NUM_2_0 _MK_ADDR_CONST(0x50) |
| 385 #define EVP_PRI_IRQ_NUM_2_0_SECURE 0x0 |
| 386 #define EVP_PRI_IRQ_NUM_2_0_WORD_COUNT 0x1 |
| 387 #define EVP_PRI_IRQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 388 #define EVP_PRI_IRQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 389 #define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 390 #define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 391 #define EVP_PRI_IRQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 392 #define EVP_PRI_IRQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 393 // Number for the Interrupt associated with this entry |
| 394 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT _MK_SHIFT_CONST(
0) |
| 395 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT) |
| 396 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE 31:0 |
| 397 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET 0x0 |
| 398 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 399 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 400 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 401 #define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 402 |
| 403 |
| 404 // Register EVP_PRI_IRQ_VEC_2_0 |
| 405 #define EVP_PRI_IRQ_VEC_2_0 _MK_ADDR_CONST(0x54) |
| 406 #define EVP_PRI_IRQ_VEC_2_0_SECURE 0x0 |
| 407 #define EVP_PRI_IRQ_VEC_2_0_WORD_COUNT 0x1 |
| 408 #define EVP_PRI_IRQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 409 #define EVP_PRI_IRQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 410 #define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 411 #define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 412 #define EVP_PRI_IRQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 413 #define EVP_PRI_IRQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 414 // Pointer to the interrupt handler for the above interrupt |
| 415 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT _MK_SHIFT_CONST(
0) |
| 416 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT) |
| 417 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE 31:0 |
| 418 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET 0x0 |
| 419 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 420 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 421 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 422 #define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 423 |
| 424 |
| 425 // Register EVP_PRI_IRQ_NUM_3_0 |
| 426 #define EVP_PRI_IRQ_NUM_3_0 _MK_ADDR_CONST(0x58) |
| 427 #define EVP_PRI_IRQ_NUM_3_0_SECURE 0x0 |
| 428 #define EVP_PRI_IRQ_NUM_3_0_WORD_COUNT 0x1 |
| 429 #define EVP_PRI_IRQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 430 #define EVP_PRI_IRQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 431 #define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 432 #define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 433 #define EVP_PRI_IRQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 434 #define EVP_PRI_IRQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 435 // Number for the Interrupt associated with this entry |
| 436 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT _MK_SHIFT_CONST(
0) |
| 437 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT) |
| 438 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE 31:0 |
| 439 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET 0x0 |
| 440 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 441 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 442 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 443 #define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 444 |
| 445 |
| 446 // Register EVP_PRI_IRQ_VEC_3_0 |
| 447 #define EVP_PRI_IRQ_VEC_3_0 _MK_ADDR_CONST(0x5c) |
| 448 #define EVP_PRI_IRQ_VEC_3_0_SECURE 0x0 |
| 449 #define EVP_PRI_IRQ_VEC_3_0_WORD_COUNT 0x1 |
| 450 #define EVP_PRI_IRQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 451 #define EVP_PRI_IRQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 452 #define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 453 #define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 454 #define EVP_PRI_IRQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 455 #define EVP_PRI_IRQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 456 // Pointer to the interrupt handler for the above interrupt |
| 457 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT _MK_SHIFT_CONST(
0) |
| 458 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT) |
| 459 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE 31:0 |
| 460 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET 0x0 |
| 461 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 462 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 463 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 464 #define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 465 |
| 466 |
| 467 // Register EVP_PRI_IRQ_NUM_4_0 |
| 468 #define EVP_PRI_IRQ_NUM_4_0 _MK_ADDR_CONST(0x60) |
| 469 #define EVP_PRI_IRQ_NUM_4_0_SECURE 0x0 |
| 470 #define EVP_PRI_IRQ_NUM_4_0_WORD_COUNT 0x1 |
| 471 #define EVP_PRI_IRQ_NUM_4_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 472 #define EVP_PRI_IRQ_NUM_4_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 473 #define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 474 #define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 475 #define EVP_PRI_IRQ_NUM_4_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 476 #define EVP_PRI_IRQ_NUM_4_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 477 // Number for the Interrupt associated with this entry |
| 478 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT _MK_SHIFT_CONST(
0) |
| 479 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT) |
| 480 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE 31:0 |
| 481 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET 0x0 |
| 482 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT _MK_MASK
_CONST(0x80) |
| 483 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 484 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 485 #define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 486 |
| 487 |
| 488 // Register EVP_PRI_IRQ_VEC_4_0 |
| 489 #define EVP_PRI_IRQ_VEC_4_0 _MK_ADDR_CONST(0x64) |
| 490 #define EVP_PRI_IRQ_VEC_4_0_SECURE 0x0 |
| 491 #define EVP_PRI_IRQ_VEC_4_0_WORD_COUNT 0x1 |
| 492 #define EVP_PRI_IRQ_VEC_4_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 493 #define EVP_PRI_IRQ_VEC_4_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 494 #define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 495 #define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 496 #define EVP_PRI_IRQ_VEC_4_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 497 #define EVP_PRI_IRQ_VEC_4_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 498 // Pointer to the interrupt handler for the above interrupt |
| 499 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT _MK_SHIFT_CONST(
0) |
| 500 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT) |
| 501 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE 31:0 |
| 502 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET 0x0 |
| 503 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 504 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 505 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 506 #define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 507 |
| 508 |
| 509 // Register EVP_PRI_IRQ_NUM_5_0 |
| 510 #define EVP_PRI_IRQ_NUM_5_0 _MK_ADDR_CONST(0x68) |
| 511 #define EVP_PRI_IRQ_NUM_5_0_SECURE 0x0 |
| 512 #define EVP_PRI_IRQ_NUM_5_0_WORD_COUNT 0x1 |
| 513 #define EVP_PRI_IRQ_NUM_5_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 514 #define EVP_PRI_IRQ_NUM_5_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 515 #define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 516 #define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 517 #define EVP_PRI_IRQ_NUM_5_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 518 #define EVP_PRI_IRQ_NUM_5_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 519 // Number for the Interrupt associated with this entry |
| 520 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT _MK_SHIFT_CONST(
0) |
| 521 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT) |
| 522 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE 31:0 |
| 523 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET 0x0 |
| 524 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT _MK_MASK
_CONST(0x80) |
| 525 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 526 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 527 #define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 528 |
| 529 |
| 530 // Register EVP_PRI_IRQ_VEC_5_0 |
| 531 #define EVP_PRI_IRQ_VEC_5_0 _MK_ADDR_CONST(0x6c) |
| 532 #define EVP_PRI_IRQ_VEC_5_0_SECURE 0x0 |
| 533 #define EVP_PRI_IRQ_VEC_5_0_WORD_COUNT 0x1 |
| 534 #define EVP_PRI_IRQ_VEC_5_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 535 #define EVP_PRI_IRQ_VEC_5_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 536 #define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 537 #define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 538 #define EVP_PRI_IRQ_VEC_5_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 539 #define EVP_PRI_IRQ_VEC_5_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 540 // Pointer to the interrupt handler for the above interrupt |
| 541 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT _MK_SHIFT_CONST(
0) |
| 542 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT) |
| 543 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE 31:0 |
| 544 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET 0x0 |
| 545 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 546 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 547 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 548 #define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 549 |
| 550 |
| 551 // Register EVP_PRI_IRQ_NUM_6_0 |
| 552 #define EVP_PRI_IRQ_NUM_6_0 _MK_ADDR_CONST(0x70) |
| 553 #define EVP_PRI_IRQ_NUM_6_0_SECURE 0x0 |
| 554 #define EVP_PRI_IRQ_NUM_6_0_WORD_COUNT 0x1 |
| 555 #define EVP_PRI_IRQ_NUM_6_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 556 #define EVP_PRI_IRQ_NUM_6_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 557 #define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 558 #define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 559 #define EVP_PRI_IRQ_NUM_6_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 560 #define EVP_PRI_IRQ_NUM_6_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 561 // Number for the Interrupt associated with this entry |
| 562 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT _MK_SHIFT_CONST(
0) |
| 563 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT) |
| 564 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE 31:0 |
| 565 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET 0x0 |
| 566 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT _MK_MASK
_CONST(0x80) |
| 567 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 568 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 569 #define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 570 |
| 571 |
| 572 // Register EVP_PRI_IRQ_VEC_6_0 |
| 573 #define EVP_PRI_IRQ_VEC_6_0 _MK_ADDR_CONST(0x74) |
| 574 #define EVP_PRI_IRQ_VEC_6_0_SECURE 0x0 |
| 575 #define EVP_PRI_IRQ_VEC_6_0_WORD_COUNT 0x1 |
| 576 #define EVP_PRI_IRQ_VEC_6_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 577 #define EVP_PRI_IRQ_VEC_6_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 578 #define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 579 #define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 580 #define EVP_PRI_IRQ_VEC_6_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 581 #define EVP_PRI_IRQ_VEC_6_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 582 // Pointer to the interrupt handler for the above interrupt |
| 583 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT _MK_SHIFT_CONST(
0) |
| 584 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT) |
| 585 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE 31:0 |
| 586 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET 0x0 |
| 587 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 588 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 589 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 590 #define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 591 |
| 592 |
| 593 // Register EVP_PRI_IRQ_NUM_7_0 |
| 594 #define EVP_PRI_IRQ_NUM_7_0 _MK_ADDR_CONST(0x78) |
| 595 #define EVP_PRI_IRQ_NUM_7_0_SECURE 0x0 |
| 596 #define EVP_PRI_IRQ_NUM_7_0_WORD_COUNT 0x1 |
| 597 #define EVP_PRI_IRQ_NUM_7_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 598 #define EVP_PRI_IRQ_NUM_7_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 599 #define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 600 #define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 601 #define EVP_PRI_IRQ_NUM_7_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 602 #define EVP_PRI_IRQ_NUM_7_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 603 // Number for the Interrupt associated with this entry |
| 604 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT _MK_SHIFT_CONST(
0) |
| 605 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT) |
| 606 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE 31:0 |
| 607 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET 0x0 |
| 608 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT _MK_MASK
_CONST(0x80) |
| 609 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 610 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 611 #define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 612 |
| 613 |
| 614 // Register EVP_PRI_IRQ_VEC_7_0 |
| 615 #define EVP_PRI_IRQ_VEC_7_0 _MK_ADDR_CONST(0x7c) |
| 616 #define EVP_PRI_IRQ_VEC_7_0_SECURE 0x0 |
| 617 #define EVP_PRI_IRQ_VEC_7_0_WORD_COUNT 0x1 |
| 618 #define EVP_PRI_IRQ_VEC_7_0_RESET_VAL _MK_MASK_CONST(0x4000001
8) |
| 619 #define EVP_PRI_IRQ_VEC_7_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 620 #define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 621 #define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 622 #define EVP_PRI_IRQ_VEC_7_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 623 #define EVP_PRI_IRQ_VEC_7_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 624 // Pointer to the interrupt handler for the above interrupt |
| 625 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT _MK_SHIFT_CONST(
0) |
| 626 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT) |
| 627 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE 31:0 |
| 628 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET 0x0 |
| 629 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 630 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 631 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 632 #define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 633 |
| 634 |
| 635 // Register EVP_PRI_FIQ_NUM_0_0 |
| 636 #define EVP_PRI_FIQ_NUM_0_0 _MK_ADDR_CONST(0x80) |
| 637 #define EVP_PRI_FIQ_NUM_0_0_SECURE 0x0 |
| 638 #define EVP_PRI_FIQ_NUM_0_0_WORD_COUNT 0x1 |
| 639 #define EVP_PRI_FIQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 640 #define EVP_PRI_FIQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 641 #define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 642 #define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 643 #define EVP_PRI_FIQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 644 #define EVP_PRI_FIQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 645 // Number for the Interrupt associated with this entry |
| 646 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT _MK_SHIFT_CONST(
0) |
| 647 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT) |
| 648 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE 31:0 |
| 649 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET 0x0 |
| 650 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 651 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 652 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 653 #define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 654 |
| 655 |
| 656 // Register EVP_PRI_FIQ_VEC_0_0 |
| 657 #define EVP_PRI_FIQ_VEC_0_0 _MK_ADDR_CONST(0x84) |
| 658 #define EVP_PRI_FIQ_VEC_0_0_SECURE 0x0 |
| 659 #define EVP_PRI_FIQ_VEC_0_0_WORD_COUNT 0x1 |
| 660 #define EVP_PRI_FIQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0x4000001
c) |
| 661 #define EVP_PRI_FIQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 662 #define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 663 #define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 664 #define EVP_PRI_FIQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 665 #define EVP_PRI_FIQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 666 // Pointer to the interrupt handler for the above interrupt |
| 667 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT _MK_SHIFT_CONST(
0) |
| 668 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT) |
| 669 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE 31:0 |
| 670 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET 0x0 |
| 671 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 672 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 673 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 674 #define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 675 |
| 676 |
| 677 // Register EVP_PRI_FIQ_NUM_1_0 |
| 678 #define EVP_PRI_FIQ_NUM_1_0 _MK_ADDR_CONST(0x88) |
| 679 #define EVP_PRI_FIQ_NUM_1_0_SECURE 0x0 |
| 680 #define EVP_PRI_FIQ_NUM_1_0_WORD_COUNT 0x1 |
| 681 #define EVP_PRI_FIQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 682 #define EVP_PRI_FIQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 683 #define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 684 #define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 685 #define EVP_PRI_FIQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 686 #define EVP_PRI_FIQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 687 // Number for the Interrupt associated with this entry |
| 688 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT _MK_SHIFT_CONST(
0) |
| 689 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT) |
| 690 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE 31:0 |
| 691 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET 0x0 |
| 692 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 693 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 694 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 695 #define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 696 |
| 697 |
| 698 // Register EVP_PRI_FIQ_VEC_1_0 |
| 699 #define EVP_PRI_FIQ_VEC_1_0 _MK_ADDR_CONST(0x8c) |
| 700 #define EVP_PRI_FIQ_VEC_1_0_SECURE 0x0 |
| 701 #define EVP_PRI_FIQ_VEC_1_0_WORD_COUNT 0x1 |
| 702 #define EVP_PRI_FIQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0x4000001
c) |
| 703 #define EVP_PRI_FIQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 704 #define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 705 #define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 706 #define EVP_PRI_FIQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 707 #define EVP_PRI_FIQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 708 // Pointer to the interrupt handler for the above interrupt |
| 709 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT _MK_SHIFT_CONST(
0) |
| 710 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT) |
| 711 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE 31:0 |
| 712 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET 0x0 |
| 713 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 714 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 715 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 716 #define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 717 |
| 718 |
| 719 // Register EVP_PRI_FIQ_NUM_2_0 |
| 720 #define EVP_PRI_FIQ_NUM_2_0 _MK_ADDR_CONST(0x90) |
| 721 #define EVP_PRI_FIQ_NUM_2_0_SECURE 0x0 |
| 722 #define EVP_PRI_FIQ_NUM_2_0_WORD_COUNT 0x1 |
| 723 #define EVP_PRI_FIQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 724 #define EVP_PRI_FIQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 725 #define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 726 #define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 727 #define EVP_PRI_FIQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 728 #define EVP_PRI_FIQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 729 // Number for the Interrupt associated with this entry |
| 730 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT _MK_SHIFT_CONST(
0) |
| 731 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT) |
| 732 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE 31:0 |
| 733 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET 0x0 |
| 734 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 735 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 736 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 737 #define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 738 |
| 739 |
| 740 // Register EVP_PRI_FIQ_VEC_2_0 |
| 741 #define EVP_PRI_FIQ_VEC_2_0 _MK_ADDR_CONST(0x94) |
| 742 #define EVP_PRI_FIQ_VEC_2_0_SECURE 0x0 |
| 743 #define EVP_PRI_FIQ_VEC_2_0_WORD_COUNT 0x1 |
| 744 #define EVP_PRI_FIQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0x4000001
c) |
| 745 #define EVP_PRI_FIQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 746 #define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 747 #define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 748 #define EVP_PRI_FIQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 749 #define EVP_PRI_FIQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 750 // Pointer to the interrupt handler for the above interrupt |
| 751 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT _MK_SHIFT_CONST(
0) |
| 752 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT) |
| 753 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE 31:0 |
| 754 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET 0x0 |
| 755 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 756 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 757 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 758 #define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 759 |
| 760 |
| 761 // Register EVP_PRI_FIQ_NUM_3_0 |
| 762 #define EVP_PRI_FIQ_NUM_3_0 _MK_ADDR_CONST(0x98) |
| 763 #define EVP_PRI_FIQ_NUM_3_0_SECURE 0x0 |
| 764 #define EVP_PRI_FIQ_NUM_3_0_WORD_COUNT 0x1 |
| 765 #define EVP_PRI_FIQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 766 #define EVP_PRI_FIQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 767 #define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 768 #define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 769 #define EVP_PRI_FIQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 770 #define EVP_PRI_FIQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 771 // Number for the Interrupt associated with this entry |
| 772 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT _MK_SHIFT_CONST(
0) |
| 773 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT) |
| 774 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE 31:0 |
| 775 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET 0x0 |
| 776 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 777 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 778 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 779 #define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 780 |
| 781 |
| 782 // Register EVP_PRI_FIQ_VEC_3_0 |
| 783 #define EVP_PRI_FIQ_VEC_3_0 _MK_ADDR_CONST(0x9c) |
| 784 #define EVP_PRI_FIQ_VEC_3_0_SECURE 0x0 |
| 785 #define EVP_PRI_FIQ_VEC_3_0_WORD_COUNT 0x1 |
| 786 #define EVP_PRI_FIQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0x4000001
c) |
| 787 #define EVP_PRI_FIQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 788 #define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 789 #define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 790 #define EVP_PRI_FIQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 791 #define EVP_PRI_FIQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0x0) |
| 792 // Pointer to the interrupt handler for the above interrupt |
| 793 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT _MK_SHIFT_CONST(
0) |
| 794 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT) |
| 795 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE 31:0 |
| 796 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET 0x0 |
| 797 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 798 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 799 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 800 #define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 801 |
| 802 |
| 803 // Register EVP_CPU_RESET_VECTOR_0 |
| 804 #define EVP_CPU_RESET_VECTOR_0 _MK_ADDR_CONST(0x100) |
| 805 #define EVP_CPU_RESET_VECTOR_0_SECURE 0x0 |
| 806 #define EVP_CPU_RESET_VECTOR_0_WORD_COUNT 0x1 |
| 807 #define EVP_CPU_RESET_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00000) |
| 808 #define EVP_CPU_RESET_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 809 #define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 810 #define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 811 #define EVP_CPU_RESET_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 812 #define EVP_CPU_RESET_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 813 // RESET Exception Vector Pointer |
| 814 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 815 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT) |
| 816 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_RANGE 31:0 |
| 817 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_WOFFSET 0x0 |
| 818 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00000) |
| 819 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 820 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 821 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 822 #define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_INIT_ENUM
-1048576 |
| 823 |
| 824 |
| 825 // Register EVP_CPU_UNDEF_VECTOR_0 |
| 826 #define EVP_CPU_UNDEF_VECTOR_0 _MK_ADDR_CONST(0x104) |
| 827 #define EVP_CPU_UNDEF_VECTOR_0_SECURE 0x0 |
| 828 #define EVP_CPU_UNDEF_VECTOR_0_WORD_COUNT 0x1 |
| 829 #define EVP_CPU_UNDEF_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00004) |
| 830 #define EVP_CPU_UNDEF_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 831 #define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 832 #define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 833 #define EVP_CPU_UNDEF_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 834 #define EVP_CPU_UNDEF_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 835 // Undefined Exception Vector Pointer |
| 836 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 837 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT) |
| 838 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_RANGE 31:0 |
| 839 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_WOFFSET 0x0 |
| 840 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00004) |
| 841 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 842 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 843 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 844 #define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_INIT_ENUM
-1048572 |
| 845 |
| 846 |
| 847 // Register EVP_CPU_SWI_VECTOR_0 |
| 848 #define EVP_CPU_SWI_VECTOR_0 _MK_ADDR_CONST(0x108) |
| 849 #define EVP_CPU_SWI_VECTOR_0_SECURE 0x0 |
| 850 #define EVP_CPU_SWI_VECTOR_0_WORD_COUNT 0x1 |
| 851 #define EVP_CPU_SWI_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
8) |
| 852 #define EVP_CPU_SWI_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 853 #define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 854 #define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 855 #define EVP_CPU_SWI_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 856 #define EVP_CPU_SWI_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 857 // Software Interrupt Vector Pointer |
| 858 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 859 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT) |
| 860 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_RANGE 31:0 |
| 861 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_WOFFSET 0x0 |
| 862 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00008) |
| 863 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 864 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 865 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 866 #define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_INIT_ENUM -1048568 |
| 867 |
| 868 |
| 869 // Register EVP_CPU_PREFETCH_ABORT_VECTOR_0 |
| 870 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0 _MK_ADDR_CONST(0x10c) |
| 871 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SECURE 0x0 |
| 872 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 873 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_VAL _MK_MASK
_CONST(0xfff0000c) |
| 874 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 875 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 876 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 877 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 878 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 879 // Code Prefetch ABORT Vector Pointer |
| 880 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SHIFT
_MK_SHIFT_CONST(0) |
| 881 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_FIELD
(_MK_MASK_CONST(0xffffffff) << EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_A
BORT_VECTOR_SHIFT) |
| 882 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_RANGE
31:0 |
| 883 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_WOFFSET
0x0 |
| 884 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff0000c) |
| 885 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 886 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 887 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 888 #define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_INIT_ENUM
-1048564 |
| 889 |
| 890 |
| 891 // Register EVP_CPU_DATA_ABORT_VECTOR_0 |
| 892 #define EVP_CPU_DATA_ABORT_VECTOR_0 _MK_ADDR_CONST(0x110) |
| 893 #define EVP_CPU_DATA_ABORT_VECTOR_0_SECURE 0x0 |
| 894 #define EVP_CPU_DATA_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 895 #define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00010) |
| 896 #define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 897 #define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 898 #define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 899 #define EVP_CPU_DATA_ABORT_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 900 #define EVP_CPU_DATA_ABORT_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 901 // Data ABORT Vector Pointer |
| 902 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SHIFT
_MK_SHIFT_CONST(0) |
| 903 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_FIELD
(_MK_MASK_CONST(0xffffffff) << EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR
_SHIFT) |
| 904 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_RANGE
31:0 |
| 905 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_WOFFSET
0x0 |
| 906 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff00010) |
| 907 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 908 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 909 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 910 #define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_INIT_ENUM
-1048560 |
| 911 |
| 912 |
| 913 // Register EVP_CPU_RSVD_VECTOR_0 |
| 914 #define EVP_CPU_RSVD_VECTOR_0 _MK_ADDR_CONST(0x114) |
| 915 #define EVP_CPU_RSVD_VECTOR_0_SECURE 0x0 |
| 916 #define EVP_CPU_RSVD_VECTOR_0_WORD_COUNT 0x1 |
| 917 #define EVP_CPU_RSVD_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00014) |
| 918 #define EVP_CPU_RSVD_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 919 #define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 920 #define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 921 #define EVP_CPU_RSVD_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 922 #define EVP_CPU_RSVD_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 923 // Reserved Exception Vector Pointer |
| 924 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 925 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT) |
| 926 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_RANGE 31:0 |
| 927 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_WOFFSET 0x0 |
| 928 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00014) |
| 929 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 930 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 931 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 932 #define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_INIT_ENUM -1048556 |
| 933 |
| 934 |
| 935 // Register EVP_CPU_IRQ_VECTOR_0 |
| 936 #define EVP_CPU_IRQ_VECTOR_0 _MK_ADDR_CONST(0x118) |
| 937 #define EVP_CPU_IRQ_VECTOR_0_SECURE 0x0 |
| 938 #define EVP_CPU_IRQ_VECTOR_0_WORD_COUNT 0x1 |
| 939 #define EVP_CPU_IRQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
8) |
| 940 #define EVP_CPU_IRQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 941 #define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 942 #define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 943 #define EVP_CPU_IRQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 944 #define EVP_CPU_IRQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 945 // IRQ Vector Pointer |
| 946 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 947 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT) |
| 948 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_RANGE 31:0 |
| 949 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_WOFFSET 0x0 |
| 950 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00018) |
| 951 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 952 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 953 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 954 #define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_INIT_ENUM -1048552 |
| 955 |
| 956 |
| 957 // Register EVP_CPU_FIQ_VECTOR_0 |
| 958 #define EVP_CPU_FIQ_VECTOR_0 _MK_ADDR_CONST(0x11c) |
| 959 #define EVP_CPU_FIQ_VECTOR_0_SECURE 0x0 |
| 960 #define EVP_CPU_FIQ_VECTOR_0_WORD_COUNT 0x1 |
| 961 #define EVP_CPU_FIQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
c) |
| 962 #define EVP_CPU_FIQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 963 #define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 964 #define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 965 #define EVP_CPU_FIQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 966 #define EVP_CPU_FIQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 967 // FIQ Vector Pointer |
| 968 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 969 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT) |
| 970 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_RANGE 31:0 |
| 971 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_WOFFSET 0x0 |
| 972 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff0001c) |
| 973 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 974 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 975 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 976 #define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_INIT_ENUM -1048548 |
| 977 |
| 978 |
| 979 // Register EVP_CPU_IRQ_STS_0 |
| 980 #define EVP_CPU_IRQ_STS_0 _MK_ADDR_CONST(0x120) |
| 981 #define EVP_CPU_IRQ_STS_0_SECURE 0x0 |
| 982 #define EVP_CPU_IRQ_STS_0_WORD_COUNT 0x1 |
| 983 #define EVP_CPU_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 984 #define EVP_CPU_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 985 #define EVP_CPU_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 986 #define EVP_CPU_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 987 #define EVP_CPU_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 988 #define EVP_CPU_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0xfffffff
f) |
| 989 // FFS (from lsb) IRQ index (0x80 indicates no active IRQ) |
| 990 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 991 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT) |
| 992 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_RANGE 31:0 |
| 993 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_WOFFSET 0x0 |
| 994 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 995 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 996 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 997 #define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 998 |
| 999 |
| 1000 // Register EVP_CPU_PRI_IRQ_STS_0 |
| 1001 #define EVP_CPU_PRI_IRQ_STS_0 _MK_ADDR_CONST(0x124) |
| 1002 #define EVP_CPU_PRI_IRQ_STS_0_SECURE 0x0 |
| 1003 #define EVP_CPU_PRI_IRQ_STS_0_WORD_COUNT 0x1 |
| 1004 #define EVP_CPU_PRI_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1005 #define EVP_CPU_PRI_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1006 #define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1007 #define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1008 #define EVP_CPU_PRI_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1009 #define EVP_CPU_PRI_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1010 // Current highest priority active IRQ (0x80 indicates no active priority IRQ) |
| 1011 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT _MK_SHIF
T_CONST(0) |
| 1012 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT) |
| 1013 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_RANGE 31:0 |
| 1014 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_WOFFSET 0x0 |
| 1015 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT _MK_MASK
_CONST(0x80) |
| 1016 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1017 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1018 #define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1019 |
| 1020 |
| 1021 // Register EVP_CPU_FIQ_STS_0 |
| 1022 #define EVP_CPU_FIQ_STS_0 _MK_ADDR_CONST(0x128) |
| 1023 #define EVP_CPU_FIQ_STS_0_SECURE 0x0 |
| 1024 #define EVP_CPU_FIQ_STS_0_WORD_COUNT 0x1 |
| 1025 #define EVP_CPU_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 1026 #define EVP_CPU_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1027 #define EVP_CPU_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1028 #define EVP_CPU_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1029 #define EVP_CPU_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1030 #define EVP_CPU_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1031 // FFS (from lsb) FIQ index (0x80 indicates no active FIQ) |
| 1032 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 1033 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT) |
| 1034 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_RANGE 31:0 |
| 1035 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_WOFFSET 0x0 |
| 1036 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 1037 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 1038 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1039 #define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1040 |
| 1041 |
| 1042 // Register EVP_CPU_PRI_FIQ_STS_0 |
| 1043 #define EVP_CPU_PRI_FIQ_STS_0 _MK_ADDR_CONST(0x12c) |
| 1044 #define EVP_CPU_PRI_FIQ_STS_0_SECURE 0x0 |
| 1045 #define EVP_CPU_PRI_FIQ_STS_0_WORD_COUNT 0x1 |
| 1046 #define EVP_CPU_PRI_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1047 #define EVP_CPU_PRI_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1048 #define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1049 #define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1050 #define EVP_CPU_PRI_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1051 #define EVP_CPU_PRI_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1052 // Current highest priority active FIQ (0x80 indicates no active priority FIQ) |
| 1053 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT _MK_SHIF
T_CONST(0) |
| 1054 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT) |
| 1055 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_RANGE 31:0 |
| 1056 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_WOFFSET 0x0 |
| 1057 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT _MK_MASK
_CONST(0x80) |
| 1058 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1059 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1060 #define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1061 |
| 1062 |
| 1063 // Register EVP_CPU_PRI_IRQ_NUM_0_0 |
| 1064 #define EVP_CPU_PRI_IRQ_NUM_0_0 _MK_ADDR_CONST(0x140) |
| 1065 #define EVP_CPU_PRI_IRQ_NUM_0_0_SECURE 0x0 |
| 1066 #define EVP_CPU_PRI_IRQ_NUM_0_0_WORD_COUNT 0x1 |
| 1067 #define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1068 #define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1069 #define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1070 #define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1071 #define EVP_CPU_PRI_IRQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1072 #define EVP_CPU_PRI_IRQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1073 // Number for the Interrupt associated with this entry |
| 1074 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1075 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT) |
| 1076 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE 31:0 |
| 1077 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET 0x0 |
| 1078 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 1079 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1080 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1081 #define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1082 |
| 1083 |
| 1084 // Register EVP_CPU_PRI_IRQ_VEC_0_0 |
| 1085 #define EVP_CPU_PRI_IRQ_VEC_0_0 _MK_ADDR_CONST(0x144) |
| 1086 #define EVP_CPU_PRI_IRQ_VEC_0_0_SECURE 0x0 |
| 1087 #define EVP_CPU_PRI_IRQ_VEC_0_0_WORD_COUNT 0x1 |
| 1088 #define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1089 #define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1090 #define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1091 #define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1092 #define EVP_CPU_PRI_IRQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1093 #define EVP_CPU_PRI_IRQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1094 // Pointer to the interrupt handler for the above interrupt |
| 1095 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1096 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT) |
| 1097 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE 31:0 |
| 1098 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET 0x0 |
| 1099 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1100 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1101 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1102 #define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1103 |
| 1104 |
| 1105 // Register EVP_CPU_PRI_IRQ_NUM_1_0 |
| 1106 #define EVP_CPU_PRI_IRQ_NUM_1_0 _MK_ADDR_CONST(0x148) |
| 1107 #define EVP_CPU_PRI_IRQ_NUM_1_0_SECURE 0x0 |
| 1108 #define EVP_CPU_PRI_IRQ_NUM_1_0_WORD_COUNT 0x1 |
| 1109 #define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1110 #define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1111 #define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1112 #define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1113 #define EVP_CPU_PRI_IRQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1114 #define EVP_CPU_PRI_IRQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1115 // Number for the Interrupt associated with this entry |
| 1116 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1117 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT) |
| 1118 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE 31:0 |
| 1119 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET 0x0 |
| 1120 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 1121 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1122 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1123 #define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1124 |
| 1125 |
| 1126 // Register EVP_CPU_PRI_IRQ_VEC_1_0 |
| 1127 #define EVP_CPU_PRI_IRQ_VEC_1_0 _MK_ADDR_CONST(0x14c) |
| 1128 #define EVP_CPU_PRI_IRQ_VEC_1_0_SECURE 0x0 |
| 1129 #define EVP_CPU_PRI_IRQ_VEC_1_0_WORD_COUNT 0x1 |
| 1130 #define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1131 #define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1132 #define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1133 #define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1134 #define EVP_CPU_PRI_IRQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1135 #define EVP_CPU_PRI_IRQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1136 // Pointer to the interrupt handler for the above interrupt |
| 1137 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1138 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT) |
| 1139 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE 31:0 |
| 1140 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET 0x0 |
| 1141 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1142 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1143 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1144 #define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1145 |
| 1146 |
| 1147 // Register EVP_CPU_PRI_IRQ_NUM_2_0 |
| 1148 #define EVP_CPU_PRI_IRQ_NUM_2_0 _MK_ADDR_CONST(0x150) |
| 1149 #define EVP_CPU_PRI_IRQ_NUM_2_0_SECURE 0x0 |
| 1150 #define EVP_CPU_PRI_IRQ_NUM_2_0_WORD_COUNT 0x1 |
| 1151 #define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1152 #define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1153 #define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1154 #define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1155 #define EVP_CPU_PRI_IRQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1156 #define EVP_CPU_PRI_IRQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1157 // Number for the Interrupt associated with this entry |
| 1158 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1159 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT) |
| 1160 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE 31:0 |
| 1161 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET 0x0 |
| 1162 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 1163 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1164 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1165 #define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1166 |
| 1167 |
| 1168 // Register EVP_CPU_PRI_IRQ_VEC_2_0 |
| 1169 #define EVP_CPU_PRI_IRQ_VEC_2_0 _MK_ADDR_CONST(0x154) |
| 1170 #define EVP_CPU_PRI_IRQ_VEC_2_0_SECURE 0x0 |
| 1171 #define EVP_CPU_PRI_IRQ_VEC_2_0_WORD_COUNT 0x1 |
| 1172 #define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1173 #define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1174 #define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1175 #define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1176 #define EVP_CPU_PRI_IRQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1177 #define EVP_CPU_PRI_IRQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1178 // Pointer to the interrupt handler for the above interrupt |
| 1179 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1180 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT) |
| 1181 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE 31:0 |
| 1182 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET 0x0 |
| 1183 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1184 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1185 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1186 #define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1187 |
| 1188 |
| 1189 // Register EVP_CPU_PRI_IRQ_NUM_3_0 |
| 1190 #define EVP_CPU_PRI_IRQ_NUM_3_0 _MK_ADDR_CONST(0x158) |
| 1191 #define EVP_CPU_PRI_IRQ_NUM_3_0_SECURE 0x0 |
| 1192 #define EVP_CPU_PRI_IRQ_NUM_3_0_WORD_COUNT 0x1 |
| 1193 #define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1194 #define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1195 #define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1196 #define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1197 #define EVP_CPU_PRI_IRQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1198 #define EVP_CPU_PRI_IRQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1199 // Number for the Interrupt associated with this entry |
| 1200 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1201 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT) |
| 1202 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE 31:0 |
| 1203 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET 0x0 |
| 1204 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 1205 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1206 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1207 #define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1208 |
| 1209 |
| 1210 // Register EVP_CPU_PRI_IRQ_VEC_3_0 |
| 1211 #define EVP_CPU_PRI_IRQ_VEC_3_0 _MK_ADDR_CONST(0x15c) |
| 1212 #define EVP_CPU_PRI_IRQ_VEC_3_0_SECURE 0x0 |
| 1213 #define EVP_CPU_PRI_IRQ_VEC_3_0_WORD_COUNT 0x1 |
| 1214 #define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1215 #define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1216 #define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1217 #define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1218 #define EVP_CPU_PRI_IRQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1219 #define EVP_CPU_PRI_IRQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1220 // Pointer to the interrupt handler for the above interrupt |
| 1221 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1222 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT) |
| 1223 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE 31:0 |
| 1224 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET 0x0 |
| 1225 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1226 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1227 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1228 #define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1229 |
| 1230 |
| 1231 // Register EVP_CPU_PRI_IRQ_NUM_4_0 |
| 1232 #define EVP_CPU_PRI_IRQ_NUM_4_0 _MK_ADDR_CONST(0x160) |
| 1233 #define EVP_CPU_PRI_IRQ_NUM_4_0_SECURE 0x0 |
| 1234 #define EVP_CPU_PRI_IRQ_NUM_4_0_WORD_COUNT 0x1 |
| 1235 #define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1236 #define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1237 #define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1238 #define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1239 #define EVP_CPU_PRI_IRQ_NUM_4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1240 #define EVP_CPU_PRI_IRQ_NUM_4_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1241 // Number for the Interrupt associated with this entry |
| 1242 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT _MK_SHIF
T_CONST(0) |
| 1243 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT) |
| 1244 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE 31:0 |
| 1245 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET 0x0 |
| 1246 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT _MK_MASK
_CONST(0x80) |
| 1247 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1248 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1249 #define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1250 |
| 1251 |
| 1252 // Register EVP_CPU_PRI_IRQ_VEC_4_0 |
| 1253 #define EVP_CPU_PRI_IRQ_VEC_4_0 _MK_ADDR_CONST(0x164) |
| 1254 #define EVP_CPU_PRI_IRQ_VEC_4_0_SECURE 0x0 |
| 1255 #define EVP_CPU_PRI_IRQ_VEC_4_0_WORD_COUNT 0x1 |
| 1256 #define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1257 #define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1258 #define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1259 #define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1260 #define EVP_CPU_PRI_IRQ_VEC_4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1261 #define EVP_CPU_PRI_IRQ_VEC_4_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1262 // Pointer to the interrupt handler for the above interrupt |
| 1263 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT _MK_SHIF
T_CONST(0) |
| 1264 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT) |
| 1265 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE 31:0 |
| 1266 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET 0x0 |
| 1267 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1268 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1269 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1270 #define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1271 |
| 1272 |
| 1273 // Register EVP_CPU_PRI_IRQ_NUM_5_0 |
| 1274 #define EVP_CPU_PRI_IRQ_NUM_5_0 _MK_ADDR_CONST(0x168) |
| 1275 #define EVP_CPU_PRI_IRQ_NUM_5_0_SECURE 0x0 |
| 1276 #define EVP_CPU_PRI_IRQ_NUM_5_0_WORD_COUNT 0x1 |
| 1277 #define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1278 #define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1279 #define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1280 #define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1281 #define EVP_CPU_PRI_IRQ_NUM_5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1282 #define EVP_CPU_PRI_IRQ_NUM_5_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1283 // Number for the Interrupt associated with this entry |
| 1284 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT _MK_SHIF
T_CONST(0) |
| 1285 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT) |
| 1286 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE 31:0 |
| 1287 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET 0x0 |
| 1288 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT _MK_MASK
_CONST(0x80) |
| 1289 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1290 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1291 #define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1292 |
| 1293 |
| 1294 // Register EVP_CPU_PRI_IRQ_VEC_5_0 |
| 1295 #define EVP_CPU_PRI_IRQ_VEC_5_0 _MK_ADDR_CONST(0x16c) |
| 1296 #define EVP_CPU_PRI_IRQ_VEC_5_0_SECURE 0x0 |
| 1297 #define EVP_CPU_PRI_IRQ_VEC_5_0_WORD_COUNT 0x1 |
| 1298 #define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1299 #define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1300 #define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1301 #define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1302 #define EVP_CPU_PRI_IRQ_VEC_5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1303 #define EVP_CPU_PRI_IRQ_VEC_5_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1304 // Pointer to the interrupt handler for the above interrupt |
| 1305 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT _MK_SHIF
T_CONST(0) |
| 1306 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT) |
| 1307 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE 31:0 |
| 1308 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET 0x0 |
| 1309 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1310 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1311 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1312 #define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1313 |
| 1314 |
| 1315 // Register EVP_CPU_PRI_IRQ_NUM_6_0 |
| 1316 #define EVP_CPU_PRI_IRQ_NUM_6_0 _MK_ADDR_CONST(0x170) |
| 1317 #define EVP_CPU_PRI_IRQ_NUM_6_0_SECURE 0x0 |
| 1318 #define EVP_CPU_PRI_IRQ_NUM_6_0_WORD_COUNT 0x1 |
| 1319 #define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1320 #define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1321 #define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1322 #define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1323 #define EVP_CPU_PRI_IRQ_NUM_6_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1324 #define EVP_CPU_PRI_IRQ_NUM_6_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1325 // Number for the Interrupt associated with this entry |
| 1326 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT _MK_SHIF
T_CONST(0) |
| 1327 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT) |
| 1328 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE 31:0 |
| 1329 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET 0x0 |
| 1330 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT _MK_MASK
_CONST(0x80) |
| 1331 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1332 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1333 #define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1334 |
| 1335 |
| 1336 // Register EVP_CPU_PRI_IRQ_VEC_6_0 |
| 1337 #define EVP_CPU_PRI_IRQ_VEC_6_0 _MK_ADDR_CONST(0x174) |
| 1338 #define EVP_CPU_PRI_IRQ_VEC_6_0_SECURE 0x0 |
| 1339 #define EVP_CPU_PRI_IRQ_VEC_6_0_WORD_COUNT 0x1 |
| 1340 #define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1341 #define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1342 #define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1343 #define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1344 #define EVP_CPU_PRI_IRQ_VEC_6_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1345 #define EVP_CPU_PRI_IRQ_VEC_6_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1346 // Pointer to the interrupt handler for the above interrupt |
| 1347 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT _MK_SHIF
T_CONST(0) |
| 1348 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT) |
| 1349 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE 31:0 |
| 1350 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET 0x0 |
| 1351 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1352 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1353 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1354 #define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1355 |
| 1356 |
| 1357 // Register EVP_CPU_PRI_IRQ_NUM_7_0 |
| 1358 #define EVP_CPU_PRI_IRQ_NUM_7_0 _MK_ADDR_CONST(0x178) |
| 1359 #define EVP_CPU_PRI_IRQ_NUM_7_0_SECURE 0x0 |
| 1360 #define EVP_CPU_PRI_IRQ_NUM_7_0_WORD_COUNT 0x1 |
| 1361 #define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1362 #define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1363 #define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1364 #define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1365 #define EVP_CPU_PRI_IRQ_NUM_7_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1366 #define EVP_CPU_PRI_IRQ_NUM_7_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1367 // Number for the Interrupt associated with this entry |
| 1368 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT _MK_SHIF
T_CONST(0) |
| 1369 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT) |
| 1370 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE 31:0 |
| 1371 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET 0x0 |
| 1372 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT _MK_MASK
_CONST(0x80) |
| 1373 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1374 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1375 #define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1376 |
| 1377 |
| 1378 // Register EVP_CPU_PRI_IRQ_VEC_7_0 |
| 1379 #define EVP_CPU_PRI_IRQ_VEC_7_0 _MK_ADDR_CONST(0x17c) |
| 1380 #define EVP_CPU_PRI_IRQ_VEC_7_0_SECURE 0x0 |
| 1381 #define EVP_CPU_PRI_IRQ_VEC_7_0_WORD_COUNT 0x1 |
| 1382 #define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1383 #define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1384 #define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1385 #define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1386 #define EVP_CPU_PRI_IRQ_VEC_7_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1387 #define EVP_CPU_PRI_IRQ_VEC_7_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1388 // Pointer to the interrupt handler for the above interrupt |
| 1389 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT _MK_SHIF
T_CONST(0) |
| 1390 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT) |
| 1391 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE 31:0 |
| 1392 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET 0x0 |
| 1393 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1394 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1395 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1396 #define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1397 |
| 1398 |
| 1399 // Register EVP_CPU_PRI_FIQ_NUM_0_0 |
| 1400 #define EVP_CPU_PRI_FIQ_NUM_0_0 _MK_ADDR_CONST(0x180) |
| 1401 #define EVP_CPU_PRI_FIQ_NUM_0_0_SECURE 0x0 |
| 1402 #define EVP_CPU_PRI_FIQ_NUM_0_0_WORD_COUNT 0x1 |
| 1403 #define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1404 #define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1405 #define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1406 #define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1407 #define EVP_CPU_PRI_FIQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1408 #define EVP_CPU_PRI_FIQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1409 // Number for the Interrupt associated with this entry |
| 1410 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1411 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT) |
| 1412 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE 31:0 |
| 1413 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET 0x0 |
| 1414 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 1415 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1416 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1417 #define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1418 |
| 1419 |
| 1420 // Register EVP_CPU_PRI_FIQ_VEC_0_0 |
| 1421 #define EVP_CPU_PRI_FIQ_VEC_0_0 _MK_ADDR_CONST(0x184) |
| 1422 #define EVP_CPU_PRI_FIQ_VEC_0_0_SECURE 0x0 |
| 1423 #define EVP_CPU_PRI_FIQ_VEC_0_0_WORD_COUNT 0x1 |
| 1424 #define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 1425 #define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1426 #define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1427 #define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1428 #define EVP_CPU_PRI_FIQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1429 #define EVP_CPU_PRI_FIQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1430 // Pointer to the interrupt handler for the above interrupt |
| 1431 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1432 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT) |
| 1433 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE 31:0 |
| 1434 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET 0x0 |
| 1435 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 1436 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1437 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1438 #define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1439 |
| 1440 |
| 1441 // Register EVP_CPU_PRI_FIQ_NUM_1_0 |
| 1442 #define EVP_CPU_PRI_FIQ_NUM_1_0 _MK_ADDR_CONST(0x188) |
| 1443 #define EVP_CPU_PRI_FIQ_NUM_1_0_SECURE 0x0 |
| 1444 #define EVP_CPU_PRI_FIQ_NUM_1_0_WORD_COUNT 0x1 |
| 1445 #define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1446 #define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1447 #define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1448 #define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1449 #define EVP_CPU_PRI_FIQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1450 #define EVP_CPU_PRI_FIQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1451 // Number for the Interrupt associated with this entry |
| 1452 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1453 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT) |
| 1454 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE 31:0 |
| 1455 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET 0x0 |
| 1456 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 1457 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1458 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1459 #define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1460 |
| 1461 |
| 1462 // Register EVP_CPU_PRI_FIQ_VEC_1_0 |
| 1463 #define EVP_CPU_PRI_FIQ_VEC_1_0 _MK_ADDR_CONST(0x18c) |
| 1464 #define EVP_CPU_PRI_FIQ_VEC_1_0_SECURE 0x0 |
| 1465 #define EVP_CPU_PRI_FIQ_VEC_1_0_WORD_COUNT 0x1 |
| 1466 #define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 1467 #define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1468 #define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1469 #define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1470 #define EVP_CPU_PRI_FIQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1471 #define EVP_CPU_PRI_FIQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1472 // Pointer to the interrupt handler for the above interrupt |
| 1473 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1474 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT) |
| 1475 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE 31:0 |
| 1476 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET 0x0 |
| 1477 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 1478 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1479 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1480 #define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1481 |
| 1482 |
| 1483 // Register EVP_CPU_PRI_FIQ_NUM_2_0 |
| 1484 #define EVP_CPU_PRI_FIQ_NUM_2_0 _MK_ADDR_CONST(0x190) |
| 1485 #define EVP_CPU_PRI_FIQ_NUM_2_0_SECURE 0x0 |
| 1486 #define EVP_CPU_PRI_FIQ_NUM_2_0_WORD_COUNT 0x1 |
| 1487 #define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1488 #define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1489 #define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1490 #define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1491 #define EVP_CPU_PRI_FIQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1492 #define EVP_CPU_PRI_FIQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1493 // Number for the Interrupt associated with this entry |
| 1494 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1495 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT) |
| 1496 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE 31:0 |
| 1497 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET 0x0 |
| 1498 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 1499 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1500 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1501 #define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1502 |
| 1503 |
| 1504 // Register EVP_CPU_PRI_FIQ_VEC_2_0 |
| 1505 #define EVP_CPU_PRI_FIQ_VEC_2_0 _MK_ADDR_CONST(0x194) |
| 1506 #define EVP_CPU_PRI_FIQ_VEC_2_0_SECURE 0x0 |
| 1507 #define EVP_CPU_PRI_FIQ_VEC_2_0_WORD_COUNT 0x1 |
| 1508 #define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 1509 #define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1510 #define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1511 #define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1512 #define EVP_CPU_PRI_FIQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1513 #define EVP_CPU_PRI_FIQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1514 // Pointer to the interrupt handler for the above interrupt |
| 1515 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1516 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT) |
| 1517 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE 31:0 |
| 1518 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET 0x0 |
| 1519 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 1520 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1521 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1522 #define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1523 |
| 1524 |
| 1525 // Register EVP_CPU_PRI_FIQ_NUM_3_0 |
| 1526 #define EVP_CPU_PRI_FIQ_NUM_3_0 _MK_ADDR_CONST(0x198) |
| 1527 #define EVP_CPU_PRI_FIQ_NUM_3_0_SECURE 0x0 |
| 1528 #define EVP_CPU_PRI_FIQ_NUM_3_0_WORD_COUNT 0x1 |
| 1529 #define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1530 #define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1531 #define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1532 #define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1533 #define EVP_CPU_PRI_FIQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1534 #define EVP_CPU_PRI_FIQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1535 // Number for the Interrupt associated with this entry |
| 1536 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1537 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT) |
| 1538 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE 31:0 |
| 1539 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET 0x0 |
| 1540 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 1541 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1542 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1543 #define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1544 |
| 1545 |
| 1546 // Register EVP_CPU_PRI_FIQ_VEC_3_0 |
| 1547 #define EVP_CPU_PRI_FIQ_VEC_3_0 _MK_ADDR_CONST(0x19c) |
| 1548 #define EVP_CPU_PRI_FIQ_VEC_3_0_SECURE 0x0 |
| 1549 #define EVP_CPU_PRI_FIQ_VEC_3_0_WORD_COUNT 0x1 |
| 1550 #define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 1551 #define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1552 #define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1553 #define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1554 #define EVP_CPU_PRI_FIQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1555 #define EVP_CPU_PRI_FIQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1556 // Pointer to the interrupt handler for the above interrupt |
| 1557 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1558 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT) |
| 1559 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE 31:0 |
| 1560 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET 0x0 |
| 1561 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 1562 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1563 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1564 #define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1565 |
| 1566 |
| 1567 // Register EVP_COP_RESET_VECTOR_0 |
| 1568 #define EVP_COP_RESET_VECTOR_0 _MK_ADDR_CONST(0x200) |
| 1569 #define EVP_COP_RESET_VECTOR_0_SECURE 0x0 |
| 1570 #define EVP_COP_RESET_VECTOR_0_WORD_COUNT 0x1 |
| 1571 #define EVP_COP_RESET_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00000) |
| 1572 #define EVP_COP_RESET_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1573 #define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1574 #define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1575 #define EVP_COP_RESET_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1576 #define EVP_COP_RESET_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1577 // RESET Exception Vector Pointer |
| 1578 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1579 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT) |
| 1580 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_RANGE 31:0 |
| 1581 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_WOFFSET 0x0 |
| 1582 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00000) |
| 1583 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1584 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1585 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1586 #define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_INIT_ENUM
-1048576 |
| 1587 |
| 1588 |
| 1589 // Register EVP_COP_UNDEF_VECTOR_0 |
| 1590 #define EVP_COP_UNDEF_VECTOR_0 _MK_ADDR_CONST(0x204) |
| 1591 #define EVP_COP_UNDEF_VECTOR_0_SECURE 0x0 |
| 1592 #define EVP_COP_UNDEF_VECTOR_0_WORD_COUNT 0x1 |
| 1593 #define EVP_COP_UNDEF_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00004) |
| 1594 #define EVP_COP_UNDEF_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1595 #define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1596 #define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1597 #define EVP_COP_UNDEF_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1598 #define EVP_COP_UNDEF_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1599 // Undefined Exception Vector Pointer |
| 1600 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1601 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT) |
| 1602 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_RANGE 31:0 |
| 1603 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_WOFFSET 0x0 |
| 1604 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00004) |
| 1605 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1606 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1607 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1608 #define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_INIT_ENUM
-1048572 |
| 1609 |
| 1610 |
| 1611 // Register EVP_COP_SWI_VECTOR_0 |
| 1612 #define EVP_COP_SWI_VECTOR_0 _MK_ADDR_CONST(0x208) |
| 1613 #define EVP_COP_SWI_VECTOR_0_SECURE 0x0 |
| 1614 #define EVP_COP_SWI_VECTOR_0_WORD_COUNT 0x1 |
| 1615 #define EVP_COP_SWI_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0000
8) |
| 1616 #define EVP_COP_SWI_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1617 #define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1618 #define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1619 #define EVP_COP_SWI_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1620 #define EVP_COP_SWI_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1621 // Software Interrupt Vector Pointer |
| 1622 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1623 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT) |
| 1624 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_RANGE 31:0 |
| 1625 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_WOFFSET 0x0 |
| 1626 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00008) |
| 1627 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1628 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1629 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1630 #define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_INIT_ENUM -1048568 |
| 1631 |
| 1632 |
| 1633 // Register EVP_COP_PREFETCH_ABORT_VECTOR_0 |
| 1634 #define EVP_COP_PREFETCH_ABORT_VECTOR_0 _MK_ADDR_CONST(0x20c) |
| 1635 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_SECURE 0x0 |
| 1636 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 1637 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_VAL _MK_MASK
_CONST(0xfff0000c) |
| 1638 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 1639 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1640 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1641 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 1642 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 1643 // Code Prefetch ABORT Vector Pointer |
| 1644 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SHIFT
_MK_SHIFT_CONST(0) |
| 1645 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_FIELD
(_MK_MASK_CONST(0xffffffff) << EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_A
BORT_VECTOR_SHIFT) |
| 1646 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_RANGE
31:0 |
| 1647 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_WOFFSET
0x0 |
| 1648 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff0000c) |
| 1649 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1650 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1651 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1652 #define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_INIT_ENUM
-1048564 |
| 1653 |
| 1654 |
| 1655 // Register EVP_COP_DATA_ABORT_VECTOR_0 |
| 1656 #define EVP_COP_DATA_ABORT_VECTOR_0 _MK_ADDR_CONST(0x210) |
| 1657 #define EVP_COP_DATA_ABORT_VECTOR_0_SECURE 0x0 |
| 1658 #define EVP_COP_DATA_ABORT_VECTOR_0_WORD_COUNT 0x1 |
| 1659 #define EVP_COP_DATA_ABORT_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00010) |
| 1660 #define EVP_COP_DATA_ABORT_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1661 #define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1662 #define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1663 #define EVP_COP_DATA_ABORT_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1664 #define EVP_COP_DATA_ABORT_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1665 // Data ABORT Vector Pointer |
| 1666 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SHIFT
_MK_SHIFT_CONST(0) |
| 1667 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_FIELD
(_MK_MASK_CONST(0xffffffff) << EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR
_SHIFT) |
| 1668 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_RANGE
31:0 |
| 1669 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_WOFFSET
0x0 |
| 1670 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT
_MK_MASK_CONST(0xfff00010) |
| 1671 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1672 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1673 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1674 #define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_INIT_ENUM
-1048560 |
| 1675 |
| 1676 |
| 1677 // Register EVP_COP_RSVD_VECTOR_0 |
| 1678 #define EVP_COP_RSVD_VECTOR_0 _MK_ADDR_CONST(0x214) |
| 1679 #define EVP_COP_RSVD_VECTOR_0_SECURE 0x0 |
| 1680 #define EVP_COP_RSVD_VECTOR_0_WORD_COUNT 0x1 |
| 1681 #define EVP_COP_RSVD_VECTOR_0_RESET_VAL _MK_MASK_CONST(0
xfff00014) |
| 1682 #define EVP_COP_RSVD_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1683 #define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1684 #define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1685 #define EVP_COP_RSVD_VECTOR_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1686 #define EVP_COP_RSVD_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1687 // Reserved Exception Vector Pointer |
| 1688 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1689 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT) |
| 1690 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_RANGE 31:0 |
| 1691 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_WOFFSET 0x0 |
| 1692 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00014) |
| 1693 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1694 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1695 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1696 #define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_INIT_ENUM -1048556 |
| 1697 |
| 1698 |
| 1699 // Register EVP_COP_IRQ_VECTOR_0 |
| 1700 #define EVP_COP_IRQ_VECTOR_0 _MK_ADDR_CONST(0x218) |
| 1701 #define EVP_COP_IRQ_VECTOR_0_SECURE 0x0 |
| 1702 #define EVP_COP_IRQ_VECTOR_0_WORD_COUNT 0x1 |
| 1703 #define EVP_COP_IRQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
8) |
| 1704 #define EVP_COP_IRQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1705 #define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1706 #define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1707 #define EVP_COP_IRQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1708 #define EVP_COP_IRQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1709 // IRQ Vector Pointer |
| 1710 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1711 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT) |
| 1712 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_RANGE 31:0 |
| 1713 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_WOFFSET 0x0 |
| 1714 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff00018) |
| 1715 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1716 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1717 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1718 #define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_INIT_ENUM -1048552 |
| 1719 |
| 1720 |
| 1721 // Register EVP_COP_FIQ_VECTOR_0 |
| 1722 #define EVP_COP_FIQ_VECTOR_0 _MK_ADDR_CONST(0x21c) |
| 1723 #define EVP_COP_FIQ_VECTOR_0_SECURE 0x0 |
| 1724 #define EVP_COP_FIQ_VECTOR_0_WORD_COUNT 0x1 |
| 1725 #define EVP_COP_FIQ_VECTOR_0_RESET_VAL _MK_MASK_CONST(0xfff0001
c) |
| 1726 #define EVP_COP_FIQ_VECTOR_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1727 #define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1728 #define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1729 #define EVP_COP_FIQ_VECTOR_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1730 #define EVP_COP_FIQ_VECTOR_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1731 // FIQ Vector Pointer |
| 1732 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT _MK_SHIF
T_CONST(0) |
| 1733 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT) |
| 1734 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_RANGE 31:0 |
| 1735 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_WOFFSET 0x0 |
| 1736 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT _MK_MASK
_CONST(0xfff0001c) |
| 1737 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1738 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1739 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1740 #define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_INIT_ENUM -1048548 |
| 1741 |
| 1742 |
| 1743 // Register EVP_COP_IRQ_STS_0 |
| 1744 #define EVP_COP_IRQ_STS_0 _MK_ADDR_CONST(0x220) |
| 1745 #define EVP_COP_IRQ_STS_0_SECURE 0x0 |
| 1746 #define EVP_COP_IRQ_STS_0_WORD_COUNT 0x1 |
| 1747 #define EVP_COP_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 1748 #define EVP_COP_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1749 #define EVP_COP_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1750 #define EVP_COP_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1751 #define EVP_COP_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1752 #define EVP_COP_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1753 // FFS (from lsb) IRQ index (0x80 indicates no active IRQ) |
| 1754 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 1755 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT) |
| 1756 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_RANGE 31:0 |
| 1757 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_WOFFSET 0x0 |
| 1758 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 1759 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 1760 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1761 #define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1762 |
| 1763 |
| 1764 // Register EVP_COP_PRI_IRQ_STS_0 |
| 1765 #define EVP_COP_PRI_IRQ_STS_0 _MK_ADDR_CONST(0x224) |
| 1766 #define EVP_COP_PRI_IRQ_STS_0_SECURE 0x0 |
| 1767 #define EVP_COP_PRI_IRQ_STS_0_WORD_COUNT 0x1 |
| 1768 #define EVP_COP_PRI_IRQ_STS_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1769 #define EVP_COP_PRI_IRQ_STS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1770 #define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1771 #define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1772 #define EVP_COP_PRI_IRQ_STS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1773 #define EVP_COP_PRI_IRQ_STS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1774 // Current highest priority active IRQ (0x80 indicates no active priority IRQ) |
| 1775 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT _MK_SHIF
T_CONST(0) |
| 1776 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT) |
| 1777 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_RANGE 31:0 |
| 1778 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_WOFFSET 0x0 |
| 1779 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT _MK_MASK
_CONST(0x80) |
| 1780 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1781 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1782 #define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1783 |
| 1784 |
| 1785 // Register EVP_COP_FIQ_STS_0 |
| 1786 #define EVP_COP_FIQ_STS_0 _MK_ADDR_CONST(0x228) |
| 1787 #define EVP_COP_FIQ_STS_0_SECURE 0x0 |
| 1788 #define EVP_COP_FIQ_STS_0_WORD_COUNT 0x1 |
| 1789 #define EVP_COP_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0x80) |
| 1790 #define EVP_COP_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1791 #define EVP_COP_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1792 #define EVP_COP_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1793 #define EVP_COP_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1794 #define EVP_COP_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0xfffffff
f) |
| 1795 // FFS (from lsb) FIQ index (0x80 indicates no active FIQ) |
| 1796 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT _MK_SHIFT_CONST(
0) |
| 1797 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_FIELD (_MK_MASK_CONST(
0xffffffff) << EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT) |
| 1798 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_RANGE 31:0 |
| 1799 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_WOFFSET 0x0 |
| 1800 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT _MK_MASK_CONST(0
x80) |
| 1801 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 1802 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1803 #define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1804 |
| 1805 |
| 1806 // Register EVP_COP_PRI_FIQ_STS_0 |
| 1807 #define EVP_COP_PRI_FIQ_STS_0 _MK_ADDR_CONST(0x22c) |
| 1808 #define EVP_COP_PRI_FIQ_STS_0_SECURE 0x0 |
| 1809 #define EVP_COP_PRI_FIQ_STS_0_WORD_COUNT 0x1 |
| 1810 #define EVP_COP_PRI_FIQ_STS_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1811 #define EVP_COP_PRI_FIQ_STS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1812 #define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1813 #define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1814 #define EVP_COP_PRI_FIQ_STS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1815 #define EVP_COP_PRI_FIQ_STS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1816 // Current highest priority active FIQ (0x80 indicates no active priority FIQ) |
| 1817 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT _MK_SHIF
T_CONST(0) |
| 1818 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT) |
| 1819 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_RANGE 31:0 |
| 1820 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_WOFFSET 0x0 |
| 1821 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT _MK_MASK
_CONST(0x80) |
| 1822 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1823 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1824 #define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1825 |
| 1826 |
| 1827 // Register EVP_COP_PRI_IRQ_NUM_0_0 |
| 1828 #define EVP_COP_PRI_IRQ_NUM_0_0 _MK_ADDR_CONST(0x240) |
| 1829 #define EVP_COP_PRI_IRQ_NUM_0_0_SECURE 0x0 |
| 1830 #define EVP_COP_PRI_IRQ_NUM_0_0_WORD_COUNT 0x1 |
| 1831 #define EVP_COP_PRI_IRQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1832 #define EVP_COP_PRI_IRQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1833 #define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1834 #define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1835 #define EVP_COP_PRI_IRQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1836 #define EVP_COP_PRI_IRQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1837 // Number for the Interrupt associated with this entry |
| 1838 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1839 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT) |
| 1840 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE 31:0 |
| 1841 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET 0x0 |
| 1842 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 1843 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1844 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1845 #define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1846 |
| 1847 |
| 1848 // Register EVP_COP_PRI_IRQ_VEC_0_0 |
| 1849 #define EVP_COP_PRI_IRQ_VEC_0_0 _MK_ADDR_CONST(0x244) |
| 1850 #define EVP_COP_PRI_IRQ_VEC_0_0_SECURE 0x0 |
| 1851 #define EVP_COP_PRI_IRQ_VEC_0_0_WORD_COUNT 0x1 |
| 1852 #define EVP_COP_PRI_IRQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1853 #define EVP_COP_PRI_IRQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1854 #define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1855 #define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1856 #define EVP_COP_PRI_IRQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1857 #define EVP_COP_PRI_IRQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1858 // Pointer to the interrupt handler for the above interrupt |
| 1859 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT _MK_SHIF
T_CONST(0) |
| 1860 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT) |
| 1861 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE 31:0 |
| 1862 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET 0x0 |
| 1863 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1864 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1865 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1866 #define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1867 |
| 1868 |
| 1869 // Register EVP_COP_PRI_IRQ_NUM_1_0 |
| 1870 #define EVP_COP_PRI_IRQ_NUM_1_0 _MK_ADDR_CONST(0x248) |
| 1871 #define EVP_COP_PRI_IRQ_NUM_1_0_SECURE 0x0 |
| 1872 #define EVP_COP_PRI_IRQ_NUM_1_0_WORD_COUNT 0x1 |
| 1873 #define EVP_COP_PRI_IRQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1874 #define EVP_COP_PRI_IRQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1875 #define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1876 #define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1877 #define EVP_COP_PRI_IRQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1878 #define EVP_COP_PRI_IRQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1879 // Number for the Interrupt associated with this entry |
| 1880 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1881 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT) |
| 1882 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE 31:0 |
| 1883 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET 0x0 |
| 1884 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 1885 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1886 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1887 #define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1888 |
| 1889 |
| 1890 // Register EVP_COP_PRI_IRQ_VEC_1_0 |
| 1891 #define EVP_COP_PRI_IRQ_VEC_1_0 _MK_ADDR_CONST(0x24c) |
| 1892 #define EVP_COP_PRI_IRQ_VEC_1_0_SECURE 0x0 |
| 1893 #define EVP_COP_PRI_IRQ_VEC_1_0_WORD_COUNT 0x1 |
| 1894 #define EVP_COP_PRI_IRQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1895 #define EVP_COP_PRI_IRQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1896 #define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1897 #define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1898 #define EVP_COP_PRI_IRQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1899 #define EVP_COP_PRI_IRQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1900 // Pointer to the interrupt handler for the above interrupt |
| 1901 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT _MK_SHIF
T_CONST(0) |
| 1902 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT) |
| 1903 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE 31:0 |
| 1904 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET 0x0 |
| 1905 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1906 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1907 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1908 #define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1909 |
| 1910 |
| 1911 // Register EVP_COP_PRI_IRQ_NUM_2_0 |
| 1912 #define EVP_COP_PRI_IRQ_NUM_2_0 _MK_ADDR_CONST(0x250) |
| 1913 #define EVP_COP_PRI_IRQ_NUM_2_0_SECURE 0x0 |
| 1914 #define EVP_COP_PRI_IRQ_NUM_2_0_WORD_COUNT 0x1 |
| 1915 #define EVP_COP_PRI_IRQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1916 #define EVP_COP_PRI_IRQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1917 #define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1918 #define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1919 #define EVP_COP_PRI_IRQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1920 #define EVP_COP_PRI_IRQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1921 // Number for the Interrupt associated with this entry |
| 1922 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1923 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT) |
| 1924 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE 31:0 |
| 1925 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET 0x0 |
| 1926 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 1927 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1928 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1929 #define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1930 |
| 1931 |
| 1932 // Register EVP_COP_PRI_IRQ_VEC_2_0 |
| 1933 #define EVP_COP_PRI_IRQ_VEC_2_0 _MK_ADDR_CONST(0x254) |
| 1934 #define EVP_COP_PRI_IRQ_VEC_2_0_SECURE 0x0 |
| 1935 #define EVP_COP_PRI_IRQ_VEC_2_0_WORD_COUNT 0x1 |
| 1936 #define EVP_COP_PRI_IRQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1937 #define EVP_COP_PRI_IRQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1938 #define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1939 #define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1940 #define EVP_COP_PRI_IRQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1941 #define EVP_COP_PRI_IRQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1942 // Pointer to the interrupt handler for the above interrupt |
| 1943 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT _MK_SHIF
T_CONST(0) |
| 1944 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT) |
| 1945 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE 31:0 |
| 1946 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET 0x0 |
| 1947 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1948 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1949 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1950 #define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1951 |
| 1952 |
| 1953 // Register EVP_COP_PRI_IRQ_NUM_3_0 |
| 1954 #define EVP_COP_PRI_IRQ_NUM_3_0 _MK_ADDR_CONST(0x258) |
| 1955 #define EVP_COP_PRI_IRQ_NUM_3_0_SECURE 0x0 |
| 1956 #define EVP_COP_PRI_IRQ_NUM_3_0_WORD_COUNT 0x1 |
| 1957 #define EVP_COP_PRI_IRQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 1958 #define EVP_COP_PRI_IRQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1959 #define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1960 #define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1961 #define EVP_COP_PRI_IRQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1962 #define EVP_COP_PRI_IRQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1963 // Number for the Interrupt associated with this entry |
| 1964 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1965 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT) |
| 1966 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE 31:0 |
| 1967 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET 0x0 |
| 1968 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 1969 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1970 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1971 #define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1972 |
| 1973 |
| 1974 // Register EVP_COP_PRI_IRQ_VEC_3_0 |
| 1975 #define EVP_COP_PRI_IRQ_VEC_3_0 _MK_ADDR_CONST(0x25c) |
| 1976 #define EVP_COP_PRI_IRQ_VEC_3_0_SECURE 0x0 |
| 1977 #define EVP_COP_PRI_IRQ_VEC_3_0_WORD_COUNT 0x1 |
| 1978 #define EVP_COP_PRI_IRQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 1979 #define EVP_COP_PRI_IRQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1980 #define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1981 #define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1982 #define EVP_COP_PRI_IRQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1983 #define EVP_COP_PRI_IRQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1984 // Pointer to the interrupt handler for the above interrupt |
| 1985 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT _MK_SHIF
T_CONST(0) |
| 1986 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT) |
| 1987 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE 31:0 |
| 1988 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET 0x0 |
| 1989 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 1990 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 1991 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1992 #define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1993 |
| 1994 |
| 1995 // Register EVP_COP_PRI_IRQ_NUM_4_0 |
| 1996 #define EVP_COP_PRI_IRQ_NUM_4_0 _MK_ADDR_CONST(0x260) |
| 1997 #define EVP_COP_PRI_IRQ_NUM_4_0_SECURE 0x0 |
| 1998 #define EVP_COP_PRI_IRQ_NUM_4_0_WORD_COUNT 0x1 |
| 1999 #define EVP_COP_PRI_IRQ_NUM_4_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2000 #define EVP_COP_PRI_IRQ_NUM_4_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2001 #define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2002 #define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2003 #define EVP_COP_PRI_IRQ_NUM_4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2004 #define EVP_COP_PRI_IRQ_NUM_4_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2005 // Number for the Interrupt associated with this entry |
| 2006 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT _MK_SHIF
T_CONST(0) |
| 2007 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT) |
| 2008 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE 31:0 |
| 2009 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET 0x0 |
| 2010 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT _MK_MASK
_CONST(0x80) |
| 2011 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2012 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2013 #define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2014 |
| 2015 |
| 2016 // Register EVP_COP_PRI_IRQ_VEC_4_0 |
| 2017 #define EVP_COP_PRI_IRQ_VEC_4_0 _MK_ADDR_CONST(0x264) |
| 2018 #define EVP_COP_PRI_IRQ_VEC_4_0_SECURE 0x0 |
| 2019 #define EVP_COP_PRI_IRQ_VEC_4_0_WORD_COUNT 0x1 |
| 2020 #define EVP_COP_PRI_IRQ_VEC_4_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 2021 #define EVP_COP_PRI_IRQ_VEC_4_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2022 #define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2023 #define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2024 #define EVP_COP_PRI_IRQ_VEC_4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2025 #define EVP_COP_PRI_IRQ_VEC_4_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2026 // Pointer to the interrupt handler for the above interrupt |
| 2027 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT _MK_SHIF
T_CONST(0) |
| 2028 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT) |
| 2029 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE 31:0 |
| 2030 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET 0x0 |
| 2031 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 2032 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2033 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2034 #define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2035 |
| 2036 |
| 2037 // Register EVP_COP_PRI_IRQ_NUM_5_0 |
| 2038 #define EVP_COP_PRI_IRQ_NUM_5_0 _MK_ADDR_CONST(0x268) |
| 2039 #define EVP_COP_PRI_IRQ_NUM_5_0_SECURE 0x0 |
| 2040 #define EVP_COP_PRI_IRQ_NUM_5_0_WORD_COUNT 0x1 |
| 2041 #define EVP_COP_PRI_IRQ_NUM_5_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2042 #define EVP_COP_PRI_IRQ_NUM_5_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2043 #define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2044 #define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2045 #define EVP_COP_PRI_IRQ_NUM_5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2046 #define EVP_COP_PRI_IRQ_NUM_5_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2047 // Number for the Interrupt associated with this entry |
| 2048 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT _MK_SHIF
T_CONST(0) |
| 2049 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT) |
| 2050 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE 31:0 |
| 2051 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET 0x0 |
| 2052 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT _MK_MASK
_CONST(0x80) |
| 2053 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2054 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2055 #define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2056 |
| 2057 |
| 2058 // Register EVP_COP_PRI_IRQ_VEC_5_0 |
| 2059 #define EVP_COP_PRI_IRQ_VEC_5_0 _MK_ADDR_CONST(0x26c) |
| 2060 #define EVP_COP_PRI_IRQ_VEC_5_0_SECURE 0x0 |
| 2061 #define EVP_COP_PRI_IRQ_VEC_5_0_WORD_COUNT 0x1 |
| 2062 #define EVP_COP_PRI_IRQ_VEC_5_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 2063 #define EVP_COP_PRI_IRQ_VEC_5_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2064 #define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2065 #define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2066 #define EVP_COP_PRI_IRQ_VEC_5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2067 #define EVP_COP_PRI_IRQ_VEC_5_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2068 // Pointer to the interrupt handler for the above interrupt |
| 2069 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT _MK_SHIF
T_CONST(0) |
| 2070 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT) |
| 2071 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE 31:0 |
| 2072 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET 0x0 |
| 2073 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 2074 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2075 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2076 #define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2077 |
| 2078 |
| 2079 // Register EVP_COP_PRI_IRQ_NUM_6_0 |
| 2080 #define EVP_COP_PRI_IRQ_NUM_6_0 _MK_ADDR_CONST(0x270) |
| 2081 #define EVP_COP_PRI_IRQ_NUM_6_0_SECURE 0x0 |
| 2082 #define EVP_COP_PRI_IRQ_NUM_6_0_WORD_COUNT 0x1 |
| 2083 #define EVP_COP_PRI_IRQ_NUM_6_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2084 #define EVP_COP_PRI_IRQ_NUM_6_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2085 #define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2086 #define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2087 #define EVP_COP_PRI_IRQ_NUM_6_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2088 #define EVP_COP_PRI_IRQ_NUM_6_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2089 // Number for the Interrupt associated with this entry |
| 2090 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT _MK_SHIF
T_CONST(0) |
| 2091 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT) |
| 2092 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE 31:0 |
| 2093 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET 0x0 |
| 2094 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT _MK_MASK
_CONST(0x80) |
| 2095 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2096 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2097 #define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2098 |
| 2099 |
| 2100 // Register EVP_COP_PRI_IRQ_VEC_6_0 |
| 2101 #define EVP_COP_PRI_IRQ_VEC_6_0 _MK_ADDR_CONST(0x274) |
| 2102 #define EVP_COP_PRI_IRQ_VEC_6_0_SECURE 0x0 |
| 2103 #define EVP_COP_PRI_IRQ_VEC_6_0_WORD_COUNT 0x1 |
| 2104 #define EVP_COP_PRI_IRQ_VEC_6_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 2105 #define EVP_COP_PRI_IRQ_VEC_6_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2106 #define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2107 #define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2108 #define EVP_COP_PRI_IRQ_VEC_6_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2109 #define EVP_COP_PRI_IRQ_VEC_6_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2110 // Pointer to the interrupt handler for the above interrupt |
| 2111 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT _MK_SHIF
T_CONST(0) |
| 2112 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT) |
| 2113 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE 31:0 |
| 2114 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET 0x0 |
| 2115 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 2116 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2117 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2118 #define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2119 |
| 2120 |
| 2121 // Register EVP_COP_PRI_IRQ_NUM_7_0 |
| 2122 #define EVP_COP_PRI_IRQ_NUM_7_0 _MK_ADDR_CONST(0x278) |
| 2123 #define EVP_COP_PRI_IRQ_NUM_7_0_SECURE 0x0 |
| 2124 #define EVP_COP_PRI_IRQ_NUM_7_0_WORD_COUNT 0x1 |
| 2125 #define EVP_COP_PRI_IRQ_NUM_7_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2126 #define EVP_COP_PRI_IRQ_NUM_7_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2127 #define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2128 #define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2129 #define EVP_COP_PRI_IRQ_NUM_7_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2130 #define EVP_COP_PRI_IRQ_NUM_7_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2131 // Number for the Interrupt associated with this entry |
| 2132 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT _MK_SHIF
T_CONST(0) |
| 2133 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT) |
| 2134 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE 31:0 |
| 2135 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET 0x0 |
| 2136 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT _MK_MASK
_CONST(0x80) |
| 2137 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2138 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2139 #define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2140 |
| 2141 |
| 2142 // Register EVP_COP_PRI_IRQ_VEC_7_0 |
| 2143 #define EVP_COP_PRI_IRQ_VEC_7_0 _MK_ADDR_CONST(0x27c) |
| 2144 #define EVP_COP_PRI_IRQ_VEC_7_0_SECURE 0x0 |
| 2145 #define EVP_COP_PRI_IRQ_VEC_7_0_WORD_COUNT 0x1 |
| 2146 #define EVP_COP_PRI_IRQ_VEC_7_0_RESET_VAL _MK_MASK_CONST(0
x40000018) |
| 2147 #define EVP_COP_PRI_IRQ_VEC_7_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2148 #define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2149 #define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2150 #define EVP_COP_PRI_IRQ_VEC_7_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2151 #define EVP_COP_PRI_IRQ_VEC_7_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2152 // Pointer to the interrupt handler for the above interrupt |
| 2153 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT _MK_SHIF
T_CONST(0) |
| 2154 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT) |
| 2155 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE 31:0 |
| 2156 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET 0x0 |
| 2157 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT _MK_MASK
_CONST(0x40000018) |
| 2158 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2159 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2160 #define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2161 |
| 2162 |
| 2163 // Register EVP_COP_PRI_FIQ_NUM_0_0 |
| 2164 #define EVP_COP_PRI_FIQ_NUM_0_0 _MK_ADDR_CONST(0x280) |
| 2165 #define EVP_COP_PRI_FIQ_NUM_0_0_SECURE 0x0 |
| 2166 #define EVP_COP_PRI_FIQ_NUM_0_0_WORD_COUNT 0x1 |
| 2167 #define EVP_COP_PRI_FIQ_NUM_0_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2168 #define EVP_COP_PRI_FIQ_NUM_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2169 #define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2170 #define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2171 #define EVP_COP_PRI_FIQ_NUM_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2172 #define EVP_COP_PRI_FIQ_NUM_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2173 // Number for the Interrupt associated with this entry |
| 2174 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT _MK_SHIF
T_CONST(0) |
| 2175 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT) |
| 2176 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE 31:0 |
| 2177 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET 0x0 |
| 2178 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT _MK_MASK
_CONST(0x80) |
| 2179 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2180 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2181 #define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2182 |
| 2183 |
| 2184 // Register EVP_COP_PRI_FIQ_VEC_0_0 |
| 2185 #define EVP_COP_PRI_FIQ_VEC_0_0 _MK_ADDR_CONST(0x284) |
| 2186 #define EVP_COP_PRI_FIQ_VEC_0_0_SECURE 0x0 |
| 2187 #define EVP_COP_PRI_FIQ_VEC_0_0_WORD_COUNT 0x1 |
| 2188 #define EVP_COP_PRI_FIQ_VEC_0_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 2189 #define EVP_COP_PRI_FIQ_VEC_0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2190 #define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2191 #define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2192 #define EVP_COP_PRI_FIQ_VEC_0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2193 #define EVP_COP_PRI_FIQ_VEC_0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2194 // Pointer to the interrupt handler for the above interrupt |
| 2195 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT _MK_SHIF
T_CONST(0) |
| 2196 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT) |
| 2197 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE 31:0 |
| 2198 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET 0x0 |
| 2199 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 2200 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2201 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2202 #define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2203 |
| 2204 |
| 2205 // Register EVP_COP_PRI_FIQ_NUM_1_0 |
| 2206 #define EVP_COP_PRI_FIQ_NUM_1_0 _MK_ADDR_CONST(0x288) |
| 2207 #define EVP_COP_PRI_FIQ_NUM_1_0_SECURE 0x0 |
| 2208 #define EVP_COP_PRI_FIQ_NUM_1_0_WORD_COUNT 0x1 |
| 2209 #define EVP_COP_PRI_FIQ_NUM_1_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2210 #define EVP_COP_PRI_FIQ_NUM_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2211 #define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2212 #define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2213 #define EVP_COP_PRI_FIQ_NUM_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2214 #define EVP_COP_PRI_FIQ_NUM_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2215 // Number for the Interrupt associated with this entry |
| 2216 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT _MK_SHIF
T_CONST(0) |
| 2217 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT) |
| 2218 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE 31:0 |
| 2219 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET 0x0 |
| 2220 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT _MK_MASK
_CONST(0x80) |
| 2221 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2222 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2223 #define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2224 |
| 2225 |
| 2226 // Register EVP_COP_PRI_FIQ_VEC_1_0 |
| 2227 #define EVP_COP_PRI_FIQ_VEC_1_0 _MK_ADDR_CONST(0x28c) |
| 2228 #define EVP_COP_PRI_FIQ_VEC_1_0_SECURE 0x0 |
| 2229 #define EVP_COP_PRI_FIQ_VEC_1_0_WORD_COUNT 0x1 |
| 2230 #define EVP_COP_PRI_FIQ_VEC_1_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 2231 #define EVP_COP_PRI_FIQ_VEC_1_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2232 #define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2233 #define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2234 #define EVP_COP_PRI_FIQ_VEC_1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2235 #define EVP_COP_PRI_FIQ_VEC_1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2236 // Pointer to the interrupt handler for the above interrupt |
| 2237 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT _MK_SHIF
T_CONST(0) |
| 2238 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT) |
| 2239 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE 31:0 |
| 2240 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET 0x0 |
| 2241 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 2242 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2243 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2244 #define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2245 |
| 2246 |
| 2247 // Register EVP_COP_PRI_FIQ_NUM_2_0 |
| 2248 #define EVP_COP_PRI_FIQ_NUM_2_0 _MK_ADDR_CONST(0x290) |
| 2249 #define EVP_COP_PRI_FIQ_NUM_2_0_SECURE 0x0 |
| 2250 #define EVP_COP_PRI_FIQ_NUM_2_0_WORD_COUNT 0x1 |
| 2251 #define EVP_COP_PRI_FIQ_NUM_2_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2252 #define EVP_COP_PRI_FIQ_NUM_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2253 #define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2254 #define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2255 #define EVP_COP_PRI_FIQ_NUM_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2256 #define EVP_COP_PRI_FIQ_NUM_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2257 // Number for the Interrupt associated with this entry |
| 2258 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT _MK_SHIF
T_CONST(0) |
| 2259 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT) |
| 2260 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE 31:0 |
| 2261 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET 0x0 |
| 2262 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT _MK_MASK
_CONST(0x80) |
| 2263 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2264 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2265 #define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2266 |
| 2267 |
| 2268 // Register EVP_COP_PRI_FIQ_VEC_2_0 |
| 2269 #define EVP_COP_PRI_FIQ_VEC_2_0 _MK_ADDR_CONST(0x294) |
| 2270 #define EVP_COP_PRI_FIQ_VEC_2_0_SECURE 0x0 |
| 2271 #define EVP_COP_PRI_FIQ_VEC_2_0_WORD_COUNT 0x1 |
| 2272 #define EVP_COP_PRI_FIQ_VEC_2_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 2273 #define EVP_COP_PRI_FIQ_VEC_2_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2274 #define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2275 #define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2276 #define EVP_COP_PRI_FIQ_VEC_2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2277 #define EVP_COP_PRI_FIQ_VEC_2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2278 // Pointer to the interrupt handler for the above interrupt |
| 2279 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT _MK_SHIF
T_CONST(0) |
| 2280 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT) |
| 2281 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE 31:0 |
| 2282 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET 0x0 |
| 2283 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 2284 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2285 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2286 #define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2287 |
| 2288 |
| 2289 // Register EVP_COP_PRI_FIQ_NUM_3_0 |
| 2290 #define EVP_COP_PRI_FIQ_NUM_3_0 _MK_ADDR_CONST(0x298) |
| 2291 #define EVP_COP_PRI_FIQ_NUM_3_0_SECURE 0x0 |
| 2292 #define EVP_COP_PRI_FIQ_NUM_3_0_WORD_COUNT 0x1 |
| 2293 #define EVP_COP_PRI_FIQ_NUM_3_0_RESET_VAL _MK_MASK_CONST(0
x80) |
| 2294 #define EVP_COP_PRI_FIQ_NUM_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2295 #define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2296 #define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2297 #define EVP_COP_PRI_FIQ_NUM_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2298 #define EVP_COP_PRI_FIQ_NUM_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2299 // Number for the Interrupt associated with this entry |
| 2300 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT _MK_SHIF
T_CONST(0) |
| 2301 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT) |
| 2302 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE 31:0 |
| 2303 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET 0x0 |
| 2304 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT _MK_MASK
_CONST(0x80) |
| 2305 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2306 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2307 #define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2308 |
| 2309 |
| 2310 // Register EVP_COP_PRI_FIQ_VEC_3_0 |
| 2311 #define EVP_COP_PRI_FIQ_VEC_3_0 _MK_ADDR_CONST(0x29c) |
| 2312 #define EVP_COP_PRI_FIQ_VEC_3_0_SECURE 0x0 |
| 2313 #define EVP_COP_PRI_FIQ_VEC_3_0_WORD_COUNT 0x1 |
| 2314 #define EVP_COP_PRI_FIQ_VEC_3_0_RESET_VAL _MK_MASK_CONST(0
x4000001c) |
| 2315 #define EVP_COP_PRI_FIQ_VEC_3_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2316 #define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2317 #define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2318 #define EVP_COP_PRI_FIQ_VEC_3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2319 #define EVP_COP_PRI_FIQ_VEC_3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2320 // Pointer to the interrupt handler for the above interrupt |
| 2321 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT _MK_SHIF
T_CONST(0) |
| 2322 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD (_MK_MAS
K_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT) |
| 2323 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE 31:0 |
| 2324 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET 0x0 |
| 2325 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT _MK_MASK
_CONST(0x4000001c) |
| 2326 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2327 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2328 #define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2329 |
| 2330 |
| 2331 // |
| 2332 // REGISTER LIST |
| 2333 // |
| 2334 #define LIST_AREVP_REGS(_op_) \ |
| 2335 _op_(EVP_RESET_VECTOR_0) \ |
| 2336 _op_(EVP_UNDEF_VECTOR_0) \ |
| 2337 _op_(EVP_SWI_VECTOR_0) \ |
| 2338 _op_(EVP_PREFETCH_ABORT_VECTOR_0) \ |
| 2339 _op_(EVP_DATA_ABORT_VECTOR_0) \ |
| 2340 _op_(EVP_RSVD_VECTOR_0) \ |
| 2341 _op_(EVP_IRQ_VECTOR_0) \ |
| 2342 _op_(EVP_FIQ_VECTOR_0) \ |
| 2343 _op_(EVP_IRQ_STS_0) \ |
| 2344 _op_(EVP_PRI_IRQ_STS_0) \ |
| 2345 _op_(EVP_FIQ_STS_0) \ |
| 2346 _op_(EVP_PRI_FIQ_STS_0) \ |
| 2347 _op_(EVP_PRI_IRQ_NUM_0_0) \ |
| 2348 _op_(EVP_PRI_IRQ_VEC_0_0) \ |
| 2349 _op_(EVP_PRI_IRQ_NUM_1_0) \ |
| 2350 _op_(EVP_PRI_IRQ_VEC_1_0) \ |
| 2351 _op_(EVP_PRI_IRQ_NUM_2_0) \ |
| 2352 _op_(EVP_PRI_IRQ_VEC_2_0) \ |
| 2353 _op_(EVP_PRI_IRQ_NUM_3_0) \ |
| 2354 _op_(EVP_PRI_IRQ_VEC_3_0) \ |
| 2355 _op_(EVP_PRI_IRQ_NUM_4_0) \ |
| 2356 _op_(EVP_PRI_IRQ_VEC_4_0) \ |
| 2357 _op_(EVP_PRI_IRQ_NUM_5_0) \ |
| 2358 _op_(EVP_PRI_IRQ_VEC_5_0) \ |
| 2359 _op_(EVP_PRI_IRQ_NUM_6_0) \ |
| 2360 _op_(EVP_PRI_IRQ_VEC_6_0) \ |
| 2361 _op_(EVP_PRI_IRQ_NUM_7_0) \ |
| 2362 _op_(EVP_PRI_IRQ_VEC_7_0) \ |
| 2363 _op_(EVP_PRI_FIQ_NUM_0_0) \ |
| 2364 _op_(EVP_PRI_FIQ_VEC_0_0) \ |
| 2365 _op_(EVP_PRI_FIQ_NUM_1_0) \ |
| 2366 _op_(EVP_PRI_FIQ_VEC_1_0) \ |
| 2367 _op_(EVP_PRI_FIQ_NUM_2_0) \ |
| 2368 _op_(EVP_PRI_FIQ_VEC_2_0) \ |
| 2369 _op_(EVP_PRI_FIQ_NUM_3_0) \ |
| 2370 _op_(EVP_PRI_FIQ_VEC_3_0) \ |
| 2371 _op_(EVP_CPU_RESET_VECTOR_0) \ |
| 2372 _op_(EVP_CPU_UNDEF_VECTOR_0) \ |
| 2373 _op_(EVP_CPU_SWI_VECTOR_0) \ |
| 2374 _op_(EVP_CPU_PREFETCH_ABORT_VECTOR_0) \ |
| 2375 _op_(EVP_CPU_DATA_ABORT_VECTOR_0) \ |
| 2376 _op_(EVP_CPU_RSVD_VECTOR_0) \ |
| 2377 _op_(EVP_CPU_IRQ_VECTOR_0) \ |
| 2378 _op_(EVP_CPU_FIQ_VECTOR_0) \ |
| 2379 _op_(EVP_CPU_IRQ_STS_0) \ |
| 2380 _op_(EVP_CPU_PRI_IRQ_STS_0) \ |
| 2381 _op_(EVP_CPU_FIQ_STS_0) \ |
| 2382 _op_(EVP_CPU_PRI_FIQ_STS_0) \ |
| 2383 _op_(EVP_CPU_PRI_IRQ_NUM_0_0) \ |
| 2384 _op_(EVP_CPU_PRI_IRQ_VEC_0_0) \ |
| 2385 _op_(EVP_CPU_PRI_IRQ_NUM_1_0) \ |
| 2386 _op_(EVP_CPU_PRI_IRQ_VEC_1_0) \ |
| 2387 _op_(EVP_CPU_PRI_IRQ_NUM_2_0) \ |
| 2388 _op_(EVP_CPU_PRI_IRQ_VEC_2_0) \ |
| 2389 _op_(EVP_CPU_PRI_IRQ_NUM_3_0) \ |
| 2390 _op_(EVP_CPU_PRI_IRQ_VEC_3_0) \ |
| 2391 _op_(EVP_CPU_PRI_IRQ_NUM_4_0) \ |
| 2392 _op_(EVP_CPU_PRI_IRQ_VEC_4_0) \ |
| 2393 _op_(EVP_CPU_PRI_IRQ_NUM_5_0) \ |
| 2394 _op_(EVP_CPU_PRI_IRQ_VEC_5_0) \ |
| 2395 _op_(EVP_CPU_PRI_IRQ_NUM_6_0) \ |
| 2396 _op_(EVP_CPU_PRI_IRQ_VEC_6_0) \ |
| 2397 _op_(EVP_CPU_PRI_IRQ_NUM_7_0) \ |
| 2398 _op_(EVP_CPU_PRI_IRQ_VEC_7_0) \ |
| 2399 _op_(EVP_CPU_PRI_FIQ_NUM_0_0) \ |
| 2400 _op_(EVP_CPU_PRI_FIQ_VEC_0_0) \ |
| 2401 _op_(EVP_CPU_PRI_FIQ_NUM_1_0) \ |
| 2402 _op_(EVP_CPU_PRI_FIQ_VEC_1_0) \ |
| 2403 _op_(EVP_CPU_PRI_FIQ_NUM_2_0) \ |
| 2404 _op_(EVP_CPU_PRI_FIQ_VEC_2_0) \ |
| 2405 _op_(EVP_CPU_PRI_FIQ_NUM_3_0) \ |
| 2406 _op_(EVP_CPU_PRI_FIQ_VEC_3_0) \ |
| 2407 _op_(EVP_COP_RESET_VECTOR_0) \ |
| 2408 _op_(EVP_COP_UNDEF_VECTOR_0) \ |
| 2409 _op_(EVP_COP_SWI_VECTOR_0) \ |
| 2410 _op_(EVP_COP_PREFETCH_ABORT_VECTOR_0) \ |
| 2411 _op_(EVP_COP_DATA_ABORT_VECTOR_0) \ |
| 2412 _op_(EVP_COP_RSVD_VECTOR_0) \ |
| 2413 _op_(EVP_COP_IRQ_VECTOR_0) \ |
| 2414 _op_(EVP_COP_FIQ_VECTOR_0) \ |
| 2415 _op_(EVP_COP_IRQ_STS_0) \ |
| 2416 _op_(EVP_COP_PRI_IRQ_STS_0) \ |
| 2417 _op_(EVP_COP_FIQ_STS_0) \ |
| 2418 _op_(EVP_COP_PRI_FIQ_STS_0) \ |
| 2419 _op_(EVP_COP_PRI_IRQ_NUM_0_0) \ |
| 2420 _op_(EVP_COP_PRI_IRQ_VEC_0_0) \ |
| 2421 _op_(EVP_COP_PRI_IRQ_NUM_1_0) \ |
| 2422 _op_(EVP_COP_PRI_IRQ_VEC_1_0) \ |
| 2423 _op_(EVP_COP_PRI_IRQ_NUM_2_0) \ |
| 2424 _op_(EVP_COP_PRI_IRQ_VEC_2_0) \ |
| 2425 _op_(EVP_COP_PRI_IRQ_NUM_3_0) \ |
| 2426 _op_(EVP_COP_PRI_IRQ_VEC_3_0) \ |
| 2427 _op_(EVP_COP_PRI_IRQ_NUM_4_0) \ |
| 2428 _op_(EVP_COP_PRI_IRQ_VEC_4_0) \ |
| 2429 _op_(EVP_COP_PRI_IRQ_NUM_5_0) \ |
| 2430 _op_(EVP_COP_PRI_IRQ_VEC_5_0) \ |
| 2431 _op_(EVP_COP_PRI_IRQ_NUM_6_0) \ |
| 2432 _op_(EVP_COP_PRI_IRQ_VEC_6_0) \ |
| 2433 _op_(EVP_COP_PRI_IRQ_NUM_7_0) \ |
| 2434 _op_(EVP_COP_PRI_IRQ_VEC_7_0) \ |
| 2435 _op_(EVP_COP_PRI_FIQ_NUM_0_0) \ |
| 2436 _op_(EVP_COP_PRI_FIQ_VEC_0_0) \ |
| 2437 _op_(EVP_COP_PRI_FIQ_NUM_1_0) \ |
| 2438 _op_(EVP_COP_PRI_FIQ_VEC_1_0) \ |
| 2439 _op_(EVP_COP_PRI_FIQ_NUM_2_0) \ |
| 2440 _op_(EVP_COP_PRI_FIQ_VEC_2_0) \ |
| 2441 _op_(EVP_COP_PRI_FIQ_NUM_3_0) \ |
| 2442 _op_(EVP_COP_PRI_FIQ_VEC_3_0) |
| 2443 |
| 2444 |
| 2445 // |
| 2446 // ADDRESS SPACES |
| 2447 // |
| 2448 |
| 2449 #define BASE_ADDRESS_EVP 0x00000000 |
| 2450 |
| 2451 // |
| 2452 // AREVP REGISTER BANKS |
| 2453 // |
| 2454 |
| 2455 #define EVP0_FIRST_REG 0x0000 // EVP_RESET_VECTOR_0 |
| 2456 #define EVP0_LAST_REG 0x002c // EVP_PRI_FIQ_STS_0 |
| 2457 #define EVP1_FIRST_REG 0x0040 // EVP_PRI_IRQ_NUM_0_0 |
| 2458 #define EVP1_LAST_REG 0x009c // EVP_PRI_FIQ_VEC_3_0 |
| 2459 #define EVP2_FIRST_REG 0x0100 // EVP_CPU_RESET_VECTOR_0 |
| 2460 #define EVP2_LAST_REG 0x012c // EVP_CPU_PRI_FIQ_STS_0 |
| 2461 #define EVP3_FIRST_REG 0x0140 // EVP_CPU_PRI_IRQ_NUM_0_0 |
| 2462 #define EVP3_LAST_REG 0x019c // EVP_CPU_PRI_FIQ_VEC_3_0 |
| 2463 #define EVP4_FIRST_REG 0x0200 // EVP_COP_RESET_VECTOR_0 |
| 2464 #define EVP4_LAST_REG 0x022c // EVP_COP_PRI_FIQ_STS_0 |
| 2465 #define EVP5_FIRST_REG 0x0240 // EVP_COP_PRI_IRQ_NUM_0_0 |
| 2466 #define EVP5_LAST_REG 0x029c // EVP_COP_PRI_FIQ_VEC_3_0 |
| 2467 |
| 2468 #ifndef _MK_SHIFT_CONST |
| 2469 #define _MK_SHIFT_CONST(_constant_) _constant_ |
| 2470 #endif |
| 2471 #ifndef _MK_MASK_CONST |
| 2472 #define _MK_MASK_CONST(_constant_) _constant_ |
| 2473 #endif |
| 2474 #ifndef _MK_ENUM_CONST |
| 2475 #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) |
| 2476 #endif |
| 2477 #ifndef _MK_ADDR_CONST |
| 2478 #define _MK_ADDR_CONST(_constant_) _constant_ |
| 2479 #endif |
| 2480 |
| 2481 #endif // ifndef ___AREVP_H_INC_ |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 3256004:
[ARM] tegra: add nvos/nvrm/nvmap drivers (Closed)
Base URL: ssh://git@gitrw.chromium.org/kernel.git