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| 1 /* |
| 2 * Copyright (c) 2009 NVIDIA Corporation. |
| 3 * All rights reserved. |
| 4 * |
| 5 * Redistribution and use in source and binary forms, with or without |
| 6 * modification, are permitted provided that the following conditions are met: |
| 7 * |
| 8 * Redistributions of source code must retain the above copyright notice, |
| 9 * this list of conditions and the following disclaimer. |
| 10 * |
| 11 * Redistributions in binary form must reproduce the above copyright notice, |
| 12 * this list of conditions and the following disclaimer in the documentation |
| 13 * and/or other materials provided with the distribution. |
| 14 * |
| 15 * Neither the name of the NVIDIA Corporation nor the names of its contributors |
| 16 * may be used to endorse or promote products derived from this software |
| 17 * without specific prior written permission. |
| 18 * |
| 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 29 * POSSIBILITY OF SUCH DAMAGE. |
| 30 * |
| 31 */ |
| 32 // |
| 33 // DO NOT EDIT - generated by simspec! |
| 34 // |
| 35 |
| 36 #ifndef ___ARAPBPM_H_INC_ |
| 37 #define ___ARAPBPM_H_INC_ |
| 38 |
| 39 // Register APBDEV_PMC_CNTRL_0 |
| 40 #define APBDEV_PMC_CNTRL_0 _MK_ADDR_CONST(0x0) |
| 41 #define APBDEV_PMC_CNTRL_0_SECURE 0x0 |
| 42 #define APBDEV_PMC_CNTRL_0_WORD_COUNT 0x1 |
| 43 #define APBDEV_PMC_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 44 #define APBDEV_PMC_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x7ffff) |
| 45 #define APBDEV_PMC_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 46 #define APBDEV_PMC_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 47 #define APBDEV_PMC_CNTRL_0_READ_MASK _MK_MASK_CONST(0x7ffff) |
| 48 #define APBDEV_PMC_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x7ffff) |
| 49 // Disable 32KHz clock to KBC |
| 50 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT _MK_SHIFT_CONST(
0) |
| 51 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT) |
| 52 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_RANGE 0:0 |
| 53 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_WOFFSET 0x0 |
| 54 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT _MK_MASK_CONST(0
x0) |
| 55 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 56 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 57 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 58 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DISABLE _MK_ENUM_CONST(0
) |
| 59 #define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_ENABLE _MK_ENUM_CONST(1
) |
| 60 |
| 61 // Disable 32KHz clock to RTC |
| 62 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT _MK_SHIFT_CONST(
1) |
| 63 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT) |
| 64 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_RANGE 1:1 |
| 65 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_WOFFSET 0x0 |
| 66 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT _MK_MASK_CONST(0
x0) |
| 67 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 68 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 69 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 70 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DISABLE _MK_ENUM_CONST(0
) |
| 71 #define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_ENABLE _MK_ENUM_CONST(1
) |
| 72 |
| 73 // Software reset to RTC |
| 74 #define APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT _MK_SHIFT_CONST(
2) |
| 75 #define APBDEV_PMC_CNTRL_0_RTC_RST_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT) |
| 76 #define APBDEV_PMC_CNTRL_0_RTC_RST_RANGE 2:2 |
| 77 #define APBDEV_PMC_CNTRL_0_RTC_RST_WOFFSET 0x0 |
| 78 #define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT _MK_MASK_CONST(0
x0) |
| 79 #define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 80 #define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 81 #define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 82 #define APBDEV_PMC_CNTRL_0_RTC_RST_DISABLE _MK_ENUM_CONST(0
) |
| 83 #define APBDEV_PMC_CNTRL_0_RTC_RST_ENABLE _MK_ENUM_CONST(1
) |
| 84 |
| 85 // Software reset to KBC |
| 86 #define APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT _MK_SHIFT_CONST(
3) |
| 87 #define APBDEV_PMC_CNTRL_0_KBC_RST_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT) |
| 88 #define APBDEV_PMC_CNTRL_0_KBC_RST_RANGE 3:3 |
| 89 #define APBDEV_PMC_CNTRL_0_KBC_RST_WOFFSET 0x0 |
| 90 #define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT _MK_MASK_CONST(0
x0) |
| 91 #define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 92 #define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 93 #define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 94 #define APBDEV_PMC_CNTRL_0_KBC_RST_DISABLE _MK_ENUM_CONST(0
) |
| 95 #define APBDEV_PMC_CNTRL_0_KBC_RST_ENABLE _MK_ENUM_CONST(1
) |
| 96 |
| 97 // Reset to CAR - generates 2 clock cycle pulse. |
| 98 #define APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT _MK_SHIFT_CONST(
4) |
| 99 #define APBDEV_PMC_CNTRL_0_MAIN_RST_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT) |
| 100 #define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE 4:4 |
| 101 #define APBDEV_PMC_CNTRL_0_MAIN_RST_WOFFSET 0x0 |
| 102 #define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT _MK_MASK_CONST(0
x0) |
| 103 #define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 104 #define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 105 #define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 106 #define APBDEV_PMC_CNTRL_0_MAIN_RST_DISABLE _MK_ENUM_CONST(0
) |
| 107 #define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE _MK_ENUM_CONST(1
) |
| 108 |
| 109 // Enables latching wakeup events - stops latching on transition from 1 to 0(s
equence - set to 1,set to 0) |
| 110 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT _MK_SHIFT_CONST(
5) |
| 111 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT) |
| 112 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_RANGE 5:5 |
| 113 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_WOFFSET 0x0 |
| 114 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT _MK_MASK_CONST(0
x0) |
| 115 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 116 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 117 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 118 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DISABLE _MK_ENUM_CONST(0
) |
| 119 #define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_ENABLE _MK_ENUM_CONST(1
) |
| 120 |
| 121 // Disable detecting glitch on wakeup event- in default operation glitches are
ignored on wakeup lines. if this bit is set to 1, glitch (event shorter than hal
f 32khz clock, will be causing wakeup from lp0 |
| 122 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT _MK_SHIFT_CONST(
6) |
| 123 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT) |
| 124 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_RANGE 6:6 |
| 125 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_WOFFSET 0x0 |
| 126 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT _MK_MASK
_CONST(0x0) |
| 127 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 128 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 129 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 130 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DISABLE _MK_ENUM
_CONST(0) |
| 131 #define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_ENABLE _MK_ENUM_CONST(1
) |
| 132 |
| 133 // Enables blinking counter and blink output -works only if BLINK field in DPD_P
ADS_ORIDE is set to 1 |
| 134 #define APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT _MK_SHIFT_CONST(
7) |
| 135 #define APBDEV_PMC_CNTRL_0_BLINK_EN_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT) |
| 136 #define APBDEV_PMC_CNTRL_0_BLINK_EN_RANGE 7:7 |
| 137 #define APBDEV_PMC_CNTRL_0_BLINK_EN_WOFFSET 0x0 |
| 138 #define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT _MK_MASK_CONST(0
x0) |
| 139 #define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 140 #define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 141 #define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 142 #define APBDEV_PMC_CNTRL_0_BLINK_EN_DISABLE _MK_ENUM_CONST(0
) |
| 143 #define APBDEV_PMC_CNTRL_0_BLINK_EN_ENABLE _MK_ENUM_CONST(1
) |
| 144 |
| 145 // Inverts power request polarity |
| 146 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT _MK_SHIF
T_CONST(8) |
| 147 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT) |
| 148 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_RANGE 8:8 |
| 149 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_WOFFSET 0x0 |
| 150 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT _MK_MASK
_CONST(0x0) |
| 151 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 152 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 153 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 154 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_NORMAL _MK_ENUM
_CONST(0) |
| 155 #define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_INVERT _MK_ENUM
_CONST(1) |
| 156 |
| 157 // Power request output enable. resets to tristate |
| 158 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT _MK_SHIFT_CONST(
9) |
| 159 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT) |
| 160 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_RANGE 9:9 |
| 161 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_WOFFSET 0x0 |
| 162 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT _MK_MASK_CONST(0
x0) |
| 163 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 164 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 165 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 166 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DISABLE _MK_ENUM_CONST(0
) |
| 167 #define APBDEV_PMC_CNTRL_0_PWRREQ_OE_ENABLE _MK_ENUM_CONST(1
) |
| 168 |
| 169 // Inverts system clock enable polarity |
| 170 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT _MK_SHIF
T_CONST(10) |
| 171 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT) |
| 172 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_RANGE 10:10 |
| 173 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_WOFFSET 0x0 |
| 174 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT _MK_MASK
_CONST(0x0) |
| 175 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 176 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 177 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 178 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_NORMAL _MK_ENUM
_CONST(0) |
| 179 #define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_INVERT _MK_ENUM
_CONST(1) |
| 180 |
| 181 // Enables output of system enable clock - works only if SYS_CLK field in DPD_PA
DS_ORIDE is set to 1. resets to tristate |
| 182 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT _MK_SHIFT_CONST(
11) |
| 183 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT) |
| 184 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_RANGE 11:11 |
| 185 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_WOFFSET 0x0 |
| 186 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT _MK_MASK_CONST(0
x0) |
| 187 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 188 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 189 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 190 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DISABLE _MK_ENUM_CONST(0
) |
| 191 #define APBDEV_PMC_CNTRL_0_SYSCLK_OE_ENABLE _MK_ENUM_CONST(1
) |
| 192 |
| 193 // Disable power gating - global override, will override function of PWRGATE_TO
GGLE register. all partitions will stay enabled. |
| 194 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT _MK_SHIFT_CONST(
12) |
| 195 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT) |
| 196 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_RANGE 12:12 |
| 197 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_WOFFSET 0x0 |
| 198 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT _MK_MASK_CONST(0
x0) |
| 199 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 200 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 201 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 202 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DISABLE _MK_ENUM_CONST(0
) |
| 203 #define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_ENABLE _MK_ENUM_CONST(1
) |
| 204 |
| 205 // AO intitlized purely sftw diagnostic and interpretation |
| 206 #define APBDEV_PMC_CNTRL_0_AOINIT_SHIFT _MK_SHIFT_CONST(13) |
| 207 #define APBDEV_PMC_CNTRL_0_AOINIT_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_CNTRL_0_AOINIT_SHIFT) |
| 208 #define APBDEV_PMC_CNTRL_0_AOINIT_RANGE 13:13 |
| 209 #define APBDEV_PMC_CNTRL_0_AOINIT_WOFFSET 0x0 |
| 210 #define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT _MK_MASK_CONST(0
x0) |
| 211 #define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 212 #define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 213 #define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 214 #define APBDEV_PMC_CNTRL_0_AOINIT_NOTDONE _MK_ENUM_CONST(0
) |
| 215 #define APBDEV_PMC_CNTRL_0_AOINIT_DONE _MK_ENUM_CONST(1) |
| 216 |
| 217 // when set causes side effect of entering lp0 after powering down cpu |
| 218 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT _MK_SHIF
T_CONST(14) |
| 219 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT) |
| 220 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_RANGE 14:14 |
| 221 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET 0x0 |
| 222 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT _MK_MASK
_CONST(0x0) |
| 223 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 224 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 225 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 226 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DISABLE _MK_ENUM
_CONST(0) |
| 227 #define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_ENABLE _MK_ENUM
_CONST(1) |
| 228 |
| 229 // Inverts power request polarity |
| 230 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT _MK_SHIF
T_CONST(15) |
| 231 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT) |
| 232 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_RANGE 15:15 |
| 233 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_WOFFSET 0x0 |
| 234 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT _MK_MASK
_CONST(0x0) |
| 235 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 236 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 237 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 238 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_NORMAL _MK_ENUM
_CONST(0) |
| 239 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_INVERT _MK_ENUM
_CONST(1) |
| 240 |
| 241 // Power request output enable. resets to tristate |
| 242 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT _MK_SHIFT_CONST(
16) |
| 243 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT) |
| 244 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_RANGE 16:16 |
| 245 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_WOFFSET 0x0 |
| 246 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT _MK_MASK_CONST(0
x0) |
| 247 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 248 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 249 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 250 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DISABLE _MK_ENUM_CONST(0
) |
| 251 #define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE _MK_ENUM_CONST(1
) |
| 252 |
| 253 // Inverts INTR polarity |
| 254 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT _MK_SHIFT_CONST(
17) |
| 255 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT) |
| 256 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_RANGE 17:17 |
| 257 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_WOFFSET 0x0 |
| 258 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT _MK_MASK
_CONST(0x0) |
| 259 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 260 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 261 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 262 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DISABLE _MK_ENUM
_CONST(0) |
| 263 #define APBDEV_PMC_CNTRL_0_INTR_POLARITY_ENABLE _MK_ENUM_CONST(1
) |
| 264 |
| 265 // Fuse override |
| 266 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT _MK_SHIFT_CONST(
18) |
| 267 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT) |
| 268 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_RANGE 18:18 |
| 269 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_WOFFSET 0x0 |
| 270 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT _MK_MASK
_CONST(0x0) |
| 271 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 272 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 273 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 274 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DISABLE _MK_ENUM
_CONST(0) |
| 275 #define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_ENABLE _MK_ENUM_CONST(1
) |
| 276 |
| 277 |
| 278 // Register APBDEV_PMC_SEC_DISABLE_0 |
| 279 #define APBDEV_PMC_SEC_DISABLE_0 _MK_ADDR_CONST(0x4) |
| 280 #define APBDEV_PMC_SEC_DISABLE_0_SECURE 0x0 |
| 281 #define APBDEV_PMC_SEC_DISABLE_0_WORD_COUNT 0x1 |
| 282 #define APBDEV_PMC_SEC_DISABLE_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 283 #define APBDEV_PMC_SEC_DISABLE_0_RESET_MASK _MK_MASK_CONST(0
xf) |
| 284 #define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 285 #define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 286 #define APBDEV_PMC_SEC_DISABLE_0_READ_MASK _MK_MASK_CONST(0
xf) |
| 287 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_MASK _MK_MASK_CONST(0
xf) |
| 288 // disable write to secure registers |
| 289 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT _MK_SHIFT_CONST(
0) |
| 290 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT) |
| 291 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_RANGE 0:0 |
| 292 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_WOFFSET 0x0 |
| 293 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT _MK_MASK_CONST(0
x0) |
| 294 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 295 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 296 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 297 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_OFF _MK_ENUM_CONST(0
) |
| 298 #define APBDEV_PMC_SEC_DISABLE_0_WRITE_ON _MK_ENUM_CONST(1
) |
| 299 |
| 300 // disable read from secure registers |
| 301 #define APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT _MK_SHIFT_CONST(
1) |
| 302 #define APBDEV_PMC_SEC_DISABLE_0_READ_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT) |
| 303 #define APBDEV_PMC_SEC_DISABLE_0_READ_RANGE 1:1 |
| 304 #define APBDEV_PMC_SEC_DISABLE_0_READ_WOFFSET 0x0 |
| 305 #define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT _MK_MASK_CONST(0
x0) |
| 306 #define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 307 #define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 308 #define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 309 #define APBDEV_PMC_SEC_DISABLE_0_READ_OFF _MK_ENUM_CONST(0
) |
| 310 #define APBDEV_PMC_SEC_DISABLE_0_READ_ON _MK_ENUM_CONST(1
) |
| 311 |
| 312 // disable write to bondout secure registers |
| 313 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT _MK_SHIFT_CONST(
2) |
| 314 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT) |
| 315 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_RANGE 2:2 |
| 316 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_WOFFSET 0x0 |
| 317 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT _MK_MASK_CONST(0
x0) |
| 318 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 319 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 320 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 321 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_OFF _MK_ENUM_CONST(0
) |
| 322 #define APBDEV_PMC_SEC_DISABLE_0_BWRITE_ON _MK_ENUM_CONST(1
) |
| 323 |
| 324 // disable read from bondout secure registers |
| 325 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT _MK_SHIFT_CONST(
3) |
| 326 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT) |
| 327 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_RANGE 3:3 |
| 328 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_WOFFSET 0x0 |
| 329 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT _MK_MASK_CONST(0
x0) |
| 330 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 331 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 332 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 333 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_OFF _MK_ENUM_CONST(0
) |
| 334 #define APBDEV_PMC_SEC_DISABLE_0_BREAD_ON _MK_ENUM_CONST(1
) |
| 335 |
| 336 |
| 337 // Register APBDEV_PMC_PMC_SWRST_0 |
| 338 #define APBDEV_PMC_PMC_SWRST_0 _MK_ADDR_CONST(0x8) |
| 339 #define APBDEV_PMC_PMC_SWRST_0_SECURE 0x0 |
| 340 #define APBDEV_PMC_PMC_SWRST_0_WORD_COUNT 0x1 |
| 341 #define APBDEV_PMC_PMC_SWRST_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 342 #define APBDEV_PMC_PMC_SWRST_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 343 #define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 344 #define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 345 #define APBDEV_PMC_PMC_SWRST_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 346 #define APBDEV_PMC_PMC_SWRST_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 347 //software reset to pmc only |
| 348 #define APBDEV_PMC_PMC_SWRST_0_RST_SHIFT _MK_SHIFT_CONST(
0) |
| 349 #define APBDEV_PMC_PMC_SWRST_0_RST_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PMC_SWRST_0_RST_SHIFT) |
| 350 #define APBDEV_PMC_PMC_SWRST_0_RST_RANGE 0:0 |
| 351 #define APBDEV_PMC_PMC_SWRST_0_RST_WOFFSET 0x0 |
| 352 #define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT _MK_MASK_CONST(0
x0) |
| 353 #define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 354 #define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 355 #define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 356 #define APBDEV_PMC_PMC_SWRST_0_RST_DISABLE _MK_ENUM_CONST(0
) |
| 357 #define APBDEV_PMC_PMC_SWRST_0_RST_ENABLE _MK_ENUM_CONST(1
) |
| 358 |
| 359 |
| 360 // Register APBDEV_PMC_WAKE_MASK_0 |
| 361 #define APBDEV_PMC_WAKE_MASK_0 _MK_ADDR_CONST(0xc) |
| 362 #define APBDEV_PMC_WAKE_MASK_0_SECURE 0x0 |
| 363 #define APBDEV_PMC_WAKE_MASK_0_WORD_COUNT 0x1 |
| 364 #define APBDEV_PMC_WAKE_MASK_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 365 #define APBDEV_PMC_WAKE_MASK_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 366 #define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 367 #define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 368 #define APBDEV_PMC_WAKE_MASK_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 369 #define APBDEV_PMC_WAKE_MASK_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 370 // pin 0-15 wake enable |
| 371 #define APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT _MK_SHIFT_CONST(
0) |
| 372 #define APBDEV_PMC_WAKE_MASK_0_EVENT_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT) |
| 373 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RANGE 15:0 |
| 374 #define APBDEV_PMC_WAKE_MASK_0_EVENT_WOFFSET 0x0 |
| 375 #define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT _MK_MASK_CONST(0
x0) |
| 376 #define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 377 #define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 378 #define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 379 #define APBDEV_PMC_WAKE_MASK_0_EVENT_DISABLE _MK_ENUM_CONST(0
) |
| 380 #define APBDEV_PMC_WAKE_MASK_0_EVENT_ENABLE _MK_ENUM_CONST(1
) |
| 381 |
| 382 // RTC wake enable |
| 383 #define APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT _MK_SHIFT_CONST(
16) |
| 384 #define APBDEV_PMC_WAKE_MASK_0_RTC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT) |
| 385 #define APBDEV_PMC_WAKE_MASK_0_RTC_RANGE 16:16 |
| 386 #define APBDEV_PMC_WAKE_MASK_0_RTC_WOFFSET 0x0 |
| 387 #define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT _MK_MASK_CONST(0
x0) |
| 388 #define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 389 #define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 390 #define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 391 #define APBDEV_PMC_WAKE_MASK_0_RTC_DISABLE _MK_ENUM_CONST(0
) |
| 392 #define APBDEV_PMC_WAKE_MASK_0_RTC_ENABLE _MK_ENUM_CONST(1
) |
| 393 |
| 394 // KBC wake enable |
| 395 #define APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT _MK_SHIFT_CONST(
17) |
| 396 #define APBDEV_PMC_WAKE_MASK_0_KBC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT) |
| 397 #define APBDEV_PMC_WAKE_MASK_0_KBC_RANGE 17:17 |
| 398 #define APBDEV_PMC_WAKE_MASK_0_KBC_WOFFSET 0x0 |
| 399 #define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT _MK_MASK_CONST(0
x0) |
| 400 #define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 401 #define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 402 #define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 403 #define APBDEV_PMC_WAKE_MASK_0_KBC_DISABLE _MK_ENUM_CONST(0
) |
| 404 #define APBDEV_PMC_WAKE_MASK_0_KBC_ENABLE _MK_ENUM_CONST(1
) |
| 405 |
| 406 // PWR_INT wake enable |
| 407 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT _MK_SHIFT_CONST(
18) |
| 408 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT) |
| 409 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_RANGE 18:18 |
| 410 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_WOFFSET 0x0 |
| 411 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT _MK_MASK_CONST(0
x0) |
| 412 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 413 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 414 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 415 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DISABLE _MK_ENUM_CONST(0
) |
| 416 #define APBDEV_PMC_WAKE_MASK_0_PWR_INT_ENABLE _MK_ENUM_CONST(1
) |
| 417 |
| 418 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT _MK_SHIFT_CONST(
19) |
| 419 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_FIELD (_MK_MASK_CONST(
0xf) << APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT) |
| 420 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_RANGE 22:19 |
| 421 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_WOFFSET 0x0 |
| 422 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT _MK_MASK
_CONST(0x0) |
| 423 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 424 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 425 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 426 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_LOW _MK_ENUM
_CONST(0) |
| 427 #define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_HIGH _MK_ENUM
_CONST(1) |
| 428 |
| 429 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT _MK_SHIFT_CONST(
23) |
| 430 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_FIELD (_MK_MASK_CONST(
0xff) << APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT) |
| 431 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_RANGE 30:23 |
| 432 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_WOFFSET 0x0 |
| 433 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT _MK_MASK
_CONST(0x0) |
| 434 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 435 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 436 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 437 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DISABLE _MK_ENUM
_CONST(0) |
| 438 #define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_ENABLE _MK_ENUM_CONST(1
) |
| 439 |
| 440 // external reset wake enable |
| 441 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT _MK_SHIFT_CONST(
31) |
| 442 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT) |
| 443 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_RANGE 31:31 |
| 444 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_WOFFSET 0x0 |
| 445 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT _MK_MASK_CONST(0
x0) |
| 446 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 447 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 448 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 449 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_DISABLE _MK_ENUM_CONST(0
) |
| 450 #define APBDEV_PMC_WAKE_MASK_0_RESET_N_ENABLE _MK_ENUM_CONST(1
) |
| 451 |
| 452 |
| 453 // Register APBDEV_PMC_WAKE_LVL_0 |
| 454 #define APBDEV_PMC_WAKE_LVL_0 _MK_ADDR_CONST(0x10) |
| 455 #define APBDEV_PMC_WAKE_LVL_0_SECURE 0x0 |
| 456 #define APBDEV_PMC_WAKE_LVL_0_WORD_COUNT 0x1 |
| 457 #define APBDEV_PMC_WAKE_LVL_0_RESET_VAL _MK_MASK_CONST(0
x7f9fffff) |
| 458 #define APBDEV_PMC_WAKE_LVL_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 459 #define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 460 #define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 461 #define APBDEV_PMC_WAKE_LVL_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 462 #define APBDEV_PMC_WAKE_LVL_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 463 // pin 0-15 wake level |
| 464 #define APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT _MK_SHIFT_CONST(
0) |
| 465 #define APBDEV_PMC_WAKE_LVL_0_EVENT_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT) |
| 466 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RANGE 15:0 |
| 467 #define APBDEV_PMC_WAKE_LVL_0_EVENT_WOFFSET 0x0 |
| 468 #define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT _MK_MASK_CONST(0
xffff) |
| 469 #define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 470 #define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 471 #define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 472 #define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_LOW _MK_ENUM_CONST(0
) |
| 473 #define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_HIGH _MK_ENUM_CONST(1
) |
| 474 |
| 475 // RTC wake level |
| 476 #define APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT _MK_SHIFT_CONST(16) |
| 477 #define APBDEV_PMC_WAKE_LVL_0_RTC_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT) |
| 478 #define APBDEV_PMC_WAKE_LVL_0_RTC_RANGE 16:16 |
| 479 #define APBDEV_PMC_WAKE_LVL_0_RTC_WOFFSET 0x0 |
| 480 #define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT _MK_MASK_CONST(0
x1) |
| 481 #define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 482 #define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 483 #define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 484 #define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_LOW _MK_ENUM_CONST(0
) |
| 485 #define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_HIGH _MK_ENUM_CONST(1
) |
| 486 |
| 487 // KBC wake level |
| 488 #define APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT _MK_SHIFT_CONST(17) |
| 489 #define APBDEV_PMC_WAKE_LVL_0_KBC_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT) |
| 490 #define APBDEV_PMC_WAKE_LVL_0_KBC_RANGE 17:17 |
| 491 #define APBDEV_PMC_WAKE_LVL_0_KBC_WOFFSET 0x0 |
| 492 #define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT _MK_MASK_CONST(0
x1) |
| 493 #define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 494 #define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 495 #define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 496 #define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_LOW _MK_ENUM_CONST(0
) |
| 497 #define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_HIGH _MK_ENUM_CONST(1
) |
| 498 |
| 499 // power interrupt - now pernamently tied to bit 18 |
| 500 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT _MK_SHIFT_CONST(
18) |
| 501 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT) |
| 502 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_RANGE 18:18 |
| 503 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_WOFFSET 0x0 |
| 504 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT _MK_MASK_CONST(0
x1) |
| 505 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 506 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 507 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 508 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_LOW _MK_ENUM
_CONST(0) |
| 509 #define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_HIGH _MK_ENUM
_CONST(1) |
| 510 |
| 511 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT _MK_SHIFT_CONST(
19) |
| 512 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_FIELD (_MK_MASK_CONST(
0xf) << APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT) |
| 513 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_RANGE 22:19 |
| 514 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_WOFFSET 0x0 |
| 515 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT _MK_MASK_CONST(0
x3) |
| 516 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 517 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 518 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 519 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_LOW _MK_ENUM
_CONST(0) |
| 520 #define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_HIGH _MK_ENUM
_CONST(1) |
| 521 |
| 522 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT _MK_SHIFT_CONST(
23) |
| 523 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_FIELD (_MK_MASK_CONST(
0xff) << APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT) |
| 524 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_RANGE 30:23 |
| 525 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_WOFFSET 0x0 |
| 526 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT _MK_MASK_CONST(0
xff) |
| 527 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 528 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 529 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 530 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_LOW _MK_ENUM
_CONST(0) |
| 531 #define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_HIGH _MK_ENUM
_CONST(1) |
| 532 |
| 533 // external reset wake level (low active!) |
| 534 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT _MK_SHIFT_CONST(
31) |
| 535 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT) |
| 536 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_RANGE 31:31 |
| 537 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_WOFFSET 0x0 |
| 538 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT _MK_MASK_CONST(0
x0) |
| 539 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 540 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 541 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 542 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_LOW _MK_ENUM
_CONST(0) |
| 543 #define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_HIGH _MK_ENUM
_CONST(1) |
| 544 |
| 545 |
| 546 // Register APBDEV_PMC_WAKE_STATUS_0 |
| 547 #define APBDEV_PMC_WAKE_STATUS_0 _MK_ADDR_CONST(0x14) |
| 548 #define APBDEV_PMC_WAKE_STATUS_0_SECURE 0x0 |
| 549 #define APBDEV_PMC_WAKE_STATUS_0_WORD_COUNT 0x1 |
| 550 #define APBDEV_PMC_WAKE_STATUS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 551 #define APBDEV_PMC_WAKE_STATUS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 552 #define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 553 #define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 554 #define APBDEV_PMC_WAKE_STATUS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 555 #define APBDEV_PMC_WAKE_STATUS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 556 // pin 0-15 wake |
| 557 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT _MK_SHIFT_CONST(
0) |
| 558 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT) |
| 559 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RANGE 15:0 |
| 560 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_WOFFSET 0x0 |
| 561 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT _MK_MASK_CONST(0
x0) |
| 562 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 563 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 564 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 565 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_NOT_SET _MK_ENUM_CONST(0
) |
| 566 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_SET _MK_ENUM_CONST(1
) |
| 567 |
| 568 // RTC wake |
| 569 #define APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT _MK_SHIFT_CONST(
16) |
| 570 #define APBDEV_PMC_WAKE_STATUS_0_RTC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT) |
| 571 #define APBDEV_PMC_WAKE_STATUS_0_RTC_RANGE 16:16 |
| 572 #define APBDEV_PMC_WAKE_STATUS_0_RTC_WOFFSET 0x0 |
| 573 #define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT _MK_MASK_CONST(0
x0) |
| 574 #define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 575 #define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 576 #define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 577 #define APBDEV_PMC_WAKE_STATUS_0_RTC_NOT_SET _MK_ENUM_CONST(0
) |
| 578 #define APBDEV_PMC_WAKE_STATUS_0_RTC_SET _MK_ENUM_CONST(1
) |
| 579 |
| 580 // KBC wake |
| 581 #define APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT _MK_SHIFT_CONST(
17) |
| 582 #define APBDEV_PMC_WAKE_STATUS_0_KBC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT) |
| 583 #define APBDEV_PMC_WAKE_STATUS_0_KBC_RANGE 17:17 |
| 584 #define APBDEV_PMC_WAKE_STATUS_0_KBC_WOFFSET 0x0 |
| 585 #define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT _MK_MASK_CONST(0
x0) |
| 586 #define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 587 #define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 588 #define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 589 #define APBDEV_PMC_WAKE_STATUS_0_KBC_NOT_SET _MK_ENUM_CONST(0
) |
| 590 #define APBDEV_PMC_WAKE_STATUS_0_KBC_SET _MK_ENUM_CONST(1
) |
| 591 |
| 592 // power interrupt |
| 593 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT _MK_SHIFT_CONST(
18) |
| 594 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT) |
| 595 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_RANGE 18:18 |
| 596 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_WOFFSET 0x0 |
| 597 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT _MK_MASK
_CONST(0x0) |
| 598 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 599 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 600 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 601 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_NOT_SET _MK_ENUM
_CONST(0) |
| 602 #define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SET _MK_ENUM_CONST(1
) |
| 603 |
| 604 // USB wake events |
| 605 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT _MK_SHIF
T_CONST(19) |
| 606 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT) |
| 607 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_RANGE 22:19 |
| 608 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_WOFFSET 0x0 |
| 609 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT _MK_MASK
_CONST(0x0) |
| 610 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 611 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 612 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 613 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_NOT_SET _MK_ENUM
_CONST(0) |
| 614 #define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SET _MK_ENUM_CONST(1
) |
| 615 |
| 616 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT _MK_SHIF
T_CONST(23) |
| 617 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_FIELD (_MK_MAS
K_CONST(0xff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT) |
| 618 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_RANGE 30:23 |
| 619 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_WOFFSET 0x0 |
| 620 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT _MK_MASK
_CONST(0x0) |
| 621 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 622 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 623 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 624 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_NOT_SET _MK_ENUM
_CONST(0) |
| 625 #define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SET _MK_ENUM_CONST(1
) |
| 626 |
| 627 // external reset |
| 628 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT _MK_SHIFT_CONST(
31) |
| 629 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT) |
| 630 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_RANGE 31:31 |
| 631 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_WOFFSET 0x0 |
| 632 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT _MK_MASK
_CONST(0x0) |
| 633 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 634 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 635 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 636 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_NOT_SET _MK_ENUM
_CONST(0) |
| 637 #define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SET _MK_ENUM_CONST(1
) |
| 638 |
| 639 |
| 640 // Register APBDEV_PMC_SW_WAKE_STATUS_0 |
| 641 #define APBDEV_PMC_SW_WAKE_STATUS_0 _MK_ADDR_CONST(0x18) |
| 642 #define APBDEV_PMC_SW_WAKE_STATUS_0_SECURE 0x0 |
| 643 #define APBDEV_PMC_SW_WAKE_STATUS_0_WORD_COUNT 0x1 |
| 644 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 645 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 646 #define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 647 #define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 648 #define APBDEV_PMC_SW_WAKE_STATUS_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 649 #define APBDEV_PMC_SW_WAKE_STATUS_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 650 // pin 0-15 wake |
| 651 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT _MK_SHIFT_CONST(
0) |
| 652 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT) |
| 653 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RANGE 15:0 |
| 654 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_WOFFSET 0x0 |
| 655 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT _MK_MASK
_CONST(0x0) |
| 656 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 657 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 658 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 659 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DISABLE _MK_ENUM
_CONST(0) |
| 660 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_ENABLE _MK_ENUM
_CONST(1) |
| 661 |
| 662 // RTC wake |
| 663 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT _MK_SHIFT_CONST(
16) |
| 664 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT) |
| 665 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_RANGE 16:16 |
| 666 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_WOFFSET 0x0 |
| 667 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT _MK_MASK_CONST(0
x0) |
| 668 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 669 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 670 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 671 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DISABLE _MK_ENUM_CONST(0
) |
| 672 #define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_ENABLE _MK_ENUM_CONST(1
) |
| 673 |
| 674 // KBC wake |
| 675 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT _MK_SHIFT_CONST(
17) |
| 676 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT) |
| 677 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_RANGE 17:17 |
| 678 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_WOFFSET 0x0 |
| 679 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT _MK_MASK_CONST(0
x0) |
| 680 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 681 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 682 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 683 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DISABLE _MK_ENUM_CONST(0
) |
| 684 #define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_ENABLE _MK_ENUM_CONST(1
) |
| 685 |
| 686 // power interrupt |
| 687 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT _MK_SHIF
T_CONST(18) |
| 688 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT) |
| 689 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_RANGE 18:18 |
| 690 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_WOFFSET 0x0 |
| 691 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT _MK_MASK
_CONST(0x0) |
| 692 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 693 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 694 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 695 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_NOT_SET _MK_ENUM
_CONST(0) |
| 696 #define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SET _MK_ENUM_CONST(1
) |
| 697 |
| 698 // USB wake events |
| 699 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT _MK_SHIF
T_CONST(19) |
| 700 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT) |
| 701 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_RANGE 22:19 |
| 702 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_WOFFSET 0x0 |
| 703 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT _MK_MASK
_CONST(0x0) |
| 704 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 705 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 706 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 707 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_NOT_SET _MK_ENUM
_CONST(0) |
| 708 #define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SET _MK_ENUM
_CONST(1) |
| 709 |
| 710 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT _MK_SHIF
T_CONST(23) |
| 711 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_FIELD (_MK_MAS
K_CONST(0xff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT) |
| 712 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_RANGE 30:23 |
| 713 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_WOFFSET 0x0 |
| 714 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT _MK_MASK
_CONST(0x0) |
| 715 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK
_MK_MASK_CONST(0xff) |
| 716 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 717 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 718 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_NOT_SET _MK_ENUM
_CONST(0) |
| 719 #define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SET _MK_ENUM
_CONST(1) |
| 720 |
| 721 // external reset |
| 722 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT _MK_SHIF
T_CONST(31) |
| 723 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT) |
| 724 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_RANGE 31:31 |
| 725 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_WOFFSET 0x0 |
| 726 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT _MK_MASK
_CONST(0x0) |
| 727 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 728 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 729 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 730 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_NOT_SET _MK_ENUM
_CONST(0) |
| 731 #define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SET _MK_ENUM_CONST(1
) |
| 732 |
| 733 |
| 734 // Register APBDEV_PMC_DPD_PADS_ORIDE_0 |
| 735 #define APBDEV_PMC_DPD_PADS_ORIDE_0 _MK_ADDR_CONST(0x1c) |
| 736 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SECURE 0x0 |
| 737 #define APBDEV_PMC_DPD_PADS_ORIDE_0_WORD_COUNT 0x1 |
| 738 #define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_VAL _MK_MASK_CONST(0
x200000) |
| 739 #define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_MASK _MK_MASK_CONST(0
x3ffffff) |
| 740 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 741 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 742 #define APBDEV_PMC_DPD_PADS_ORIDE_0_READ_MASK _MK_MASK_CONST(0
x3ffffff) |
| 743 #define APBDEV_PMC_DPD_PADS_ORIDE_0_WRITE_MASK _MK_MASK_CONST(0
x3ffffff) |
| 744 //override dpd idle state with column 0 output |
| 745 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT _MK_SHIF
T_CONST(0) |
| 746 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT) |
| 747 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_RANGE 0:0 |
| 748 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_WOFFSET 0x0 |
| 749 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT _MK_MASK
_CONST(0x0) |
| 750 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 751 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 752 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 753 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DISABLE _MK_ENUM
_CONST(0) |
| 754 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_ENABLE _MK_ENUM
_CONST(1) |
| 755 |
| 756 //override dpd idle state with column 1 output |
| 757 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT _MK_SHIF
T_CONST(1) |
| 758 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT) |
| 759 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_RANGE 1:1 |
| 760 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_WOFFSET 0x0 |
| 761 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT _MK_MASK
_CONST(0x0) |
| 762 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 763 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 764 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 765 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DISABLE _MK_ENUM
_CONST(0) |
| 766 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_ENABLE _MK_ENUM
_CONST(1) |
| 767 |
| 768 //override dpd idle state with column 2 output |
| 769 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT _MK_SHIF
T_CONST(2) |
| 770 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT) |
| 771 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_RANGE 2:2 |
| 772 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_WOFFSET 0x0 |
| 773 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT _MK_MASK
_CONST(0x0) |
| 774 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 775 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 776 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 777 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DISABLE _MK_ENUM
_CONST(0) |
| 778 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_ENABLE _MK_ENUM
_CONST(1) |
| 779 |
| 780 //override dpd idle state with column 3 output |
| 781 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT _MK_SHIF
T_CONST(3) |
| 782 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT) |
| 783 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_RANGE 3:3 |
| 784 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_WOFFSET 0x0 |
| 785 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT _MK_MASK
_CONST(0x0) |
| 786 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 787 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 788 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 789 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DISABLE _MK_ENUM
_CONST(0) |
| 790 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_ENABLE _MK_ENUM
_CONST(1) |
| 791 |
| 792 //override dpd idle state with column 4 output |
| 793 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT _MK_SHIF
T_CONST(4) |
| 794 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT) |
| 795 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_RANGE 4:4 |
| 796 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_WOFFSET 0x0 |
| 797 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT _MK_MASK
_CONST(0x0) |
| 798 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 799 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 800 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 801 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DISABLE _MK_ENUM
_CONST(0) |
| 802 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_ENABLE _MK_ENUM
_CONST(1) |
| 803 |
| 804 //override dpd idle state with column 5 output |
| 805 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT _MK_SHIF
T_CONST(5) |
| 806 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT) |
| 807 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_RANGE 5:5 |
| 808 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_WOFFSET 0x0 |
| 809 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT _MK_MASK
_CONST(0x0) |
| 810 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 811 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 812 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 813 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DISABLE _MK_ENUM
_CONST(0) |
| 814 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_ENABLE _MK_ENUM
_CONST(1) |
| 815 |
| 816 //override dpd idle state with column 6 output |
| 817 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT _MK_SHIF
T_CONST(6) |
| 818 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT) |
| 819 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_RANGE 6:6 |
| 820 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_WOFFSET 0x0 |
| 821 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT _MK_MASK
_CONST(0x0) |
| 822 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 823 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 824 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 825 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DISABLE _MK_ENUM
_CONST(0) |
| 826 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_ENABLE _MK_ENUM
_CONST(1) |
| 827 |
| 828 //override dpd idle state with column 7 output |
| 829 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT _MK_SHIF
T_CONST(7) |
| 830 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT) |
| 831 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_RANGE 7:7 |
| 832 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_WOFFSET 0x0 |
| 833 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT _MK_MASK
_CONST(0x0) |
| 834 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 835 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 836 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 837 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DISABLE _MK_ENUM
_CONST(0) |
| 838 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_ENABLE _MK_ENUM
_CONST(1) |
| 839 |
| 840 //override dpd idle state with column 8 output |
| 841 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT _MK_SHIF
T_CONST(8) |
| 842 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT) |
| 843 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_RANGE 8:8 |
| 844 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_WOFFSET 0x0 |
| 845 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT _MK_MASK
_CONST(0x0) |
| 846 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 847 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 848 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 849 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DISABLE _MK_ENUM
_CONST(0) |
| 850 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_ENABLE _MK_ENUM
_CONST(1) |
| 851 |
| 852 //override dpd idle state with column 9 output |
| 853 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT _MK_SHIF
T_CONST(9) |
| 854 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT) |
| 855 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_RANGE 9:9 |
| 856 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_WOFFSET 0x0 |
| 857 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT _MK_MASK
_CONST(0x0) |
| 858 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 859 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 860 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 861 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DISABLE _MK_ENUM
_CONST(0) |
| 862 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_ENABLE _MK_ENUM
_CONST(1) |
| 863 |
| 864 //override dpd idle state with column 10 output |
| 865 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT _MK_SHIF
T_CONST(10) |
| 866 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT) |
| 867 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_RANGE 10:10 |
| 868 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_WOFFSET 0x0 |
| 869 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT _MK_MASK
_CONST(0x0) |
| 870 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 871 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 872 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 873 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DISABLE _MK_ENUM
_CONST(0) |
| 874 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_ENABLE _MK_ENUM
_CONST(1) |
| 875 |
| 876 //override dpd idle state with column 11 output |
| 877 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT _MK_SHIF
T_CONST(11) |
| 878 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT) |
| 879 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_RANGE 11:11 |
| 880 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_WOFFSET 0x0 |
| 881 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT _MK_MASK
_CONST(0x0) |
| 882 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 883 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 884 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 885 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DISABLE _MK_ENUM
_CONST(0) |
| 886 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_ENABLE _MK_ENUM
_CONST(1) |
| 887 |
| 888 //override dpd idle state with column 12 output |
| 889 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT _MK_SHIF
T_CONST(12) |
| 890 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT) |
| 891 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_RANGE 12:12 |
| 892 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_WOFFSET 0x0 |
| 893 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT _MK_MASK
_CONST(0x0) |
| 894 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 895 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 896 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 897 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DISABLE _MK_ENUM
_CONST(0) |
| 898 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_ENABLE _MK_ENUM
_CONST(1) |
| 899 |
| 900 //override dpd idle state with row 0 output |
| 901 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT _MK_SHIF
T_CONST(13) |
| 902 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT) |
| 903 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_RANGE 13:13 |
| 904 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_WOFFSET 0x0 |
| 905 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT _MK_MASK
_CONST(0x0) |
| 906 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 907 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 908 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 909 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DISABLE _MK_ENUM
_CONST(0) |
| 910 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_ENABLE _MK_ENUM
_CONST(1) |
| 911 |
| 912 //override dpd idle state with row 1 output |
| 913 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT _MK_SHIF
T_CONST(14) |
| 914 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT) |
| 915 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_RANGE 14:14 |
| 916 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_WOFFSET 0x0 |
| 917 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT _MK_MASK
_CONST(0x0) |
| 918 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 919 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 920 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 921 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DISABLE _MK_ENUM
_CONST(0) |
| 922 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_ENABLE _MK_ENUM
_CONST(1) |
| 923 |
| 924 //override dpd idle state with row 2 output |
| 925 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT _MK_SHIF
T_CONST(15) |
| 926 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT) |
| 927 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_RANGE 15:15 |
| 928 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_WOFFSET 0x0 |
| 929 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT _MK_MASK
_CONST(0x0) |
| 930 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 931 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 932 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 933 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DISABLE _MK_ENUM
_CONST(0) |
| 934 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_ENABLE _MK_ENUM
_CONST(1) |
| 935 |
| 936 //override dpd idle state with row 3 output |
| 937 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT _MK_SHIF
T_CONST(16) |
| 938 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT) |
| 939 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_RANGE 16:16 |
| 940 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_WOFFSET 0x0 |
| 941 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT _MK_MASK
_CONST(0x0) |
| 942 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 943 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 944 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 945 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DISABLE _MK_ENUM
_CONST(0) |
| 946 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_ENABLE _MK_ENUM
_CONST(1) |
| 947 |
| 948 //override dpd idle state with row 4 output |
| 949 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT _MK_SHIF
T_CONST(17) |
| 950 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT) |
| 951 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_RANGE 17:17 |
| 952 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_WOFFSET 0x0 |
| 953 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT _MK_MASK
_CONST(0x0) |
| 954 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 955 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 956 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 957 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DISABLE _MK_ENUM
_CONST(0) |
| 958 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_ENABLE _MK_ENUM
_CONST(1) |
| 959 |
| 960 //override dpd idle state with row 5 output |
| 961 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT _MK_SHIF
T_CONST(18) |
| 962 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT) |
| 963 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_RANGE 18:18 |
| 964 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_WOFFSET 0x0 |
| 965 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT _MK_MASK
_CONST(0x0) |
| 966 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 967 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 968 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 969 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DISABLE _MK_ENUM
_CONST(0) |
| 970 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_ENABLE _MK_ENUM
_CONST(1) |
| 971 |
| 972 //override dpd idle state with row 6 output |
| 973 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT _MK_SHIF
T_CONST(19) |
| 974 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT) |
| 975 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_RANGE 19:19 |
| 976 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_WOFFSET 0x0 |
| 977 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT _MK_MASK
_CONST(0x0) |
| 978 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 979 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 980 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 981 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DISABLE _MK_ENUM
_CONST(0) |
| 982 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_ENABLE _MK_ENUM
_CONST(1) |
| 983 |
| 984 //override dpd idle state with blink ouptut |
| 985 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT _MK_SHIFT_CONST(
20) |
| 986 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT) |
| 987 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_RANGE 20:20 |
| 988 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_WOFFSET 0x0 |
| 989 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT _MK_MASK
_CONST(0x0) |
| 990 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 991 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 992 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 993 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DISABLE _MK_ENUM
_CONST(0) |
| 994 #define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_ENABLE _MK_ENUM
_CONST(1) |
| 995 |
| 996 //override dpd idle state with column with sys_clk_request output |
| 997 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT _MK_SHIF
T_CONST(21) |
| 998 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT) |
| 999 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_RANGE 21:21 |
| 1000 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET 0x0 |
| 1001 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT _MK_MASK
_CONST(0x1) |
| 1002 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1003 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1004 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1005 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE _MK_ENUM
_CONST(0) |
| 1006 #define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE _MK_ENUM
_CONST(1) |
| 1007 |
| 1008 //override dpd idle state with row 7 output |
| 1009 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT _MK_SHIF
T_CONST(22) |
| 1010 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT) |
| 1011 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_RANGE 22:22 |
| 1012 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_WOFFSET 0x0 |
| 1013 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT _MK_MASK
_CONST(0x0) |
| 1014 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1015 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1016 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1017 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DISABLE _MK_ENUM
_CONST(0) |
| 1018 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_ENABLE _MK_ENUM
_CONST(1) |
| 1019 |
| 1020 //override dpd idle state with row 8 output |
| 1021 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT _MK_SHIF
T_CONST(23) |
| 1022 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT) |
| 1023 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_RANGE 23:23 |
| 1024 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_WOFFSET 0x0 |
| 1025 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT _MK_MASK
_CONST(0x0) |
| 1026 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1027 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1028 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1029 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DISABLE _MK_ENUM
_CONST(0) |
| 1030 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_ENABLE _MK_ENUM
_CONST(1) |
| 1031 |
| 1032 //override dpd idle state with row 9 output |
| 1033 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT _MK_SHIF
T_CONST(24) |
| 1034 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT) |
| 1035 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_RANGE 24:24 |
| 1036 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_WOFFSET 0x0 |
| 1037 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT _MK_MASK
_CONST(0x0) |
| 1038 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1039 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1040 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1041 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DISABLE _MK_ENUM
_CONST(0) |
| 1042 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_ENABLE _MK_ENUM
_CONST(1) |
| 1043 |
| 1044 //override dpd idle state with row 10 output |
| 1045 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT _MK_SHIF
T_CONST(25) |
| 1046 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT) |
| 1047 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_RANGE 25:25 |
| 1048 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_WOFFSET 0x0 |
| 1049 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT _MK_MASK
_CONST(0x0) |
| 1050 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1051 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 1052 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1053 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DISABLE _MK_ENUM
_CONST(0) |
| 1054 #define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_ENABLE _MK_ENUM
_CONST(1) |
| 1055 |
| 1056 |
| 1057 // Register APBDEV_PMC_DPD_SAMPLE_0 |
| 1058 #define APBDEV_PMC_DPD_SAMPLE_0 _MK_ADDR_CONST(0x20) |
| 1059 #define APBDEV_PMC_DPD_SAMPLE_0_SECURE 0x0 |
| 1060 #define APBDEV_PMC_DPD_SAMPLE_0_WORD_COUNT 0x1 |
| 1061 #define APBDEV_PMC_DPD_SAMPLE_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1062 #define APBDEV_PMC_DPD_SAMPLE_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 1063 #define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1064 #define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1065 #define APBDEV_PMC_DPD_SAMPLE_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 1066 #define APBDEV_PMC_DPD_SAMPLE_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 1067 // will set sampling of pads value |
| 1068 #define APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT _MK_SHIFT_CONST(
0) |
| 1069 #define APBDEV_PMC_DPD_SAMPLE_0_ON_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT) |
| 1070 #define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE 0:0 |
| 1071 #define APBDEV_PMC_DPD_SAMPLE_0_ON_WOFFSET 0x0 |
| 1072 #define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT _MK_MASK_CONST(0
x0) |
| 1073 #define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1074 #define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1075 #define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1076 #define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE _MK_ENUM_CONST(0
) |
| 1077 #define APBDEV_PMC_DPD_SAMPLE_0_ON_ENABLE _MK_ENUM_CONST(1
) |
| 1078 |
| 1079 |
| 1080 // Register APBDEV_PMC_DPD_ENABLE_0 |
| 1081 #define APBDEV_PMC_DPD_ENABLE_0 _MK_ADDR_CONST(0x24) |
| 1082 #define APBDEV_PMC_DPD_ENABLE_0_SECURE 0x0 |
| 1083 #define APBDEV_PMC_DPD_ENABLE_0_WORD_COUNT 0x1 |
| 1084 #define APBDEV_PMC_DPD_ENABLE_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1085 #define APBDEV_PMC_DPD_ENABLE_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 1086 #define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1087 #define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1088 #define APBDEV_PMC_DPD_ENABLE_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 1089 #define APBDEV_PMC_DPD_ENABLE_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 1090 // will set sampling of pads value |
| 1091 #define APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT _MK_SHIFT_CONST(
0) |
| 1092 #define APBDEV_PMC_DPD_ENABLE_0_ON_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT) |
| 1093 #define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE 0:0 |
| 1094 #define APBDEV_PMC_DPD_ENABLE_0_ON_WOFFSET 0x0 |
| 1095 #define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT _MK_MASK_CONST(0
x0) |
| 1096 #define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1097 #define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1098 #define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1099 #define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE _MK_ENUM_CONST(0
) |
| 1100 #define APBDEV_PMC_DPD_ENABLE_0_ON_ENABLE _MK_ENUM_CONST(1
) |
| 1101 |
| 1102 |
| 1103 // Register APBDEV_PMC_PWRGATE_TIMER_OFF_0 |
| 1104 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0 _MK_ADDR_CONST(0x28) |
| 1105 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SECURE 0x0 |
| 1106 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WORD_COUNT 0x1 |
| 1107 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_VAL _MK_MASK
_CONST(0xeca97531) |
| 1108 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 1109 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1110 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1111 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 1112 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 1113 // timer value for rail 0 |
| 1114 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT _MK_SHIF
T_CONST(0) |
| 1115 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT) |
| 1116 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_RANGE 3:0 |
| 1117 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_WOFFSET 0x0 |
| 1118 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT _MK_MASK
_CONST(0x1) |
| 1119 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1120 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1121 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1122 |
| 1123 // timer value for rail 1 |
| 1124 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT _MK_SHIF
T_CONST(4) |
| 1125 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT) |
| 1126 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_RANGE 7:4 |
| 1127 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_WOFFSET 0x0 |
| 1128 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT _MK_MASK
_CONST(0x3) |
| 1129 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1130 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1131 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1132 |
| 1133 // timer value for rail 2 |
| 1134 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT _MK_SHIF
T_CONST(8) |
| 1135 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT) |
| 1136 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_RANGE 11:8 |
| 1137 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_WOFFSET 0x0 |
| 1138 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT _MK_MASK
_CONST(0x5) |
| 1139 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1140 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1141 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1142 |
| 1143 // timer value for rail 3 |
| 1144 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT _MK_SHIF
T_CONST(12) |
| 1145 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT) |
| 1146 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_RANGE 15:12 |
| 1147 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_WOFFSET 0x0 |
| 1148 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT _MK_MASK
_CONST(0x7) |
| 1149 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1150 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1151 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1152 |
| 1153 // timer value for rail 4 |
| 1154 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT _MK_SHIF
T_CONST(16) |
| 1155 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT) |
| 1156 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_RANGE 19:16 |
| 1157 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_WOFFSET 0x0 |
| 1158 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT _MK_MASK
_CONST(0x9) |
| 1159 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1160 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1161 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1162 |
| 1163 // timer value for rail 5 |
| 1164 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT _MK_SHIF
T_CONST(20) |
| 1165 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT) |
| 1166 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_RANGE 23:20 |
| 1167 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_WOFFSET 0x0 |
| 1168 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT _MK_MASK
_CONST(0xa) |
| 1169 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1170 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1171 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1172 |
| 1173 // timer value for rail 6 |
| 1174 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT _MK_SHIF
T_CONST(24) |
| 1175 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT) |
| 1176 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_RANGE 27:24 |
| 1177 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_WOFFSET 0x0 |
| 1178 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT _MK_MASK
_CONST(0xc) |
| 1179 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1180 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1181 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1182 |
| 1183 // timer value for rail 7 |
| 1184 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT _MK_SHIF
T_CONST(28) |
| 1185 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT) |
| 1186 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_RANGE 31:28 |
| 1187 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_WOFFSET 0x0 |
| 1188 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT _MK_MASK
_CONST(0xe) |
| 1189 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1190 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1191 #define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1192 |
| 1193 |
| 1194 // Register APBDEV_PMC_PWRGATE_TIMER_ON_0 |
| 1195 #define APBDEV_PMC_PWRGATE_TIMER_ON_0 _MK_ADDR_CONST(0x2c) |
| 1196 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_SECURE 0x0 |
| 1197 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_WORD_COUNT 0x1 |
| 1198 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_VAL _MK_MASK
_CONST(0xeca97531) |
| 1199 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 1200 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1201 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1202 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 1203 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 1204 // timer value for rail 0 |
| 1205 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT _MK_SHIF
T_CONST(0) |
| 1206 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT) |
| 1207 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_RANGE 3:0 |
| 1208 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_WOFFSET 0x0 |
| 1209 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT _MK_MASK
_CONST(0x1) |
| 1210 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1211 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1212 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1213 |
| 1214 // timer value for rail 1 |
| 1215 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT _MK_SHIF
T_CONST(4) |
| 1216 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT) |
| 1217 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_RANGE 7:4 |
| 1218 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_WOFFSET 0x0 |
| 1219 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT _MK_MASK
_CONST(0x3) |
| 1220 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1221 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1222 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1223 |
| 1224 // timer value for rail 2 |
| 1225 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT _MK_SHIF
T_CONST(8) |
| 1226 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT) |
| 1227 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_RANGE 11:8 |
| 1228 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_WOFFSET 0x0 |
| 1229 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT _MK_MASK
_CONST(0x5) |
| 1230 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1231 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1232 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1233 |
| 1234 // timer value for rail 3 |
| 1235 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT _MK_SHIF
T_CONST(12) |
| 1236 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT) |
| 1237 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_RANGE 15:12 |
| 1238 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_WOFFSET 0x0 |
| 1239 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT _MK_MASK
_CONST(0x7) |
| 1240 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1241 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1242 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1243 |
| 1244 // timer value for rail 4 |
| 1245 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT _MK_SHIF
T_CONST(16) |
| 1246 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT) |
| 1247 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_RANGE 19:16 |
| 1248 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_WOFFSET 0x0 |
| 1249 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT _MK_MASK
_CONST(0x9) |
| 1250 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1251 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1252 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1253 |
| 1254 // timer value for rail 5 |
| 1255 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT _MK_SHIF
T_CONST(20) |
| 1256 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT) |
| 1257 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_RANGE 23:20 |
| 1258 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_WOFFSET 0x0 |
| 1259 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT _MK_MASK
_CONST(0xa) |
| 1260 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1261 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1262 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1263 |
| 1264 // timer value for rail 6 |
| 1265 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT _MK_SHIF
T_CONST(24) |
| 1266 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT) |
| 1267 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_RANGE 27:24 |
| 1268 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_WOFFSET 0x0 |
| 1269 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT _MK_MASK
_CONST(0xc) |
| 1270 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1271 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1272 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1273 |
| 1274 // timer value for rail 7 |
| 1275 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT _MK_SHIF
T_CONST(28) |
| 1276 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT) |
| 1277 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_RANGE 31:28 |
| 1278 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_WOFFSET 0x0 |
| 1279 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT _MK_MASK
_CONST(0xe) |
| 1280 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT_MASK
_MK_MASK_CONST(0xf) |
| 1281 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1282 #define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1283 |
| 1284 |
| 1285 // Register APBDEV_PMC_PWRGATE_TOGGLE_0 |
| 1286 #define APBDEV_PMC_PWRGATE_TOGGLE_0 _MK_ADDR_CONST(0x30) |
| 1287 #define APBDEV_PMC_PWRGATE_TOGGLE_0_SECURE 0x0 |
| 1288 #define APBDEV_PMC_PWRGATE_TOGGLE_0_WORD_COUNT 0x1 |
| 1289 #define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1290 #define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_MASK _MK_MASK_CONST(0
x107) |
| 1291 #define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1292 #define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1293 #define APBDEV_PMC_PWRGATE_TOGGLE_0_READ_MASK _MK_MASK_CONST(0
x107) |
| 1294 #define APBDEV_PMC_PWRGATE_TOGGLE_0_WRITE_MASK _MK_MASK_CONST(0
x107) |
| 1295 //id of partition to be toggled |
| 1296 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT _MK_SHIF
T_CONST(0) |
| 1297 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_FIELD (_MK_MAS
K_CONST(0x7) << APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT) |
| 1298 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE 2:0 |
| 1299 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_WOFFSET 0x0 |
| 1300 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT _MK_MASK
_CONST(0x0) |
| 1301 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT_MASK _MK_MASK
_CONST(0x7) |
| 1302 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1303 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1304 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP _MK_ENUM_CONST(0
) |
| 1305 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_TD _MK_ENUM_CONST(1
) |
| 1306 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VE _MK_ENUM_CONST(2
) |
| 1307 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VDE _MK_ENUM_CONST(4
) |
| 1308 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_PCX _MK_ENUM_CONST(3
) |
| 1309 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_L2C _MK_ENUM_CONST(5
) |
| 1310 #define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_MPE _MK_ENUM_CONST(6
) |
| 1311 |
| 1312 //start power down/up |
| 1313 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT _MK_SHIFT_CONST(
8) |
| 1314 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT) |
| 1315 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE 8:8 |
| 1316 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_WOFFSET 0x0 |
| 1317 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT _MK_MASK
_CONST(0x0) |
| 1318 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1319 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1320 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1321 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DISABLE _MK_ENUM
_CONST(0) |
| 1322 #define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE _MK_ENUM
_CONST(1) |
| 1323 |
| 1324 |
| 1325 // Register APBDEV_PMC_REMOVE_CLAMPING_CMD_0 |
| 1326 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0 _MK_ADDR_CONST(0
x34) |
| 1327 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SECURE 0x0 |
| 1328 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WORD_COUNT 0x1 |
| 1329 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_VAL _MK_MASK
_CONST(0x0) |
| 1330 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_MASK _MK_MASK
_CONST(0x7f) |
| 1331 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_VAL
_MK_MASK_CONST(0x0) |
| 1332 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1333 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_READ_MASK _MK_MASK
_CONST(0x7f) |
| 1334 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WRITE_MASK _MK_MASK
_CONST(0x7f) |
| 1335 //remove clamping to CPU |
| 1336 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT _MK_SHIF
T_CONST(0) |
| 1337 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT) |
| 1338 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE 0:0 |
| 1339 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_WOFFSET 0x0 |
| 1340 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT _MK_MASK
_CONST(0x0) |
| 1341 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1342 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1343 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1344 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DISABLE _MK_ENUM
_CONST(0) |
| 1345 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE _MK_ENUM
_CONST(1) |
| 1346 |
| 1347 //remove clamping to TD |
| 1348 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT _MK_SHIF
T_CONST(1) |
| 1349 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT) |
| 1350 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_RANGE 1:1 |
| 1351 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_WOFFSET 0x0 |
| 1352 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT _MK_MASK
_CONST(0x0) |
| 1353 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1354 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1355 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1356 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DISABLE _MK_ENUM
_CONST(0) |
| 1357 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_ENABLE _MK_ENUM
_CONST(1) |
| 1358 |
| 1359 //remove clamping to VE |
| 1360 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT _MK_SHIF
T_CONST(2) |
| 1361 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT) |
| 1362 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_RANGE 2:2 |
| 1363 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_WOFFSET 0x0 |
| 1364 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT _MK_MASK
_CONST(0x0) |
| 1365 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1366 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1367 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1368 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DISABLE _MK_ENUM
_CONST(0) |
| 1369 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_ENABLE _MK_ENUM
_CONST(1) |
| 1370 |
| 1371 //remove clamping to VDE |
| 1372 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT _MK_SHIF
T_CONST(3) |
| 1373 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT) |
| 1374 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_RANGE 3:3 |
| 1375 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_WOFFSET 0x0 |
| 1376 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT _MK_MASK
_CONST(0x0) |
| 1377 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1378 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1379 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1380 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DISABLE _MK_ENUM
_CONST(0) |
| 1381 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_ENABLE _MK_ENUM
_CONST(1) |
| 1382 |
| 1383 //remove clamping to PCX |
| 1384 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT _MK_SHIF
T_CONST(4) |
| 1385 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT) |
| 1386 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_RANGE 4:4 |
| 1387 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_WOFFSET 0x0 |
| 1388 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT _MK_MASK
_CONST(0x0) |
| 1389 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1390 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1391 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1392 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DISABLE _MK_ENUM
_CONST(0) |
| 1393 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_ENABLE _MK_ENUM
_CONST(1) |
| 1394 |
| 1395 //remove clamping to L2_CACHE |
| 1396 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT _MK_SHIF
T_CONST(5) |
| 1397 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT) |
| 1398 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_RANGE 5:5 |
| 1399 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_WOFFSET 0x0 |
| 1400 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT _MK_MASK
_CONST(0x0) |
| 1401 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1402 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1403 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1404 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DISABLE _MK_ENUM
_CONST(0) |
| 1405 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_ENABLE _MK_ENUM
_CONST(1) |
| 1406 |
| 1407 //remove clamping to MPE_CACHE |
| 1408 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT _MK_SHIF
T_CONST(6) |
| 1409 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT) |
| 1410 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_RANGE 6:6 |
| 1411 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_WOFFSET 0x0 |
| 1412 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT _MK_MASK
_CONST(0x0) |
| 1413 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1414 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1415 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1416 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DISABLE _MK_ENUM
_CONST(0) |
| 1417 #define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_ENABLE _MK_ENUM
_CONST(1) |
| 1418 |
| 1419 |
| 1420 // Register APBDEV_PMC_PWRGATE_STATUS_0 |
| 1421 #define APBDEV_PMC_PWRGATE_STATUS_0 _MK_ADDR_CONST(0x38) |
| 1422 #define APBDEV_PMC_PWRGATE_STATUS_0_SECURE 0x0 |
| 1423 #define APBDEV_PMC_PWRGATE_STATUS_0_WORD_COUNT 0x1 |
| 1424 #define APBDEV_PMC_PWRGATE_STATUS_0_RESET_VAL _MK_MASK_CONST(0
x7f) |
| 1425 #define APBDEV_PMC_PWRGATE_STATUS_0_RESET_MASK _MK_MASK_CONST(0
x7f) |
| 1426 #define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1427 #define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1428 #define APBDEV_PMC_PWRGATE_STATUS_0_READ_MASK _MK_MASK_CONST(0
x7f) |
| 1429 #define APBDEV_PMC_PWRGATE_STATUS_0_WRITE_MASK _MK_MASK_CONST(0
x0) |
| 1430 //status of CPU partition |
| 1431 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT _MK_SHIFT_CONST(
0) |
| 1432 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT) |
| 1433 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE 0:0 |
| 1434 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_WOFFSET 0x0 |
| 1435 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT _MK_MASK_CONST(0
x1) |
| 1436 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1437 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1438 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1439 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_OFF _MK_ENUM_CONST(0
) |
| 1440 #define APBDEV_PMC_PWRGATE_STATUS_0_CPU_ON _MK_ENUM_CONST(1
) |
| 1441 |
| 1442 //status of TD Partition |
| 1443 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT _MK_SHIFT_CONST(
1) |
| 1444 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT) |
| 1445 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_RANGE 1:1 |
| 1446 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_WOFFSET 0x0 |
| 1447 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT _MK_MASK_CONST(0
x1) |
| 1448 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1449 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1450 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1451 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_OFF _MK_ENUM_CONST(0
) |
| 1452 #define APBDEV_PMC_PWRGATE_STATUS_0_TD_ON _MK_ENUM_CONST(1
) |
| 1453 |
| 1454 //status of VE partition |
| 1455 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT _MK_SHIFT_CONST(
2) |
| 1456 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT) |
| 1457 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_RANGE 2:2 |
| 1458 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_WOFFSET 0x0 |
| 1459 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT _MK_MASK_CONST(0
x1) |
| 1460 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1461 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1462 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1463 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_OFF _MK_ENUM_CONST(0
) |
| 1464 #define APBDEV_PMC_PWRGATE_STATUS_0_VE_ON _MK_ENUM_CONST(1
) |
| 1465 |
| 1466 //status of VDE partition |
| 1467 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT _MK_SHIFT_CONST(
4) |
| 1468 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT) |
| 1469 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_RANGE 4:4 |
| 1470 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_WOFFSET 0x0 |
| 1471 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT _MK_MASK_CONST(0
x1) |
| 1472 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1473 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1474 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1475 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_OFF _MK_ENUM_CONST(0
) |
| 1476 #define APBDEV_PMC_PWRGATE_STATUS_0_VDE_ON _MK_ENUM_CONST(1
) |
| 1477 |
| 1478 //status of PCX partition |
| 1479 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT _MK_SHIFT_CONST(
3) |
| 1480 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT) |
| 1481 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_RANGE 3:3 |
| 1482 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_WOFFSET 0x0 |
| 1483 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT _MK_MASK_CONST(0
x1) |
| 1484 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1485 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1486 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1487 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_OFF _MK_ENUM_CONST(0
) |
| 1488 #define APBDEV_PMC_PWRGATE_STATUS_0_PCX_ON _MK_ENUM_CONST(1
) |
| 1489 |
| 1490 //status of L2C partition |
| 1491 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT _MK_SHIFT_CONST(
5) |
| 1492 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT) |
| 1493 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_RANGE 5:5 |
| 1494 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_WOFFSET 0x0 |
| 1495 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT _MK_MASK_CONST(0
x1) |
| 1496 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1497 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1498 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1499 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_OFF _MK_ENUM_CONST(0
) |
| 1500 #define APBDEV_PMC_PWRGATE_STATUS_0_L2C_ON _MK_ENUM_CONST(1
) |
| 1501 |
| 1502 //status of MPE partition |
| 1503 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT _MK_SHIFT_CONST(
6) |
| 1504 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT) |
| 1505 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_RANGE 6:6 |
| 1506 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_WOFFSET 0x0 |
| 1507 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT _MK_MASK_CONST(0
x1) |
| 1508 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1509 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1510 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1511 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_OFF _MK_ENUM_CONST(0
) |
| 1512 #define APBDEV_PMC_PWRGATE_STATUS_0_MPE_ON _MK_ENUM_CONST(1
) |
| 1513 |
| 1514 |
| 1515 // Register APBDEV_PMC_PWRGOOD_TIMER_0 |
| 1516 #define APBDEV_PMC_PWRGOOD_TIMER_0 _MK_ADDR_CONST(0x3c) |
| 1517 #define APBDEV_PMC_PWRGOOD_TIMER_0_SECURE 0x0 |
| 1518 #define APBDEV_PMC_PWRGOOD_TIMER_0_WORD_COUNT 0x1 |
| 1519 #define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_VAL _MK_MASK_CONST(0
x7f) |
| 1520 #define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_MASK _MK_MASK_CONST(0
xffff) |
| 1521 #define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1522 #define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1523 #define APBDEV_PMC_PWRGOOD_TIMER_0_READ_MASK _MK_MASK_CONST(0
xffff) |
| 1524 #define APBDEV_PMC_PWRGOOD_TIMER_0_WRITE_MASK _MK_MASK_CONST(0
xffff) |
| 1525 // pmu timer * 32 |
| 1526 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT _MK_SHIF
T_CONST(0) |
| 1527 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_FIELD (_MK_MAS
K_CONST(0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT) |
| 1528 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_RANGE 7:0 |
| 1529 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_WOFFSET 0x0 |
| 1530 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT _MK_MASK
_CONST(0x7f) |
| 1531 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 1532 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1533 #define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1534 |
| 1535 // xtal timer * 32 |
| 1536 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT _MK_SHIFT_CONST(
8) |
| 1537 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_FIELD (_MK_MASK_CONST(
0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT) |
| 1538 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_RANGE 15:8 |
| 1539 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_WOFFSET 0x0 |
| 1540 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT _MK_MASK_CONST(0
x0) |
| 1541 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT_MASK _MK_MASK
_CONST(0xff) |
| 1542 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1543 #define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1544 |
| 1545 |
| 1546 // Register APBDEV_PMC_BLINK_TIMER_0 |
| 1547 #define APBDEV_PMC_BLINK_TIMER_0 _MK_ADDR_CONST(0x40) |
| 1548 #define APBDEV_PMC_BLINK_TIMER_0_SECURE 0x0 |
| 1549 #define APBDEV_PMC_BLINK_TIMER_0_WORD_COUNT 0x1 |
| 1550 #define APBDEV_PMC_BLINK_TIMER_0_RESET_VAL _MK_MASK_CONST(0
xffffffff) |
| 1551 #define APBDEV_PMC_BLINK_TIMER_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1552 #define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1553 #define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1554 #define APBDEV_PMC_BLINK_TIMER_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1555 #define APBDEV_PMC_BLINK_TIMER_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1556 // time on |
| 1557 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT _MK_SHIFT_CONST(
0) |
| 1558 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_FIELD (_MK_MASK_CONST(
0x7fff) << APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT) |
| 1559 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_RANGE 14:0 |
| 1560 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_WOFFSET 0x0 |
| 1561 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT _MK_MASK
_CONST(0xffff) |
| 1562 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK _MK_MASK
_CONST(0x7fff) |
| 1563 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1564 #define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1565 |
| 1566 // if 0 32khz clock |
| 1567 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT _MK_SHIF
T_CONST(15) |
| 1568 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT) |
| 1569 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_RANGE 15:15 |
| 1570 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_WOFFSET 0x0 |
| 1571 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT _MK_MASK
_CONST(0x1) |
| 1572 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 1573 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1574 #define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1575 |
| 1576 // time off |
| 1577 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT _MK_SHIFT_CONST(
16) |
| 1578 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT) |
| 1579 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_RANGE 31:16 |
| 1580 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_WOFFSET 0x0 |
| 1581 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT _MK_MASK
_CONST(0xffff) |
| 1582 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 1583 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1584 #define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1585 |
| 1586 |
| 1587 // Register APBDEV_PMC_NO_IOPOWER_0 |
| 1588 #define APBDEV_PMC_NO_IOPOWER_0 _MK_ADDR_CONST(0x44) |
| 1589 #define APBDEV_PMC_NO_IOPOWER_0_SECURE 0x0 |
| 1590 #define APBDEV_PMC_NO_IOPOWER_0_WORD_COUNT 0x1 |
| 1591 #define APBDEV_PMC_NO_IOPOWER_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1592 #define APBDEV_PMC_NO_IOPOWER_0_RESET_MASK _MK_MASK_CONST(0
x3ff) |
| 1593 #define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1594 #define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1595 #define APBDEV_PMC_NO_IOPOWER_0_READ_MASK _MK_MASK_CONST(0
x3ff) |
| 1596 #define APBDEV_PMC_NO_IOPOWER_0_WRITE_MASK _MK_MASK_CONST(0
x3ff) |
| 1597 //rail ao IOs |
| 1598 #define APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT _MK_SHIFT_CONST(
0) |
| 1599 #define APBDEV_PMC_NO_IOPOWER_0_SYS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT) |
| 1600 #define APBDEV_PMC_NO_IOPOWER_0_SYS_RANGE 0:0 |
| 1601 #define APBDEV_PMC_NO_IOPOWER_0_SYS_WOFFSET 0x0 |
| 1602 #define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT _MK_MASK_CONST(0
x0) |
| 1603 #define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1604 #define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1605 #define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1606 #define APBDEV_PMC_NO_IOPOWER_0_SYS_DISABLE _MK_ENUM_CONST(0
) |
| 1607 #define APBDEV_PMC_NO_IOPOWER_0_SYS_ENABLE _MK_ENUM_CONST(1
) |
| 1608 |
| 1609 //rail at3 IOs |
| 1610 #define APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT _MK_SHIFT_CONST(
1) |
| 1611 #define APBDEV_PMC_NO_IOPOWER_0_NAND_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT) |
| 1612 #define APBDEV_PMC_NO_IOPOWER_0_NAND_RANGE 1:1 |
| 1613 #define APBDEV_PMC_NO_IOPOWER_0_NAND_WOFFSET 0x0 |
| 1614 #define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT _MK_MASK_CONST(0
x0) |
| 1615 #define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1616 #define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1617 #define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1618 #define APBDEV_PMC_NO_IOPOWER_0_NAND_DISABLE _MK_ENUM_CONST(0
) |
| 1619 #define APBDEV_PMC_NO_IOPOWER_0_NAND_ENABLE _MK_ENUM_CONST(1
) |
| 1620 |
| 1621 //rail dbg IOs |
| 1622 #define APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT _MK_SHIFT_CONST(
2) |
| 1623 #define APBDEV_PMC_NO_IOPOWER_0_UART_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT) |
| 1624 #define APBDEV_PMC_NO_IOPOWER_0_UART_RANGE 2:2 |
| 1625 #define APBDEV_PMC_NO_IOPOWER_0_UART_WOFFSET 0x0 |
| 1626 #define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT _MK_MASK_CONST(0
x0) |
| 1627 #define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1628 #define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1629 #define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1630 #define APBDEV_PMC_NO_IOPOWER_0_UART_DISABLE _MK_ENUM_CONST(0
) |
| 1631 #define APBDEV_PMC_NO_IOPOWER_0_UART_ENABLE _MK_ENUM_CONST(1
) |
| 1632 |
| 1633 //rail dlcd IOs |
| 1634 #define APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT _MK_SHIFT_CONST(
3) |
| 1635 #define APBDEV_PMC_NO_IOPOWER_0_BB_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT) |
| 1636 #define APBDEV_PMC_NO_IOPOWER_0_BB_RANGE 3:3 |
| 1637 #define APBDEV_PMC_NO_IOPOWER_0_BB_WOFFSET 0x0 |
| 1638 #define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT _MK_MASK_CONST(0
x0) |
| 1639 #define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1640 #define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1641 #define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1642 #define APBDEV_PMC_NO_IOPOWER_0_BB_DISABLE _MK_ENUM_CONST(0
) |
| 1643 #define APBDEV_PMC_NO_IOPOWER_0_BB_ENABLE _MK_ENUM_CONST(1
) |
| 1644 |
| 1645 //rail dvi IOs |
| 1646 #define APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT _MK_SHIFT_CONST(
4) |
| 1647 #define APBDEV_PMC_NO_IOPOWER_0_VI_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT) |
| 1648 #define APBDEV_PMC_NO_IOPOWER_0_VI_RANGE 4:4 |
| 1649 #define APBDEV_PMC_NO_IOPOWER_0_VI_WOFFSET 0x0 |
| 1650 #define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT _MK_MASK_CONST(0
x0) |
| 1651 #define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1652 #define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1653 #define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1654 #define APBDEV_PMC_NO_IOPOWER_0_VI_DISABLE _MK_ENUM_CONST(0
) |
| 1655 #define APBDEV_PMC_NO_IOPOWER_0_VI_ENABLE _MK_ENUM_CONST(1
) |
| 1656 |
| 1657 //rail i2s IOs |
| 1658 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT _MK_SHIFT_CONST(
5) |
| 1659 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT) |
| 1660 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_RANGE 5:5 |
| 1661 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_WOFFSET 0x0 |
| 1662 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT _MK_MASK_CONST(0
x0) |
| 1663 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1664 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1665 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1666 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DISABLE _MK_ENUM_CONST(0
) |
| 1667 #define APBDEV_PMC_NO_IOPOWER_0_AUDIO_ENABLE _MK_ENUM_CONST(1
) |
| 1668 |
| 1669 //rail lcd IOs |
| 1670 #define APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT _MK_SHIFT_CONST(
6) |
| 1671 #define APBDEV_PMC_NO_IOPOWER_0_LCD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT) |
| 1672 #define APBDEV_PMC_NO_IOPOWER_0_LCD_RANGE 6:6 |
| 1673 #define APBDEV_PMC_NO_IOPOWER_0_LCD_WOFFSET 0x0 |
| 1674 #define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT _MK_MASK_CONST(0
x0) |
| 1675 #define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1676 #define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1677 #define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1678 #define APBDEV_PMC_NO_IOPOWER_0_LCD_DISABLE _MK_ENUM_CONST(0
) |
| 1679 #define APBDEV_PMC_NO_IOPOWER_0_LCD_ENABLE _MK_ENUM_CONST(1
) |
| 1680 |
| 1681 //rail mem IOs |
| 1682 #define APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT _MK_SHIFT_CONST(
7) |
| 1683 #define APBDEV_PMC_NO_IOPOWER_0_MEM_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT) |
| 1684 #define APBDEV_PMC_NO_IOPOWER_0_MEM_RANGE 7:7 |
| 1685 #define APBDEV_PMC_NO_IOPOWER_0_MEM_WOFFSET 0x0 |
| 1686 #define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT _MK_MASK_CONST(0
x0) |
| 1687 #define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1688 #define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1689 #define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1690 #define APBDEV_PMC_NO_IOPOWER_0_MEM_DISABLE _MK_ENUM_CONST(0
) |
| 1691 #define APBDEV_PMC_NO_IOPOWER_0_MEM_ENABLE _MK_ENUM_CONST(1
) |
| 1692 |
| 1693 //rail sd IOs |
| 1694 #define APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT _MK_SHIFT_CONST(
8) |
| 1695 #define APBDEV_PMC_NO_IOPOWER_0_SD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT) |
| 1696 #define APBDEV_PMC_NO_IOPOWER_0_SD_RANGE 8:8 |
| 1697 #define APBDEV_PMC_NO_IOPOWER_0_SD_WOFFSET 0x0 |
| 1698 #define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT _MK_MASK_CONST(0
x0) |
| 1699 #define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1700 #define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1701 #define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1702 #define APBDEV_PMC_NO_IOPOWER_0_SD_DISABLE _MK_ENUM_CONST(0
) |
| 1703 #define APBDEV_PMC_NO_IOPOWER_0_SD_ENABLE _MK_ENUM_CONST(1
) |
| 1704 |
| 1705 //rail mipi IOs |
| 1706 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT _MK_SHIFT_CONST(
9) |
| 1707 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT) |
| 1708 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_RANGE 9:9 |
| 1709 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_WOFFSET 0x0 |
| 1710 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT _MK_MASK_CONST(0
x0) |
| 1711 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1712 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1713 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1714 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_DISABLE _MK_ENUM_CONST(0
) |
| 1715 #define APBDEV_PMC_NO_IOPOWER_0_MIPI_ENABLE _MK_ENUM_CONST(1
) |
| 1716 |
| 1717 |
| 1718 // Register APBDEV_PMC_PWR_DET_0 |
| 1719 #define APBDEV_PMC_PWR_DET_0 _MK_ADDR_CONST(0x48) |
| 1720 #define APBDEV_PMC_PWR_DET_0_SECURE 0x0 |
| 1721 #define APBDEV_PMC_PWR_DET_0_WORD_COUNT 0x1 |
| 1722 #define APBDEV_PMC_PWR_DET_0_RESET_VAL _MK_MASK_CONST(0x1ff) |
| 1723 #define APBDEV_PMC_PWR_DET_0_RESET_MASK _MK_MASK_CONST(0
x1ff) |
| 1724 #define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1725 #define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1726 #define APBDEV_PMC_PWR_DET_0_READ_MASK _MK_MASK_CONST(0x1ff) |
| 1727 #define APBDEV_PMC_PWR_DET_0_WRITE_MASK _MK_MASK_CONST(0
x1ff) |
| 1728 //rail ao IOs |
| 1729 #define APBDEV_PMC_PWR_DET_0_SYS_SHIFT _MK_SHIFT_CONST(0) |
| 1730 #define APBDEV_PMC_PWR_DET_0_SYS_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_SYS_SHIFT) |
| 1731 #define APBDEV_PMC_PWR_DET_0_SYS_RANGE 0:0 |
| 1732 #define APBDEV_PMC_PWR_DET_0_SYS_WOFFSET 0x0 |
| 1733 #define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT _MK_MASK_CONST(0
x1) |
| 1734 #define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1735 #define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1736 #define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1737 #define APBDEV_PMC_PWR_DET_0_SYS_ENABLE _MK_ENUM_CONST(0) |
| 1738 #define APBDEV_PMC_PWR_DET_0_SYS_DISABLE _MK_ENUM_CONST(1
) |
| 1739 |
| 1740 //rail at3 IOs |
| 1741 #define APBDEV_PMC_PWR_DET_0_NAND_SHIFT _MK_SHIFT_CONST(1) |
| 1742 #define APBDEV_PMC_PWR_DET_0_NAND_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_NAND_SHIFT) |
| 1743 #define APBDEV_PMC_PWR_DET_0_NAND_RANGE 1:1 |
| 1744 #define APBDEV_PMC_PWR_DET_0_NAND_WOFFSET 0x0 |
| 1745 #define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT _MK_MASK_CONST(0
x1) |
| 1746 #define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1747 #define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1748 #define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1749 #define APBDEV_PMC_PWR_DET_0_NAND_ENABLE _MK_ENUM_CONST(0
) |
| 1750 #define APBDEV_PMC_PWR_DET_0_NAND_DISABLE _MK_ENUM_CONST(1
) |
| 1751 |
| 1752 //rail dbg IOs |
| 1753 #define APBDEV_PMC_PWR_DET_0_UART_SHIFT _MK_SHIFT_CONST(2) |
| 1754 #define APBDEV_PMC_PWR_DET_0_UART_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_UART_SHIFT) |
| 1755 #define APBDEV_PMC_PWR_DET_0_UART_RANGE 2:2 |
| 1756 #define APBDEV_PMC_PWR_DET_0_UART_WOFFSET 0x0 |
| 1757 #define APBDEV_PMC_PWR_DET_0_UART_DEFAULT _MK_MASK_CONST(0
x1) |
| 1758 #define APBDEV_PMC_PWR_DET_0_UART_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1759 #define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1760 #define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1761 #define APBDEV_PMC_PWR_DET_0_UART_ENABLE _MK_ENUM_CONST(0
) |
| 1762 #define APBDEV_PMC_PWR_DET_0_UART_DISABLE _MK_ENUM_CONST(1
) |
| 1763 |
| 1764 //rail dlcd IOs |
| 1765 #define APBDEV_PMC_PWR_DET_0_BB_SHIFT _MK_SHIFT_CONST(3) |
| 1766 #define APBDEV_PMC_PWR_DET_0_BB_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_BB_SHIFT) |
| 1767 #define APBDEV_PMC_PWR_DET_0_BB_RANGE 3:3 |
| 1768 #define APBDEV_PMC_PWR_DET_0_BB_WOFFSET 0x0 |
| 1769 #define APBDEV_PMC_PWR_DET_0_BB_DEFAULT _MK_MASK_CONST(0x1) |
| 1770 #define APBDEV_PMC_PWR_DET_0_BB_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1771 #define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1772 #define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1773 #define APBDEV_PMC_PWR_DET_0_BB_ENABLE _MK_ENUM_CONST(0) |
| 1774 #define APBDEV_PMC_PWR_DET_0_BB_DISABLE _MK_ENUM_CONST(1) |
| 1775 |
| 1776 //rail dvi IOs |
| 1777 #define APBDEV_PMC_PWR_DET_0_VI_SHIFT _MK_SHIFT_CONST(4) |
| 1778 #define APBDEV_PMC_PWR_DET_0_VI_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_VI_SHIFT) |
| 1779 #define APBDEV_PMC_PWR_DET_0_VI_RANGE 4:4 |
| 1780 #define APBDEV_PMC_PWR_DET_0_VI_WOFFSET 0x0 |
| 1781 #define APBDEV_PMC_PWR_DET_0_VI_DEFAULT _MK_MASK_CONST(0x1) |
| 1782 #define APBDEV_PMC_PWR_DET_0_VI_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1783 #define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1784 #define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1785 #define APBDEV_PMC_PWR_DET_0_VI_ENABLE _MK_ENUM_CONST(0) |
| 1786 #define APBDEV_PMC_PWR_DET_0_VI_DISABLE _MK_ENUM_CONST(1) |
| 1787 |
| 1788 //rail i2s IOs |
| 1789 #define APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT _MK_SHIFT_CONST(
5) |
| 1790 #define APBDEV_PMC_PWR_DET_0_AUDIO_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT) |
| 1791 #define APBDEV_PMC_PWR_DET_0_AUDIO_RANGE 5:5 |
| 1792 #define APBDEV_PMC_PWR_DET_0_AUDIO_WOFFSET 0x0 |
| 1793 #define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT _MK_MASK_CONST(0
x1) |
| 1794 #define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1795 #define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1796 #define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1797 #define APBDEV_PMC_PWR_DET_0_AUDIO_ENABLE _MK_ENUM_CONST(0
) |
| 1798 #define APBDEV_PMC_PWR_DET_0_AUDIO_DISABLE _MK_ENUM_CONST(1
) |
| 1799 |
| 1800 //rail lcd IOs |
| 1801 #define APBDEV_PMC_PWR_DET_0_LCD_SHIFT _MK_SHIFT_CONST(6) |
| 1802 #define APBDEV_PMC_PWR_DET_0_LCD_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_LCD_SHIFT) |
| 1803 #define APBDEV_PMC_PWR_DET_0_LCD_RANGE 6:6 |
| 1804 #define APBDEV_PMC_PWR_DET_0_LCD_WOFFSET 0x0 |
| 1805 #define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT _MK_MASK_CONST(0
x1) |
| 1806 #define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1807 #define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1808 #define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1809 #define APBDEV_PMC_PWR_DET_0_LCD_ENABLE _MK_ENUM_CONST(0) |
| 1810 #define APBDEV_PMC_PWR_DET_0_LCD_DISABLE _MK_ENUM_CONST(1
) |
| 1811 |
| 1812 //rail mem IOs |
| 1813 #define APBDEV_PMC_PWR_DET_0_MEM_SHIFT _MK_SHIFT_CONST(7) |
| 1814 #define APBDEV_PMC_PWR_DET_0_MEM_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_MEM_SHIFT) |
| 1815 #define APBDEV_PMC_PWR_DET_0_MEM_RANGE 7:7 |
| 1816 #define APBDEV_PMC_PWR_DET_0_MEM_WOFFSET 0x0 |
| 1817 #define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT _MK_MASK_CONST(0
x1) |
| 1818 #define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1819 #define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1820 #define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1821 #define APBDEV_PMC_PWR_DET_0_MEM_ENABLE _MK_ENUM_CONST(0) |
| 1822 #define APBDEV_PMC_PWR_DET_0_MEM_DISABLE _MK_ENUM_CONST(1
) |
| 1823 |
| 1824 //rail sd IOs |
| 1825 #define APBDEV_PMC_PWR_DET_0_SD_SHIFT _MK_SHIFT_CONST(8) |
| 1826 #define APBDEV_PMC_PWR_DET_0_SD_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_PWR_DET_0_SD_SHIFT) |
| 1827 #define APBDEV_PMC_PWR_DET_0_SD_RANGE 8:8 |
| 1828 #define APBDEV_PMC_PWR_DET_0_SD_WOFFSET 0x0 |
| 1829 #define APBDEV_PMC_PWR_DET_0_SD_DEFAULT _MK_MASK_CONST(0x1) |
| 1830 #define APBDEV_PMC_PWR_DET_0_SD_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 1831 #define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 1832 #define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1833 #define APBDEV_PMC_PWR_DET_0_SD_ENABLE _MK_ENUM_CONST(0) |
| 1834 #define APBDEV_PMC_PWR_DET_0_SD_DISABLE _MK_ENUM_CONST(1) |
| 1835 |
| 1836 |
| 1837 // Register APBDEV_PMC_PWR_DET_LATCH_0 |
| 1838 #define APBDEV_PMC_PWR_DET_LATCH_0 _MK_ADDR_CONST(0x4c) |
| 1839 #define APBDEV_PMC_PWR_DET_LATCH_0_SECURE 0x0 |
| 1840 #define APBDEV_PMC_PWR_DET_LATCH_0_WORD_COUNT 0x1 |
| 1841 #define APBDEV_PMC_PWR_DET_LATCH_0_RESET_VAL _MK_MASK_CONST(0
x1) |
| 1842 #define APBDEV_PMC_PWR_DET_LATCH_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 1843 #define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 1844 #define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1845 #define APBDEV_PMC_PWR_DET_LATCH_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 1846 #define APBDEV_PMC_PWR_DET_LATCH_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 1847 //power detect latch, latches value as long set to 1 |
| 1848 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT _MK_SHIFT_CONST(
0) |
| 1849 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT) |
| 1850 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_RANGE 0:0 |
| 1851 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_WOFFSET 0x0 |
| 1852 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT _MK_MASK
_CONST(0x1) |
| 1853 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 1854 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1855 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 1856 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_ENABLE _MK_ENUM_CONST(0
) |
| 1857 #define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DISABLE _MK_ENUM
_CONST(1) |
| 1858 |
| 1859 |
| 1860 // Register APBDEV_PMC_SCRATCH0_0 // Scratch register |
| 1861 #define APBDEV_PMC_SCRATCH0_0 _MK_ADDR_CONST(0x50) |
| 1862 #define APBDEV_PMC_SCRATCH0_0_SECURE 0x0 |
| 1863 #define APBDEV_PMC_SCRATCH0_0_WORD_COUNT 0x1 |
| 1864 #define APBDEV_PMC_SCRATCH0_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1865 #define APBDEV_PMC_SCRATCH0_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 1866 #define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1867 #define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1868 #define APBDEV_PMC_SCRATCH0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1869 #define APBDEV_PMC_SCRATCH0_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1870 // General purpose register storage |
| 1871 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT _MK_SHIFT_CONST(
0) |
| 1872 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT) |
| 1873 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_RANGE 31:0 |
| 1874 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_WOFFSET 0x0 |
| 1875 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT _MK_MASK_CONST(0
x0) |
| 1876 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 1877 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1878 #define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1879 |
| 1880 |
| 1881 // Register APBDEV_PMC_SCRATCH1_0 // Scratch register |
| 1882 #define APBDEV_PMC_SCRATCH1_0 _MK_ADDR_CONST(0x54) |
| 1883 #define APBDEV_PMC_SCRATCH1_0_SECURE 0x0 |
| 1884 #define APBDEV_PMC_SCRATCH1_0_WORD_COUNT 0x1 |
| 1885 #define APBDEV_PMC_SCRATCH1_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1886 #define APBDEV_PMC_SCRATCH1_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1887 #define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1888 #define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1889 #define APBDEV_PMC_SCRATCH1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1890 #define APBDEV_PMC_SCRATCH1_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1891 // General purpose register storage |
| 1892 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT _MK_SHIFT_CONST(
0) |
| 1893 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT) |
| 1894 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_RANGE 31:0 |
| 1895 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_WOFFSET 0x0 |
| 1896 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT _MK_MASK_CONST(0
x0) |
| 1897 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1898 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1899 #define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1900 |
| 1901 |
| 1902 // Register APBDEV_PMC_SCRATCH2_0 // Scratch register |
| 1903 #define APBDEV_PMC_SCRATCH2_0 _MK_ADDR_CONST(0x58) |
| 1904 #define APBDEV_PMC_SCRATCH2_0_SECURE 0x0 |
| 1905 #define APBDEV_PMC_SCRATCH2_0_WORD_COUNT 0x1 |
| 1906 #define APBDEV_PMC_SCRATCH2_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1907 #define APBDEV_PMC_SCRATCH2_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1908 #define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1909 #define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1910 #define APBDEV_PMC_SCRATCH2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1911 #define APBDEV_PMC_SCRATCH2_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1912 // General purpose register storage |
| 1913 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT _MK_SHIFT_CONST(
0) |
| 1914 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT) |
| 1915 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_RANGE 31:0 |
| 1916 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_WOFFSET 0x0 |
| 1917 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT _MK_MASK_CONST(0
x0) |
| 1918 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1919 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1920 #define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1921 |
| 1922 |
| 1923 // Register APBDEV_PMC_SCRATCH3_0 // Scratch register |
| 1924 #define APBDEV_PMC_SCRATCH3_0 _MK_ADDR_CONST(0x5c) |
| 1925 #define APBDEV_PMC_SCRATCH3_0_SECURE 0x0 |
| 1926 #define APBDEV_PMC_SCRATCH3_0_WORD_COUNT 0x1 |
| 1927 #define APBDEV_PMC_SCRATCH3_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1928 #define APBDEV_PMC_SCRATCH3_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1929 #define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1930 #define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1931 #define APBDEV_PMC_SCRATCH3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1932 #define APBDEV_PMC_SCRATCH3_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1933 // General purpose register storage |
| 1934 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT _MK_SHIFT_CONST(
0) |
| 1935 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT) |
| 1936 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_RANGE 31:0 |
| 1937 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_WOFFSET 0x0 |
| 1938 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT _MK_MASK_CONST(0
x0) |
| 1939 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1940 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1941 #define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1942 |
| 1943 |
| 1944 // Register APBDEV_PMC_SCRATCH4_0 // Scratch register |
| 1945 #define APBDEV_PMC_SCRATCH4_0 _MK_ADDR_CONST(0x60) |
| 1946 #define APBDEV_PMC_SCRATCH4_0_SECURE 0x0 |
| 1947 #define APBDEV_PMC_SCRATCH4_0_WORD_COUNT 0x1 |
| 1948 #define APBDEV_PMC_SCRATCH4_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1949 #define APBDEV_PMC_SCRATCH4_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1950 #define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1951 #define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1952 #define APBDEV_PMC_SCRATCH4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1953 #define APBDEV_PMC_SCRATCH4_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1954 // General purpose register storage |
| 1955 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT _MK_SHIFT_CONST(
0) |
| 1956 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT) |
| 1957 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_RANGE 31:0 |
| 1958 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_WOFFSET 0x0 |
| 1959 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT _MK_MASK_CONST(0
x0) |
| 1960 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1961 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1962 #define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1963 |
| 1964 |
| 1965 // Register APBDEV_PMC_SCRATCH5_0 // Scratch register |
| 1966 #define APBDEV_PMC_SCRATCH5_0 _MK_ADDR_CONST(0x64) |
| 1967 #define APBDEV_PMC_SCRATCH5_0_SECURE 0x0 |
| 1968 #define APBDEV_PMC_SCRATCH5_0_WORD_COUNT 0x1 |
| 1969 #define APBDEV_PMC_SCRATCH5_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1970 #define APBDEV_PMC_SCRATCH5_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1971 #define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1972 #define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1973 #define APBDEV_PMC_SCRATCH5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1974 #define APBDEV_PMC_SCRATCH5_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1975 // General purpose register storage |
| 1976 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT _MK_SHIFT_CONST(
0) |
| 1977 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT) |
| 1978 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_RANGE 31:0 |
| 1979 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_WOFFSET 0x0 |
| 1980 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT _MK_MASK_CONST(0
x0) |
| 1981 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1982 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 1983 #define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 1984 |
| 1985 |
| 1986 // Register APBDEV_PMC_SCRATCH6_0 // Scratch register |
| 1987 #define APBDEV_PMC_SCRATCH6_0 _MK_ADDR_CONST(0x68) |
| 1988 #define APBDEV_PMC_SCRATCH6_0_SECURE 0x0 |
| 1989 #define APBDEV_PMC_SCRATCH6_0_WORD_COUNT 0x1 |
| 1990 #define APBDEV_PMC_SCRATCH6_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 1991 #define APBDEV_PMC_SCRATCH6_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 1992 #define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 1993 #define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 1994 #define APBDEV_PMC_SCRATCH6_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 1995 #define APBDEV_PMC_SCRATCH6_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 1996 // General purpose register storage |
| 1997 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT _MK_SHIFT_CONST(
0) |
| 1998 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT) |
| 1999 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_RANGE 31:0 |
| 2000 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_WOFFSET 0x0 |
| 2001 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT _MK_MASK_CONST(0
x0) |
| 2002 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2003 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2004 #define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2005 |
| 2006 |
| 2007 // Register APBDEV_PMC_SCRATCH7_0 // Scratch register |
| 2008 #define APBDEV_PMC_SCRATCH7_0 _MK_ADDR_CONST(0x6c) |
| 2009 #define APBDEV_PMC_SCRATCH7_0_SECURE 0x0 |
| 2010 #define APBDEV_PMC_SCRATCH7_0_WORD_COUNT 0x1 |
| 2011 #define APBDEV_PMC_SCRATCH7_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2012 #define APBDEV_PMC_SCRATCH7_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2013 #define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2014 #define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2015 #define APBDEV_PMC_SCRATCH7_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2016 #define APBDEV_PMC_SCRATCH7_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2017 // General purpose register storage |
| 2018 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT _MK_SHIFT_CONST(
0) |
| 2019 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT) |
| 2020 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_RANGE 31:0 |
| 2021 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_WOFFSET 0x0 |
| 2022 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT _MK_MASK_CONST(0
x0) |
| 2023 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2024 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2025 #define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2026 |
| 2027 |
| 2028 // Register APBDEV_PMC_SCRATCH8_0 // Scratch register |
| 2029 #define APBDEV_PMC_SCRATCH8_0 _MK_ADDR_CONST(0x70) |
| 2030 #define APBDEV_PMC_SCRATCH8_0_SECURE 0x0 |
| 2031 #define APBDEV_PMC_SCRATCH8_0_WORD_COUNT 0x1 |
| 2032 #define APBDEV_PMC_SCRATCH8_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2033 #define APBDEV_PMC_SCRATCH8_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2034 #define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2035 #define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2036 #define APBDEV_PMC_SCRATCH8_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2037 #define APBDEV_PMC_SCRATCH8_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2038 // General purpose register storage |
| 2039 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT _MK_SHIFT_CONST(
0) |
| 2040 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT) |
| 2041 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_RANGE 31:0 |
| 2042 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_WOFFSET 0x0 |
| 2043 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT _MK_MASK_CONST(0
x0) |
| 2044 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2045 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2046 #define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2047 |
| 2048 |
| 2049 // Register APBDEV_PMC_SCRATCH9_0 // Scratch register |
| 2050 #define APBDEV_PMC_SCRATCH9_0 _MK_ADDR_CONST(0x74) |
| 2051 #define APBDEV_PMC_SCRATCH9_0_SECURE 0x0 |
| 2052 #define APBDEV_PMC_SCRATCH9_0_WORD_COUNT 0x1 |
| 2053 #define APBDEV_PMC_SCRATCH9_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2054 #define APBDEV_PMC_SCRATCH9_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2055 #define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2056 #define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2057 #define APBDEV_PMC_SCRATCH9_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2058 #define APBDEV_PMC_SCRATCH9_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2059 // General purpose register storage |
| 2060 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT _MK_SHIFT_CONST(
0) |
| 2061 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT) |
| 2062 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_RANGE 31:0 |
| 2063 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_WOFFSET 0x0 |
| 2064 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT _MK_MASK_CONST(0
x0) |
| 2065 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2066 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2067 #define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2068 |
| 2069 |
| 2070 // Register APBDEV_PMC_SCRATCH10_0 // Scratch register |
| 2071 #define APBDEV_PMC_SCRATCH10_0 _MK_ADDR_CONST(0x78) |
| 2072 #define APBDEV_PMC_SCRATCH10_0_SECURE 0x0 |
| 2073 #define APBDEV_PMC_SCRATCH10_0_WORD_COUNT 0x1 |
| 2074 #define APBDEV_PMC_SCRATCH10_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2075 #define APBDEV_PMC_SCRATCH10_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2076 #define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2077 #define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2078 #define APBDEV_PMC_SCRATCH10_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2079 #define APBDEV_PMC_SCRATCH10_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2080 // General purpose register storage |
| 2081 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT _MK_SHIFT_CONST(
0) |
| 2082 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT) |
| 2083 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_RANGE 31:0 |
| 2084 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_WOFFSET 0x0 |
| 2085 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT _MK_MASK
_CONST(0x0) |
| 2086 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2087 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2088 #define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2089 |
| 2090 |
| 2091 // Register APBDEV_PMC_SCRATCH11_0 // Scratch register |
| 2092 #define APBDEV_PMC_SCRATCH11_0 _MK_ADDR_CONST(0x7c) |
| 2093 #define APBDEV_PMC_SCRATCH11_0_SECURE 0x0 |
| 2094 #define APBDEV_PMC_SCRATCH11_0_WORD_COUNT 0x1 |
| 2095 #define APBDEV_PMC_SCRATCH11_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2096 #define APBDEV_PMC_SCRATCH11_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2097 #define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2098 #define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2099 #define APBDEV_PMC_SCRATCH11_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2100 #define APBDEV_PMC_SCRATCH11_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2101 // General purpose register storage |
| 2102 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT _MK_SHIFT_CONST(
0) |
| 2103 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT) |
| 2104 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_RANGE 31:0 |
| 2105 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_WOFFSET 0x0 |
| 2106 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT _MK_MASK
_CONST(0x0) |
| 2107 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2108 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2109 #define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2110 |
| 2111 |
| 2112 // Register APBDEV_PMC_SCRATCH12_0 // Scratch register |
| 2113 #define APBDEV_PMC_SCRATCH12_0 _MK_ADDR_CONST(0x80) |
| 2114 #define APBDEV_PMC_SCRATCH12_0_SECURE 0x0 |
| 2115 #define APBDEV_PMC_SCRATCH12_0_WORD_COUNT 0x1 |
| 2116 #define APBDEV_PMC_SCRATCH12_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2117 #define APBDEV_PMC_SCRATCH12_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2118 #define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2119 #define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2120 #define APBDEV_PMC_SCRATCH12_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2121 #define APBDEV_PMC_SCRATCH12_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2122 // General purpose register storage |
| 2123 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT _MK_SHIFT_CONST(
0) |
| 2124 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT) |
| 2125 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_RANGE 31:0 |
| 2126 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_WOFFSET 0x0 |
| 2127 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT _MK_MASK
_CONST(0x0) |
| 2128 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2129 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2130 #define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2131 |
| 2132 |
| 2133 // Register APBDEV_PMC_SCRATCH13_0 // Scratch register |
| 2134 #define APBDEV_PMC_SCRATCH13_0 _MK_ADDR_CONST(0x84) |
| 2135 #define APBDEV_PMC_SCRATCH13_0_SECURE 0x0 |
| 2136 #define APBDEV_PMC_SCRATCH13_0_WORD_COUNT 0x1 |
| 2137 #define APBDEV_PMC_SCRATCH13_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2138 #define APBDEV_PMC_SCRATCH13_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2139 #define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2140 #define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2141 #define APBDEV_PMC_SCRATCH13_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2142 #define APBDEV_PMC_SCRATCH13_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2143 // General purpose register storage |
| 2144 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT _MK_SHIFT_CONST(
0) |
| 2145 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT) |
| 2146 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_RANGE 31:0 |
| 2147 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_WOFFSET 0x0 |
| 2148 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT _MK_MASK
_CONST(0x0) |
| 2149 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2150 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2151 #define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2152 |
| 2153 |
| 2154 // Register APBDEV_PMC_SCRATCH14_0 // Scratch register |
| 2155 #define APBDEV_PMC_SCRATCH14_0 _MK_ADDR_CONST(0x88) |
| 2156 #define APBDEV_PMC_SCRATCH14_0_SECURE 0x0 |
| 2157 #define APBDEV_PMC_SCRATCH14_0_WORD_COUNT 0x1 |
| 2158 #define APBDEV_PMC_SCRATCH14_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2159 #define APBDEV_PMC_SCRATCH14_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2160 #define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2161 #define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2162 #define APBDEV_PMC_SCRATCH14_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2163 #define APBDEV_PMC_SCRATCH14_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2164 // General purpose register storage |
| 2165 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT _MK_SHIFT_CONST(
0) |
| 2166 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT) |
| 2167 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_RANGE 31:0 |
| 2168 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_WOFFSET 0x0 |
| 2169 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT _MK_MASK
_CONST(0x0) |
| 2170 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2171 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2172 #define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2173 |
| 2174 |
| 2175 // Register APBDEV_PMC_SCRATCH15_0 // Scratch register |
| 2176 #define APBDEV_PMC_SCRATCH15_0 _MK_ADDR_CONST(0x8c) |
| 2177 #define APBDEV_PMC_SCRATCH15_0_SECURE 0x0 |
| 2178 #define APBDEV_PMC_SCRATCH15_0_WORD_COUNT 0x1 |
| 2179 #define APBDEV_PMC_SCRATCH15_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2180 #define APBDEV_PMC_SCRATCH15_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2181 #define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2182 #define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2183 #define APBDEV_PMC_SCRATCH15_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2184 #define APBDEV_PMC_SCRATCH15_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2185 // General purpose register storage |
| 2186 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT _MK_SHIFT_CONST(
0) |
| 2187 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT) |
| 2188 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_RANGE 31:0 |
| 2189 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_WOFFSET 0x0 |
| 2190 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT _MK_MASK
_CONST(0x0) |
| 2191 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2192 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2193 #define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2194 |
| 2195 |
| 2196 // Register APBDEV_PMC_SCRATCH16_0 // Scratch register |
| 2197 #define APBDEV_PMC_SCRATCH16_0 _MK_ADDR_CONST(0x90) |
| 2198 #define APBDEV_PMC_SCRATCH16_0_SECURE 0x0 |
| 2199 #define APBDEV_PMC_SCRATCH16_0_WORD_COUNT 0x1 |
| 2200 #define APBDEV_PMC_SCRATCH16_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2201 #define APBDEV_PMC_SCRATCH16_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2202 #define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2203 #define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2204 #define APBDEV_PMC_SCRATCH16_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2205 #define APBDEV_PMC_SCRATCH16_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2206 // General purpose register storage |
| 2207 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT _MK_SHIFT_CONST(
0) |
| 2208 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT) |
| 2209 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_RANGE 31:0 |
| 2210 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_WOFFSET 0x0 |
| 2211 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT _MK_MASK
_CONST(0x0) |
| 2212 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2213 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2214 #define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2215 |
| 2216 |
| 2217 // Register APBDEV_PMC_SCRATCH17_0 // Scratch register |
| 2218 #define APBDEV_PMC_SCRATCH17_0 _MK_ADDR_CONST(0x94) |
| 2219 #define APBDEV_PMC_SCRATCH17_0_SECURE 0x0 |
| 2220 #define APBDEV_PMC_SCRATCH17_0_WORD_COUNT 0x1 |
| 2221 #define APBDEV_PMC_SCRATCH17_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2222 #define APBDEV_PMC_SCRATCH17_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2223 #define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2224 #define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2225 #define APBDEV_PMC_SCRATCH17_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2226 #define APBDEV_PMC_SCRATCH17_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2227 // General purpose register storage |
| 2228 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT _MK_SHIFT_CONST(
0) |
| 2229 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT) |
| 2230 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_RANGE 31:0 |
| 2231 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_WOFFSET 0x0 |
| 2232 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT _MK_MASK
_CONST(0x0) |
| 2233 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2234 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2235 #define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2236 |
| 2237 |
| 2238 // Register APBDEV_PMC_SCRATCH18_0 // Scratch register |
| 2239 #define APBDEV_PMC_SCRATCH18_0 _MK_ADDR_CONST(0x98) |
| 2240 #define APBDEV_PMC_SCRATCH18_0_SECURE 0x0 |
| 2241 #define APBDEV_PMC_SCRATCH18_0_WORD_COUNT 0x1 |
| 2242 #define APBDEV_PMC_SCRATCH18_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2243 #define APBDEV_PMC_SCRATCH18_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2244 #define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2245 #define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2246 #define APBDEV_PMC_SCRATCH18_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2247 #define APBDEV_PMC_SCRATCH18_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2248 // General purpose register storage |
| 2249 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT _MK_SHIFT_CONST(
0) |
| 2250 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT) |
| 2251 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_RANGE 31:0 |
| 2252 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_WOFFSET 0x0 |
| 2253 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT _MK_MASK
_CONST(0x0) |
| 2254 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2255 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2256 #define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2257 |
| 2258 |
| 2259 // Register APBDEV_PMC_SCRATCH19_0 // Scratch register |
| 2260 #define APBDEV_PMC_SCRATCH19_0 _MK_ADDR_CONST(0x9c) |
| 2261 #define APBDEV_PMC_SCRATCH19_0_SECURE 0x0 |
| 2262 #define APBDEV_PMC_SCRATCH19_0_WORD_COUNT 0x1 |
| 2263 #define APBDEV_PMC_SCRATCH19_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2264 #define APBDEV_PMC_SCRATCH19_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2265 #define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2266 #define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2267 #define APBDEV_PMC_SCRATCH19_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2268 #define APBDEV_PMC_SCRATCH19_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2269 // General purpose register storage |
| 2270 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT _MK_SHIFT_CONST(
0) |
| 2271 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT) |
| 2272 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_RANGE 31:0 |
| 2273 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_WOFFSET 0x0 |
| 2274 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT _MK_MASK
_CONST(0x0) |
| 2275 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2276 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2277 #define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2278 |
| 2279 |
| 2280 // Register APBDEV_PMC_SCRATCH20_0 // Scratch register |
| 2281 #define APBDEV_PMC_SCRATCH20_0 _MK_ADDR_CONST(0xa0) |
| 2282 #define APBDEV_PMC_SCRATCH20_0_SECURE 0x0 |
| 2283 #define APBDEV_PMC_SCRATCH20_0_WORD_COUNT 0x1 |
| 2284 #define APBDEV_PMC_SCRATCH20_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2285 #define APBDEV_PMC_SCRATCH20_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2286 #define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2287 #define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2288 #define APBDEV_PMC_SCRATCH20_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2289 #define APBDEV_PMC_SCRATCH20_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2290 // General purpose register storage |
| 2291 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT _MK_SHIFT_CONST(
0) |
| 2292 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT) |
| 2293 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_RANGE 31:0 |
| 2294 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_WOFFSET 0x0 |
| 2295 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT _MK_MASK
_CONST(0x0) |
| 2296 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2297 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2298 #define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2299 |
| 2300 |
| 2301 // Register APBDEV_PMC_SCRATCH21_0 // Scratch register |
| 2302 #define APBDEV_PMC_SCRATCH21_0 _MK_ADDR_CONST(0xa4) |
| 2303 #define APBDEV_PMC_SCRATCH21_0_SECURE 0x0 |
| 2304 #define APBDEV_PMC_SCRATCH21_0_WORD_COUNT 0x1 |
| 2305 #define APBDEV_PMC_SCRATCH21_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2306 #define APBDEV_PMC_SCRATCH21_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2307 #define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2308 #define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2309 #define APBDEV_PMC_SCRATCH21_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2310 #define APBDEV_PMC_SCRATCH21_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2311 // General purpose register storage |
| 2312 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT _MK_SHIFT_CONST(
0) |
| 2313 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT) |
| 2314 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_RANGE 31:0 |
| 2315 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_WOFFSET 0x0 |
| 2316 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT _MK_MASK
_CONST(0x0) |
| 2317 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2318 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2319 #define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2320 |
| 2321 |
| 2322 // Register APBDEV_PMC_SCRATCH22_0 // Scratch register |
| 2323 #define APBDEV_PMC_SCRATCH22_0 _MK_ADDR_CONST(0xa8) |
| 2324 #define APBDEV_PMC_SCRATCH22_0_SECURE 0x0 |
| 2325 #define APBDEV_PMC_SCRATCH22_0_WORD_COUNT 0x1 |
| 2326 #define APBDEV_PMC_SCRATCH22_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2327 #define APBDEV_PMC_SCRATCH22_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2328 #define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2329 #define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2330 #define APBDEV_PMC_SCRATCH22_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2331 #define APBDEV_PMC_SCRATCH22_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2332 // General purpose register storage |
| 2333 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT _MK_SHIFT_CONST(
0) |
| 2334 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT) |
| 2335 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_RANGE 31:0 |
| 2336 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_WOFFSET 0x0 |
| 2337 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT _MK_MASK
_CONST(0x0) |
| 2338 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2339 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2340 #define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2341 |
| 2342 |
| 2343 // Register APBDEV_PMC_SCRATCH23_0 // Scratch register |
| 2344 #define APBDEV_PMC_SCRATCH23_0 _MK_ADDR_CONST(0xac) |
| 2345 #define APBDEV_PMC_SCRATCH23_0_SECURE 0x0 |
| 2346 #define APBDEV_PMC_SCRATCH23_0_WORD_COUNT 0x1 |
| 2347 #define APBDEV_PMC_SCRATCH23_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2348 #define APBDEV_PMC_SCRATCH23_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2349 #define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2350 #define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2351 #define APBDEV_PMC_SCRATCH23_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2352 #define APBDEV_PMC_SCRATCH23_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2353 // General purpose register storage |
| 2354 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT _MK_SHIFT_CONST(
0) |
| 2355 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT) |
| 2356 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_RANGE 31:0 |
| 2357 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_WOFFSET 0x0 |
| 2358 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT _MK_MASK
_CONST(0x0) |
| 2359 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2360 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2361 #define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2362 |
| 2363 |
| 2364 // Register APBDEV_PMC_SECURE_SCRATCH0_0 // Secure scratch register |
| 2365 #define APBDEV_PMC_SECURE_SCRATCH0_0 _MK_ADDR_CONST(0xb0) |
| 2366 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE 0x0 |
| 2367 #define APBDEV_PMC_SECURE_SCRATCH0_0_WORD_COUNT 0x1 |
| 2368 #define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2369 #define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2370 #define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2371 #define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2372 #define APBDEV_PMC_SECURE_SCRATCH0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2373 #define APBDEV_PMC_SECURE_SCRATCH0_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2374 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT
_MK_SHIFT_CONST(0) |
| 2375 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIF
T) |
| 2376 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_RANGE
31:0 |
| 2377 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_WOFFSET
0x0 |
| 2378 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT
_MK_MASK_CONST(0x0) |
| 2379 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2380 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2381 #define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2382 |
| 2383 |
| 2384 // Register APBDEV_PMC_SECURE_SCRATCH1_0 // Secure scratch register |
| 2385 #define APBDEV_PMC_SECURE_SCRATCH1_0 _MK_ADDR_CONST(0xb4) |
| 2386 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE 0x0 |
| 2387 #define APBDEV_PMC_SECURE_SCRATCH1_0_WORD_COUNT 0x1 |
| 2388 #define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2389 #define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2390 #define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2391 #define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2392 #define APBDEV_PMC_SECURE_SCRATCH1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2393 #define APBDEV_PMC_SECURE_SCRATCH1_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2394 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT
_MK_SHIFT_CONST(0) |
| 2395 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIF
T) |
| 2396 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_RANGE
31:0 |
| 2397 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_WOFFSET
0x0 |
| 2398 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT
_MK_MASK_CONST(0x0) |
| 2399 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2400 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2401 #define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2402 |
| 2403 |
| 2404 // Register APBDEV_PMC_SECURE_SCRATCH2_0 // Secure scratch register |
| 2405 #define APBDEV_PMC_SECURE_SCRATCH2_0 _MK_ADDR_CONST(0xb8) |
| 2406 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE 0x0 |
| 2407 #define APBDEV_PMC_SECURE_SCRATCH2_0_WORD_COUNT 0x1 |
| 2408 #define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2409 #define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2410 #define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2411 #define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2412 #define APBDEV_PMC_SECURE_SCRATCH2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2413 #define APBDEV_PMC_SECURE_SCRATCH2_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2414 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT
_MK_SHIFT_CONST(0) |
| 2415 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIF
T) |
| 2416 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_RANGE
31:0 |
| 2417 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_WOFFSET
0x0 |
| 2418 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT
_MK_MASK_CONST(0x0) |
| 2419 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2420 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2421 #define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2422 |
| 2423 |
| 2424 // Register APBDEV_PMC_SECURE_SCRATCH3_0 // Secure scratch register |
| 2425 #define APBDEV_PMC_SECURE_SCRATCH3_0 _MK_ADDR_CONST(0xbc) |
| 2426 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE 0x0 |
| 2427 #define APBDEV_PMC_SECURE_SCRATCH3_0_WORD_COUNT 0x1 |
| 2428 #define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2429 #define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2430 #define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2431 #define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2432 #define APBDEV_PMC_SECURE_SCRATCH3_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2433 #define APBDEV_PMC_SECURE_SCRATCH3_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2434 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT
_MK_SHIFT_CONST(0) |
| 2435 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIF
T) |
| 2436 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_RANGE
31:0 |
| 2437 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_WOFFSET
0x0 |
| 2438 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT
_MK_MASK_CONST(0x0) |
| 2439 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2440 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2441 #define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2442 |
| 2443 |
| 2444 // Register APBDEV_PMC_SECURE_SCRATCH4_0 // Secure scratch register |
| 2445 #define APBDEV_PMC_SECURE_SCRATCH4_0 _MK_ADDR_CONST(0xc0) |
| 2446 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE 0x0 |
| 2447 #define APBDEV_PMC_SECURE_SCRATCH4_0_WORD_COUNT 0x1 |
| 2448 #define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2449 #define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2450 #define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2451 #define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2452 #define APBDEV_PMC_SECURE_SCRATCH4_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2453 #define APBDEV_PMC_SECURE_SCRATCH4_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2454 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIFT
_MK_SHIFT_CONST(0) |
| 2455 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIF
T) |
| 2456 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_RANGE
31:0 |
| 2457 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_WOFFSET
0x0 |
| 2458 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT
_MK_MASK_CONST(0x0) |
| 2459 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2460 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2461 #define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2462 |
| 2463 |
| 2464 // Register APBDEV_PMC_SECURE_SCRATCH5_0 // Secure scratch register |
| 2465 #define APBDEV_PMC_SECURE_SCRATCH5_0 _MK_ADDR_CONST(0xc4) |
| 2466 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE 0x0 |
| 2467 #define APBDEV_PMC_SECURE_SCRATCH5_0_WORD_COUNT 0x1 |
| 2468 #define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2469 #define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 2470 #define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2471 #define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2472 #define APBDEV_PMC_SECURE_SCRATCH5_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2473 #define APBDEV_PMC_SECURE_SCRATCH5_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2474 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIFT
_MK_SHIFT_CONST(0) |
| 2475 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIF
T) |
| 2476 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_RANGE
31:0 |
| 2477 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_WOFFSET
0x0 |
| 2478 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT
_MK_MASK_CONST(0x0) |
| 2479 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2480 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2481 #define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2482 |
| 2483 |
| 2484 // Register APBDEV_PMC_CPUPWRGOOD_TIMER_0 |
| 2485 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0 _MK_ADDR_CONST(0xc8) |
| 2486 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SECURE 0x0 |
| 2487 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WORD_COUNT 0x1 |
| 2488 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_VAL _MK_MASK
_CONST(0xffff) |
| 2489 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 2490 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2491 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2492 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 2493 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2494 // timer data |
| 2495 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT _MK_SHIF
T_CONST(0) |
| 2496 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_FIELD (_MK_MAS
K_CONST(0xffffffff) << APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT) |
| 2497 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_RANGE 31:0 |
| 2498 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_WOFFSET 0x0 |
| 2499 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT _MK_MASK
_CONST(0xffff) |
| 2500 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 2501 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2502 #define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2503 |
| 2504 |
| 2505 // Register APBDEV_PMC_CPUPWROFF_TIMER_0 |
| 2506 #define APBDEV_PMC_CPUPWROFF_TIMER_0 _MK_ADDR_CONST(0xcc) |
| 2507 #define APBDEV_PMC_CPUPWROFF_TIMER_0_SECURE 0x0 |
| 2508 #define APBDEV_PMC_CPUPWROFF_TIMER_0_WORD_COUNT 0x1 |
| 2509 #define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_VAL _MK_MASK_CONST(0
xffff) |
| 2510 #define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 2511 #define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2512 #define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2513 #define APBDEV_PMC_CPUPWROFF_TIMER_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2514 #define APBDEV_PMC_CPUPWROFF_TIMER_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2515 // timer data |
| 2516 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT _MK_SHIFT_CONST(
0) |
| 2517 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT) |
| 2518 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_RANGE 31:0 |
| 2519 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_WOFFSET 0x0 |
| 2520 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT _MK_MASK
_CONST(0xffff) |
| 2521 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT_MASK _MK_MASK
_CONST(0xffffffff) |
| 2522 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2523 #define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2524 |
| 2525 |
| 2526 // Register APBDEV_PMC_PG_MASK_0 |
| 2527 #define APBDEV_PMC_PG_MASK_0 _MK_ADDR_CONST(0xd0) |
| 2528 #define APBDEV_PMC_PG_MASK_0_SECURE 0x0 |
| 2529 #define APBDEV_PMC_PG_MASK_0_WORD_COUNT 0x1 |
| 2530 #define APBDEV_PMC_PG_MASK_0_RESET_VAL _MK_MASK_CONST(0xfffffff
f) |
| 2531 #define APBDEV_PMC_PG_MASK_0_RESET_MASK _MK_MASK_CONST(0
xffffffff) |
| 2532 #define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2533 #define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2534 #define APBDEV_PMC_PG_MASK_0_READ_MASK _MK_MASK_CONST(0xfffffff
f) |
| 2535 #define APBDEV_PMC_PG_MASK_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2536 // Mask TD rail |
| 2537 #define APBDEV_PMC_PG_MASK_0_TD_SHIFT _MK_SHIFT_CONST(0) |
| 2538 #define APBDEV_PMC_PG_MASK_0_TD_FIELD (_MK_MASK_CONST(0xff) <<
APBDEV_PMC_PG_MASK_0_TD_SHIFT) |
| 2539 #define APBDEV_PMC_PG_MASK_0_TD_RANGE 7:0 |
| 2540 #define APBDEV_PMC_PG_MASK_0_TD_WOFFSET 0x0 |
| 2541 #define APBDEV_PMC_PG_MASK_0_TD_DEFAULT _MK_MASK_CONST(0xff) |
| 2542 #define APBDEV_PMC_PG_MASK_0_TD_DEFAULT_MASK _MK_MASK_CONST(0
xff) |
| 2543 #define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2544 #define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2545 |
| 2546 // Mask VE rail |
| 2547 #define APBDEV_PMC_PG_MASK_0_VE_SHIFT _MK_SHIFT_CONST(8) |
| 2548 #define APBDEV_PMC_PG_MASK_0_VE_FIELD (_MK_MASK_CONST(0xff) <<
APBDEV_PMC_PG_MASK_0_VE_SHIFT) |
| 2549 #define APBDEV_PMC_PG_MASK_0_VE_RANGE 15:8 |
| 2550 #define APBDEV_PMC_PG_MASK_0_VE_WOFFSET 0x0 |
| 2551 #define APBDEV_PMC_PG_MASK_0_VE_DEFAULT _MK_MASK_CONST(0xff) |
| 2552 #define APBDEV_PMC_PG_MASK_0_VE_DEFAULT_MASK _MK_MASK_CONST(0
xff) |
| 2553 #define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2554 #define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2555 |
| 2556 // Mask VDE rail |
| 2557 #define APBDEV_PMC_PG_MASK_0_VD_SHIFT _MK_SHIFT_CONST(16) |
| 2558 #define APBDEV_PMC_PG_MASK_0_VD_FIELD (_MK_MASK_CONST(0xff) <<
APBDEV_PMC_PG_MASK_0_VD_SHIFT) |
| 2559 #define APBDEV_PMC_PG_MASK_0_VD_RANGE 23:16 |
| 2560 #define APBDEV_PMC_PG_MASK_0_VD_WOFFSET 0x0 |
| 2561 #define APBDEV_PMC_PG_MASK_0_VD_DEFAULT _MK_MASK_CONST(0xff) |
| 2562 #define APBDEV_PMC_PG_MASK_0_VD_DEFAULT_MASK _MK_MASK_CONST(0
xff) |
| 2563 #define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2564 #define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2565 |
| 2566 // Mask PCX rail |
| 2567 #define APBDEV_PMC_PG_MASK_0_PX_SHIFT _MK_SHIFT_CONST(24) |
| 2568 #define APBDEV_PMC_PG_MASK_0_PX_FIELD (_MK_MASK_CONST(0xff) <<
APBDEV_PMC_PG_MASK_0_PX_SHIFT) |
| 2569 #define APBDEV_PMC_PG_MASK_0_PX_RANGE 31:24 |
| 2570 #define APBDEV_PMC_PG_MASK_0_PX_WOFFSET 0x0 |
| 2571 #define APBDEV_PMC_PG_MASK_0_PX_DEFAULT _MK_MASK_CONST(0xff) |
| 2572 #define APBDEV_PMC_PG_MASK_0_PX_DEFAULT_MASK _MK_MASK_CONST(0
xff) |
| 2573 #define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2574 #define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2575 |
| 2576 |
| 2577 // Register APBDEV_PMC_PG_MASK_1_0 |
| 2578 #define APBDEV_PMC_PG_MASK_1_0 _MK_ADDR_CONST(0xd4) |
| 2579 #define APBDEV_PMC_PG_MASK_1_0_SECURE 0x0 |
| 2580 #define APBDEV_PMC_PG_MASK_1_0_WORD_COUNT 0x1 |
| 2581 #define APBDEV_PMC_PG_MASK_1_0_RESET_VAL _MK_MASK_CONST(0
xff01) |
| 2582 #define APBDEV_PMC_PG_MASK_1_0_RESET_MASK _MK_MASK_CONST(0
xff01) |
| 2583 #define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2584 #define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2585 #define APBDEV_PMC_PG_MASK_1_0_READ_MASK _MK_MASK_CONST(0
xff01) |
| 2586 #define APBDEV_PMC_PG_MASK_1_0_WRITE_MASK _MK_MASK_CONST(0
xff01) |
| 2587 // MASK L2C rail |
| 2588 #define APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT _MK_SHIFT_CONST(
0) |
| 2589 #define APBDEV_PMC_PG_MASK_1_0_L2C_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT) |
| 2590 #define APBDEV_PMC_PG_MASK_1_0_L2C_RANGE 0:0 |
| 2591 #define APBDEV_PMC_PG_MASK_1_0_L2C_WOFFSET 0x0 |
| 2592 #define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT _MK_MASK_CONST(0
x1) |
| 2593 #define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 2594 #define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2595 #define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2596 |
| 2597 // MASK MPE rail |
| 2598 #define APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT _MK_SHIFT_CONST(
8) |
| 2599 #define APBDEV_PMC_PG_MASK_1_0_MPE_FIELD (_MK_MASK_CONST(
0xff) << APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT) |
| 2600 #define APBDEV_PMC_PG_MASK_1_0_MPE_RANGE 15:8 |
| 2601 #define APBDEV_PMC_PG_MASK_1_0_MPE_WOFFSET 0x0 |
| 2602 #define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT _MK_MASK_CONST(0
xff) |
| 2603 #define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT_MASK _MK_MASK_CONST(0
xff) |
| 2604 #define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2605 #define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2606 |
| 2607 |
| 2608 // Register APBDEV_PMC_AUTO_WAKE_LVL_0 |
| 2609 #define APBDEV_PMC_AUTO_WAKE_LVL_0 _MK_ADDR_CONST(0xd8) |
| 2610 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SECURE 0x0 |
| 2611 #define APBDEV_PMC_AUTO_WAKE_LVL_0_WORD_COUNT 0x1 |
| 2612 #define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2613 #define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 2614 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2615 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2616 #define APBDEV_PMC_AUTO_WAKE_LVL_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 2617 #define APBDEV_PMC_AUTO_WAKE_LVL_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 2618 //Causes PMC to sample the wake pads |
| 2619 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT _MK_SHIFT_CONST(
0) |
| 2620 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT) |
| 2621 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_RANGE 0:0 |
| 2622 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_WOFFSET 0x0 |
| 2623 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT _MK_MASK_CONST(0
x0) |
| 2624 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2625 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2626 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2627 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DISABLE _MK_ENUM_CONST(0
) |
| 2628 #define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_ENABLE _MK_ENUM_CONST(1
) |
| 2629 |
| 2630 |
| 2631 // Register APBDEV_PMC_AUTO_WAKE_LVL_MASK_0 |
| 2632 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0 _MK_ADDR_CONST(0xdc) |
| 2633 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SECURE 0x0 |
| 2634 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WORD_COUNT 0x1 |
| 2635 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_VAL _MK_MASK
_CONST(0x0) |
| 2636 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_MASK _MK_MASK
_CONST(0xffffffff) |
| 2637 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2638 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2639 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_READ_MASK _MK_MASK
_CONST(0xffffffff) |
| 2640 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 2641 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT _MK_SHIF
T_CONST(0) |
| 2642 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_FIELD (_MK_MAS
K_CONST(0xffffffff) << APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT) |
| 2643 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_RANGE 31:0 |
| 2644 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_WOFFSET 0x0 |
| 2645 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT _MK_MASK
_CONST(0x0) |
| 2646 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT_MASK
_MK_MASK_CONST(0xffffffff) |
| 2647 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2648 #define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2649 |
| 2650 |
| 2651 // Register APBDEV_PMC_WAKE_DELAY_0 |
| 2652 #define APBDEV_PMC_WAKE_DELAY_0 _MK_ADDR_CONST(0xe0) |
| 2653 #define APBDEV_PMC_WAKE_DELAY_0_SECURE 0x0 |
| 2654 #define APBDEV_PMC_WAKE_DELAY_0_WORD_COUNT 0x1 |
| 2655 #define APBDEV_PMC_WAKE_DELAY_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2656 #define APBDEV_PMC_WAKE_DELAY_0_RESET_MASK _MK_MASK_CONST(0
xffff) |
| 2657 #define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2658 #define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2659 #define APBDEV_PMC_WAKE_DELAY_0_READ_MASK _MK_MASK_CONST(0
xffff) |
| 2660 #define APBDEV_PMC_WAKE_DELAY_0_WRITE_MASK _MK_MASK_CONST(0
xffff) |
| 2661 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT _MK_SHIFT_CONST(
0) |
| 2662 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT) |
| 2663 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_RANGE 15:0 |
| 2664 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_WOFFSET 0x0 |
| 2665 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT _MK_MASK_CONST(0
x0) |
| 2666 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 2667 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2668 #define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2669 |
| 2670 |
| 2671 // Register APBDEV_PMC_PWR_DET_VAL_0 |
| 2672 #define APBDEV_PMC_PWR_DET_VAL_0 _MK_ADDR_CONST(0xe4) |
| 2673 #define APBDEV_PMC_PWR_DET_VAL_0_SECURE 0x0 |
| 2674 #define APBDEV_PMC_PWR_DET_VAL_0_WORD_COUNT 0x1 |
| 2675 #define APBDEV_PMC_PWR_DET_VAL_0_RESET_VAL _MK_MASK_CONST(0
x1ff) |
| 2676 #define APBDEV_PMC_PWR_DET_VAL_0_RESET_MASK _MK_MASK_CONST(0
x1ff) |
| 2677 #define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2678 #define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2679 #define APBDEV_PMC_PWR_DET_VAL_0_READ_MASK _MK_MASK_CONST(0
x1ff) |
| 2680 #define APBDEV_PMC_PWR_DET_VAL_0_WRITE_MASK _MK_MASK_CONST(0
x1ff) |
| 2681 //rail ao IOs |
| 2682 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT _MK_SHIFT_CONST(
0) |
| 2683 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT) |
| 2684 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_RANGE 0:0 |
| 2685 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_WOFFSET 0x0 |
| 2686 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT _MK_MASK_CONST(0
x1) |
| 2687 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2688 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2689 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2690 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_ENABLE _MK_ENUM_CONST(0
) |
| 2691 #define APBDEV_PMC_PWR_DET_VAL_0_SYS_DISABLE _MK_ENUM_CONST(1
) |
| 2692 |
| 2693 //rail at3 IOs |
| 2694 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT _MK_SHIFT_CONST(
1) |
| 2695 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT) |
| 2696 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_RANGE 1:1 |
| 2697 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_WOFFSET 0x0 |
| 2698 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT _MK_MASK_CONST(0
x1) |
| 2699 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2700 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2701 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2702 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_ENABLE _MK_ENUM_CONST(0
) |
| 2703 #define APBDEV_PMC_PWR_DET_VAL_0_NAND_DISABLE _MK_ENUM_CONST(1
) |
| 2704 |
| 2705 //rail dbg IOs |
| 2706 #define APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT _MK_SHIFT_CONST(
2) |
| 2707 #define APBDEV_PMC_PWR_DET_VAL_0_UART_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT) |
| 2708 #define APBDEV_PMC_PWR_DET_VAL_0_UART_RANGE 2:2 |
| 2709 #define APBDEV_PMC_PWR_DET_VAL_0_UART_WOFFSET 0x0 |
| 2710 #define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT _MK_MASK_CONST(0
x1) |
| 2711 #define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2712 #define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2713 #define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2714 #define APBDEV_PMC_PWR_DET_VAL_0_UART_ENABLE _MK_ENUM_CONST(0
) |
| 2715 #define APBDEV_PMC_PWR_DET_VAL_0_UART_DISABLE _MK_ENUM_CONST(1
) |
| 2716 |
| 2717 //rail dlcd IOs |
| 2718 #define APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT _MK_SHIFT_CONST(
3) |
| 2719 #define APBDEV_PMC_PWR_DET_VAL_0_BB_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT) |
| 2720 #define APBDEV_PMC_PWR_DET_VAL_0_BB_RANGE 3:3 |
| 2721 #define APBDEV_PMC_PWR_DET_VAL_0_BB_WOFFSET 0x0 |
| 2722 #define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT _MK_MASK_CONST(0
x1) |
| 2723 #define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2724 #define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2725 #define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2726 #define APBDEV_PMC_PWR_DET_VAL_0_BB_ENABLE _MK_ENUM_CONST(0
) |
| 2727 #define APBDEV_PMC_PWR_DET_VAL_0_BB_DISABLE _MK_ENUM_CONST(1
) |
| 2728 |
| 2729 //rail dvi IOs |
| 2730 #define APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT _MK_SHIFT_CONST(
4) |
| 2731 #define APBDEV_PMC_PWR_DET_VAL_0_VI_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT) |
| 2732 #define APBDEV_PMC_PWR_DET_VAL_0_VI_RANGE 4:4 |
| 2733 #define APBDEV_PMC_PWR_DET_VAL_0_VI_WOFFSET 0x0 |
| 2734 #define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT _MK_MASK_CONST(0
x1) |
| 2735 #define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2736 #define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2737 #define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2738 #define APBDEV_PMC_PWR_DET_VAL_0_VI_ENABLE _MK_ENUM_CONST(0
) |
| 2739 #define APBDEV_PMC_PWR_DET_VAL_0_VI_DISABLE _MK_ENUM_CONST(1
) |
| 2740 |
| 2741 //rail i2s IOs |
| 2742 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT _MK_SHIFT_CONST(
5) |
| 2743 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT) |
| 2744 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_RANGE 5:5 |
| 2745 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_WOFFSET 0x0 |
| 2746 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT _MK_MASK_CONST(0
x1) |
| 2747 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2748 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2749 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2750 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_ENABLE _MK_ENUM_CONST(0
) |
| 2751 #define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DISABLE _MK_ENUM_CONST(1
) |
| 2752 |
| 2753 //rail lcd IOs |
| 2754 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT _MK_SHIFT_CONST(
6) |
| 2755 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT) |
| 2756 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_RANGE 6:6 |
| 2757 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_WOFFSET 0x0 |
| 2758 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT _MK_MASK_CONST(0
x1) |
| 2759 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2760 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2761 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2762 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_ENABLE _MK_ENUM_CONST(0
) |
| 2763 #define APBDEV_PMC_PWR_DET_VAL_0_LCD_DISABLE _MK_ENUM_CONST(1
) |
| 2764 |
| 2765 //rail mem IOs |
| 2766 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT _MK_SHIFT_CONST(
7) |
| 2767 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT) |
| 2768 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_RANGE 7:7 |
| 2769 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_WOFFSET 0x0 |
| 2770 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT _MK_MASK_CONST(0
x1) |
| 2771 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2772 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2773 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2774 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_ENABLE _MK_ENUM_CONST(0
) |
| 2775 #define APBDEV_PMC_PWR_DET_VAL_0_MEM_DISABLE _MK_ENUM_CONST(1
) |
| 2776 |
| 2777 //rail sd IOs |
| 2778 #define APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT _MK_SHIFT_CONST(
8) |
| 2779 #define APBDEV_PMC_PWR_DET_VAL_0_SD_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT) |
| 2780 #define APBDEV_PMC_PWR_DET_VAL_0_SD_RANGE 8:8 |
| 2781 #define APBDEV_PMC_PWR_DET_VAL_0_SD_WOFFSET 0x0 |
| 2782 #define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT _MK_MASK_CONST(0
x1) |
| 2783 #define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 2784 #define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2785 #define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2786 #define APBDEV_PMC_PWR_DET_VAL_0_SD_ENABLE _MK_ENUM_CONST(0
) |
| 2787 #define APBDEV_PMC_PWR_DET_VAL_0_SD_DISABLE _MK_ENUM_CONST(1
) |
| 2788 |
| 2789 |
| 2790 // Register APBDEV_PMC_DDR_PWR_0 |
| 2791 #define APBDEV_PMC_DDR_PWR_0 _MK_ADDR_CONST(0xe8) |
| 2792 #define APBDEV_PMC_DDR_PWR_0_SECURE 0x0 |
| 2793 #define APBDEV_PMC_DDR_PWR_0_WORD_COUNT 0x1 |
| 2794 #define APBDEV_PMC_DDR_PWR_0_RESET_VAL _MK_MASK_CONST(0x1) |
| 2795 #define APBDEV_PMC_DDR_PWR_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 2796 #define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2797 #define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2798 #define APBDEV_PMC_DDR_PWR_0_READ_MASK _MK_MASK_CONST(0x1) |
| 2799 #define APBDEV_PMC_DDR_PWR_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 2800 #define APBDEV_PMC_DDR_PWR_0_VAL_SHIFT _MK_SHIFT_CONST(0) |
| 2801 #define APBDEV_PMC_DDR_PWR_0_VAL_FIELD (_MK_MASK_CONST(0x1) <<
APBDEV_PMC_DDR_PWR_0_VAL_SHIFT) |
| 2802 #define APBDEV_PMC_DDR_PWR_0_VAL_RANGE 0:0 |
| 2803 #define APBDEV_PMC_DDR_PWR_0_VAL_WOFFSET 0x0 |
| 2804 #define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT _MK_MASK_CONST(0
x1) |
| 2805 #define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 2806 #define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2807 #define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2808 #define APBDEV_PMC_DDR_PWR_0_VAL_E_12V _MK_ENUM_CONST(0) |
| 2809 #define APBDEV_PMC_DDR_PWR_0_VAL_E_18V _MK_ENUM_CONST(1) |
| 2810 |
| 2811 |
| 2812 // Register APBDEV_PMC_USB_DEBOUNCE_DEL_0 |
| 2813 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0 _MK_ADDR_CONST(0xec) |
| 2814 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SECURE 0x0 |
| 2815 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WORD_COUNT 0x1 |
| 2816 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_VAL _MK_MASK
_CONST(0x0) |
| 2817 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_MASK _MK_MASK
_CONST(0xffff) |
| 2818 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2819 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2820 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_READ_MASK _MK_MASK
_CONST(0xffff) |
| 2821 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WRITE_MASK _MK_MASK
_CONST(0xffff) |
| 2822 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT _MK_SHIFT_CONST(
0) |
| 2823 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_FIELD (_MK_MASK_CONST(
0xffff) << APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT) |
| 2824 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_RANGE 15:0 |
| 2825 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_WOFFSET 0x0 |
| 2826 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT _MK_MASK
_CONST(0x0) |
| 2827 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT_MASK _MK_MASK
_CONST(0xffff) |
| 2828 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2829 #define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2830 |
| 2831 |
| 2832 // Register APBDEV_PMC_USB_AO_0 |
| 2833 #define APBDEV_PMC_USB_AO_0 _MK_ADDR_CONST(0xf0) |
| 2834 #define APBDEV_PMC_USB_AO_0_SECURE 0x0 |
| 2835 #define APBDEV_PMC_USB_AO_0_WORD_COUNT 0x1 |
| 2836 #define APBDEV_PMC_USB_AO_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 2837 #define APBDEV_PMC_USB_AO_0_RESET_MASK _MK_MASK_CONST(0xf) |
| 2838 #define APBDEV_PMC_USB_AO_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2839 #define APBDEV_PMC_USB_AO_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2840 #define APBDEV_PMC_USB_AO_0_READ_MASK _MK_MASK_CONST(0xf) |
| 2841 #define APBDEV_PMC_USB_AO_0_WRITE_MASK _MK_MASK_CONST(0xf) |
| 2842 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT _MK_SHIFT_CONST(
0) |
| 2843 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_FIELD (_MK_MASK_CONST(
0x3) << APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT) |
| 2844 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_RANGE 1:0 |
| 2845 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_WOFFSET 0x0 |
| 2846 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT _MK_MASK_CONST(0
x0) |
| 2847 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 2848 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2849 #define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2850 |
| 2851 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT _MK_SHIF
T_CONST(2) |
| 2852 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_FIELD (_MK_MAS
K_CONST(0x3) << APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT) |
| 2853 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_RANGE 3:2 |
| 2854 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_WOFFSET 0x0 |
| 2855 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT _MK_MASK
_CONST(0x0) |
| 2856 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT_MASK _MK_MASK
_CONST(0x3) |
| 2857 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2858 #define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2859 |
| 2860 |
| 2861 // Register APBDEV_PMC_CRYPTO_OP_0 |
| 2862 #define APBDEV_PMC_CRYPTO_OP_0 _MK_ADDR_CONST(0xf4) |
| 2863 #define APBDEV_PMC_CRYPTO_OP_0_SECURE 0x0 |
| 2864 #define APBDEV_PMC_CRYPTO_OP_0_WORD_COUNT 0x1 |
| 2865 #define APBDEV_PMC_CRYPTO_OP_0_RESET_VAL _MK_MASK_CONST(0
x1) |
| 2866 #define APBDEV_PMC_CRYPTO_OP_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 2867 #define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2868 #define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2869 #define APBDEV_PMC_CRYPTO_OP_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 2870 #define APBDEV_PMC_CRYPTO_OP_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 2871 //Disabled by default |
| 2872 #define APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT _MK_SHIFT_CONST(
0) |
| 2873 #define APBDEV_PMC_CRYPTO_OP_0_VAL_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT) |
| 2874 #define APBDEV_PMC_CRYPTO_OP_0_VAL_RANGE 0:0 |
| 2875 #define APBDEV_PMC_CRYPTO_OP_0_VAL_WOFFSET 0x0 |
| 2876 #define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT _MK_MASK_CONST(0
x1) |
| 2877 #define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0
x1) |
| 2878 #define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 2879 #define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2880 #define APBDEV_PMC_CRYPTO_OP_0_VAL_ENABLE _MK_ENUM_CONST(0
) |
| 2881 #define APBDEV_PMC_CRYPTO_OP_0_VAL_DISABLE _MK_ENUM_CONST(1
) |
| 2882 |
| 2883 |
| 2884 // Register APBDEV_PMC_PLLP_WB0_OVERRIDE_0 |
| 2885 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0 _MK_ADDR_CONST(0xf8) |
| 2886 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SECURE 0x0 |
| 2887 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WORD_COUNT 0x1 |
| 2888 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_VAL _MK_MASK
_CONST(0x0) |
| 2889 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_MASK _MK_MASK
_CONST(0xf) |
| 2890 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 2891 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2892 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_READ_MASK _MK_MASK
_CONST(0xf) |
| 2893 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WRITE_MASK _MK_MASK
_CONST(0xf) |
| 2894 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT _MK_SHIF
T_CONST(0) |
| 2895 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_FIELD (_MK_MAS
K_CONST(0xf) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT) |
| 2896 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_RANGE 3:0 |
| 2897 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_WOFFSET 0x0 |
| 2898 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT _MK_MASK
_CONST(0x0) |
| 2899 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT_MASK _MK_MASK
_CONST(0xf) |
| 2900 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2901 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2902 |
| 2903 // 1 = override CAR PLLP setting, 0 = no override. |
| 2904 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT
_MK_SHIFT_CONST(0) |
| 2905 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_FIELD
(_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT) |
| 2906 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_RANGE
0:0 |
| 2907 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_WOFFSET
0x0 |
| 2908 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT
_MK_MASK_CONST(0x0) |
| 2909 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 2910 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2911 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2912 |
| 2913 // 1 = enable PLLP, 0 = disable PLLP. |
| 2914 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT
_MK_SHIFT_CONST(1) |
| 2915 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_FIELD
(_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT) |
| 2916 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_RANGE
1:1 |
| 2917 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WOFFSET
0x0 |
| 2918 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT
_MK_MASK_CONST(0x0) |
| 2919 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 2920 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2921 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2922 |
| 2923 // 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz. |
| 2924 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT _MK_SHIF
T_CONST(2) |
| 2925 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_FIELD (_MK_MAS
K_CONST(0x3) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT) |
| 2926 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_RANGE 3:2 |
| 2927 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_WOFFSET 0x0 |
| 2928 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT _MK_MASK
_CONST(0x0) |
| 2929 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT_MASK
_MK_MASK_CONST(0x3) |
| 2930 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 2931 #define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2932 |
| 2933 |
| 2934 // Register APBDEV_PMC_SCRATCH24_0 // Scratch register |
| 2935 #define APBDEV_PMC_SCRATCH24_0 _MK_ADDR_CONST(0xfc) |
| 2936 #define APBDEV_PMC_SCRATCH24_0_SECURE 0x0 |
| 2937 #define APBDEV_PMC_SCRATCH24_0_WORD_COUNT 0x1 |
| 2938 #define APBDEV_PMC_SCRATCH24_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2939 #define APBDEV_PMC_SCRATCH24_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2940 #define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2941 #define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2942 #define APBDEV_PMC_SCRATCH24_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2943 #define APBDEV_PMC_SCRATCH24_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2944 // General purpose register storage |
| 2945 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT _MK_SHIFT_CONST(
0) |
| 2946 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT) |
| 2947 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_RANGE 31:0 |
| 2948 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_WOFFSET 0x0 |
| 2949 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT _MK_MASK
_CONST(0x0) |
| 2950 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2951 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2952 #define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2953 |
| 2954 |
| 2955 // Register APBDEV_PMC_SCRATCH25_0 // Scratch register |
| 2956 #define APBDEV_PMC_SCRATCH25_0 _MK_ADDR_CONST(0x100) |
| 2957 #define APBDEV_PMC_SCRATCH25_0_SECURE 0x0 |
| 2958 #define APBDEV_PMC_SCRATCH25_0_WORD_COUNT 0x1 |
| 2959 #define APBDEV_PMC_SCRATCH25_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2960 #define APBDEV_PMC_SCRATCH25_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2961 #define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2962 #define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2963 #define APBDEV_PMC_SCRATCH25_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2964 #define APBDEV_PMC_SCRATCH25_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2965 // General purpose register storage |
| 2966 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT _MK_SHIFT_CONST(
0) |
| 2967 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT) |
| 2968 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_RANGE 31:0 |
| 2969 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_WOFFSET 0x0 |
| 2970 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT _MK_MASK
_CONST(0x0) |
| 2971 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2972 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2973 #define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2974 |
| 2975 |
| 2976 // Register APBDEV_PMC_SCRATCH26_0 // Scratch register |
| 2977 #define APBDEV_PMC_SCRATCH26_0 _MK_ADDR_CONST(0x104) |
| 2978 #define APBDEV_PMC_SCRATCH26_0_SECURE 0x0 |
| 2979 #define APBDEV_PMC_SCRATCH26_0_WORD_COUNT 0x1 |
| 2980 #define APBDEV_PMC_SCRATCH26_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 2981 #define APBDEV_PMC_SCRATCH26_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 2982 #define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 2983 #define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 2984 #define APBDEV_PMC_SCRATCH26_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 2985 #define APBDEV_PMC_SCRATCH26_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 2986 // General purpose register storage |
| 2987 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT _MK_SHIFT_CONST(
0) |
| 2988 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT) |
| 2989 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_RANGE 31:0 |
| 2990 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_WOFFSET 0x0 |
| 2991 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT _MK_MASK
_CONST(0x0) |
| 2992 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 2993 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 2994 #define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 2995 |
| 2996 |
| 2997 // Register APBDEV_PMC_SCRATCH27_0 // Scratch register |
| 2998 #define APBDEV_PMC_SCRATCH27_0 _MK_ADDR_CONST(0x108) |
| 2999 #define APBDEV_PMC_SCRATCH27_0_SECURE 0x0 |
| 3000 #define APBDEV_PMC_SCRATCH27_0_WORD_COUNT 0x1 |
| 3001 #define APBDEV_PMC_SCRATCH27_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3002 #define APBDEV_PMC_SCRATCH27_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3003 #define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3004 #define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3005 #define APBDEV_PMC_SCRATCH27_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3006 #define APBDEV_PMC_SCRATCH27_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3007 // General purpose register storage |
| 3008 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT _MK_SHIFT_CONST(
0) |
| 3009 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT) |
| 3010 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_RANGE 31:0 |
| 3011 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_WOFFSET 0x0 |
| 3012 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT _MK_MASK
_CONST(0x0) |
| 3013 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3014 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3015 #define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3016 |
| 3017 |
| 3018 // Register APBDEV_PMC_SCRATCH28_0 // Scratch register |
| 3019 #define APBDEV_PMC_SCRATCH28_0 _MK_ADDR_CONST(0x10c) |
| 3020 #define APBDEV_PMC_SCRATCH28_0_SECURE 0x0 |
| 3021 #define APBDEV_PMC_SCRATCH28_0_WORD_COUNT 0x1 |
| 3022 #define APBDEV_PMC_SCRATCH28_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3023 #define APBDEV_PMC_SCRATCH28_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3024 #define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3025 #define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3026 #define APBDEV_PMC_SCRATCH28_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3027 #define APBDEV_PMC_SCRATCH28_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3028 // General purpose register storage |
| 3029 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT _MK_SHIFT_CONST(
0) |
| 3030 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT) |
| 3031 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_RANGE 31:0 |
| 3032 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_WOFFSET 0x0 |
| 3033 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT _MK_MASK
_CONST(0x0) |
| 3034 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3035 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3036 #define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3037 |
| 3038 |
| 3039 // Register APBDEV_PMC_SCRATCH29_0 // Scratch register |
| 3040 #define APBDEV_PMC_SCRATCH29_0 _MK_ADDR_CONST(0x110) |
| 3041 #define APBDEV_PMC_SCRATCH29_0_SECURE 0x0 |
| 3042 #define APBDEV_PMC_SCRATCH29_0_WORD_COUNT 0x1 |
| 3043 #define APBDEV_PMC_SCRATCH29_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3044 #define APBDEV_PMC_SCRATCH29_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3045 #define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3046 #define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3047 #define APBDEV_PMC_SCRATCH29_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3048 #define APBDEV_PMC_SCRATCH29_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3049 // General purpose register storage |
| 3050 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT _MK_SHIFT_CONST(
0) |
| 3051 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT) |
| 3052 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_RANGE 31:0 |
| 3053 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_WOFFSET 0x0 |
| 3054 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT _MK_MASK
_CONST(0x0) |
| 3055 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3056 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3057 #define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3058 |
| 3059 |
| 3060 // Register APBDEV_PMC_SCRATCH30_0 // Scratch register |
| 3061 #define APBDEV_PMC_SCRATCH30_0 _MK_ADDR_CONST(0x114) |
| 3062 #define APBDEV_PMC_SCRATCH30_0_SECURE 0x0 |
| 3063 #define APBDEV_PMC_SCRATCH30_0_WORD_COUNT 0x1 |
| 3064 #define APBDEV_PMC_SCRATCH30_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3065 #define APBDEV_PMC_SCRATCH30_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3066 #define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3067 #define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3068 #define APBDEV_PMC_SCRATCH30_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3069 #define APBDEV_PMC_SCRATCH30_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3070 // General purpose register storage |
| 3071 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT _MK_SHIFT_CONST(
0) |
| 3072 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT) |
| 3073 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_RANGE 31:0 |
| 3074 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_WOFFSET 0x0 |
| 3075 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT _MK_MASK
_CONST(0x0) |
| 3076 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3077 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3078 #define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3079 |
| 3080 |
| 3081 // Register APBDEV_PMC_SCRATCH31_0 // Scratch register |
| 3082 #define APBDEV_PMC_SCRATCH31_0 _MK_ADDR_CONST(0x118) |
| 3083 #define APBDEV_PMC_SCRATCH31_0_SECURE 0x0 |
| 3084 #define APBDEV_PMC_SCRATCH31_0_WORD_COUNT 0x1 |
| 3085 #define APBDEV_PMC_SCRATCH31_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3086 #define APBDEV_PMC_SCRATCH31_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3087 #define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3088 #define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3089 #define APBDEV_PMC_SCRATCH31_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3090 #define APBDEV_PMC_SCRATCH31_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3091 // General purpose register storage |
| 3092 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT _MK_SHIFT_CONST(
0) |
| 3093 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT) |
| 3094 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_RANGE 31:0 |
| 3095 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_WOFFSET 0x0 |
| 3096 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT _MK_MASK
_CONST(0x0) |
| 3097 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3098 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3099 #define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3100 |
| 3101 |
| 3102 // Register APBDEV_PMC_SCRATCH32_0 // Scratch register |
| 3103 #define APBDEV_PMC_SCRATCH32_0 _MK_ADDR_CONST(0x11c) |
| 3104 #define APBDEV_PMC_SCRATCH32_0_SECURE 0x0 |
| 3105 #define APBDEV_PMC_SCRATCH32_0_WORD_COUNT 0x1 |
| 3106 #define APBDEV_PMC_SCRATCH32_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3107 #define APBDEV_PMC_SCRATCH32_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3108 #define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3109 #define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3110 #define APBDEV_PMC_SCRATCH32_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3111 #define APBDEV_PMC_SCRATCH32_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3112 // General purpose register storage |
| 3113 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT _MK_SHIFT_CONST(
0) |
| 3114 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT) |
| 3115 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_RANGE 31:0 |
| 3116 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_WOFFSET 0x0 |
| 3117 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT _MK_MASK
_CONST(0x0) |
| 3118 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3119 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3120 #define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3121 |
| 3122 |
| 3123 // Register APBDEV_PMC_SCRATCH33_0 // Scratch register |
| 3124 #define APBDEV_PMC_SCRATCH33_0 _MK_ADDR_CONST(0x120) |
| 3125 #define APBDEV_PMC_SCRATCH33_0_SECURE 0x0 |
| 3126 #define APBDEV_PMC_SCRATCH33_0_WORD_COUNT 0x1 |
| 3127 #define APBDEV_PMC_SCRATCH33_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3128 #define APBDEV_PMC_SCRATCH33_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3129 #define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3130 #define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3131 #define APBDEV_PMC_SCRATCH33_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3132 #define APBDEV_PMC_SCRATCH33_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3133 // General purpose register storage |
| 3134 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT _MK_SHIFT_CONST(
0) |
| 3135 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT) |
| 3136 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_RANGE 31:0 |
| 3137 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_WOFFSET 0x0 |
| 3138 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT _MK_MASK
_CONST(0x0) |
| 3139 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3140 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3141 #define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3142 |
| 3143 |
| 3144 // Register APBDEV_PMC_SCRATCH34_0 // Scratch register |
| 3145 #define APBDEV_PMC_SCRATCH34_0 _MK_ADDR_CONST(0x124) |
| 3146 #define APBDEV_PMC_SCRATCH34_0_SECURE 0x0 |
| 3147 #define APBDEV_PMC_SCRATCH34_0_WORD_COUNT 0x1 |
| 3148 #define APBDEV_PMC_SCRATCH34_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3149 #define APBDEV_PMC_SCRATCH34_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3150 #define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3151 #define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3152 #define APBDEV_PMC_SCRATCH34_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3153 #define APBDEV_PMC_SCRATCH34_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3154 // General purpose register storage |
| 3155 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT _MK_SHIFT_CONST(
0) |
| 3156 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT) |
| 3157 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_RANGE 31:0 |
| 3158 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_WOFFSET 0x0 |
| 3159 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT _MK_MASK
_CONST(0x0) |
| 3160 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3161 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3162 #define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3163 |
| 3164 |
| 3165 // Register APBDEV_PMC_SCRATCH35_0 // Scratch register |
| 3166 #define APBDEV_PMC_SCRATCH35_0 _MK_ADDR_CONST(0x128) |
| 3167 #define APBDEV_PMC_SCRATCH35_0_SECURE 0x0 |
| 3168 #define APBDEV_PMC_SCRATCH35_0_WORD_COUNT 0x1 |
| 3169 #define APBDEV_PMC_SCRATCH35_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3170 #define APBDEV_PMC_SCRATCH35_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3171 #define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3172 #define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3173 #define APBDEV_PMC_SCRATCH35_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3174 #define APBDEV_PMC_SCRATCH35_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3175 // General purpose register storage |
| 3176 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT _MK_SHIFT_CONST(
0) |
| 3177 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT) |
| 3178 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_RANGE 31:0 |
| 3179 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_WOFFSET 0x0 |
| 3180 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT _MK_MASK
_CONST(0x0) |
| 3181 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3182 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3183 #define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3184 |
| 3185 |
| 3186 // Register APBDEV_PMC_SCRATCH36_0 // Scratch register |
| 3187 #define APBDEV_PMC_SCRATCH36_0 _MK_ADDR_CONST(0x12c) |
| 3188 #define APBDEV_PMC_SCRATCH36_0_SECURE 0x0 |
| 3189 #define APBDEV_PMC_SCRATCH36_0_WORD_COUNT 0x1 |
| 3190 #define APBDEV_PMC_SCRATCH36_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3191 #define APBDEV_PMC_SCRATCH36_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3192 #define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3193 #define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3194 #define APBDEV_PMC_SCRATCH36_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3195 #define APBDEV_PMC_SCRATCH36_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3196 // General purpose register storage |
| 3197 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT _MK_SHIFT_CONST(
0) |
| 3198 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT) |
| 3199 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_RANGE 31:0 |
| 3200 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_WOFFSET 0x0 |
| 3201 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT _MK_MASK
_CONST(0x0) |
| 3202 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3203 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3204 #define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3205 |
| 3206 |
| 3207 // Register APBDEV_PMC_SCRATCH37_0 // Scratch register |
| 3208 #define APBDEV_PMC_SCRATCH37_0 _MK_ADDR_CONST(0x130) |
| 3209 #define APBDEV_PMC_SCRATCH37_0_SECURE 0x0 |
| 3210 #define APBDEV_PMC_SCRATCH37_0_WORD_COUNT 0x1 |
| 3211 #define APBDEV_PMC_SCRATCH37_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3212 #define APBDEV_PMC_SCRATCH37_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3213 #define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3214 #define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3215 #define APBDEV_PMC_SCRATCH37_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3216 #define APBDEV_PMC_SCRATCH37_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3217 // General purpose register storage |
| 3218 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT _MK_SHIFT_CONST(
0) |
| 3219 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT) |
| 3220 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_RANGE 31:0 |
| 3221 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_WOFFSET 0x0 |
| 3222 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT _MK_MASK
_CONST(0x0) |
| 3223 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3224 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3225 #define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3226 |
| 3227 |
| 3228 // Register APBDEV_PMC_SCRATCH38_0 // Scratch register |
| 3229 #define APBDEV_PMC_SCRATCH38_0 _MK_ADDR_CONST(0x134) |
| 3230 #define APBDEV_PMC_SCRATCH38_0_SECURE 0x0 |
| 3231 #define APBDEV_PMC_SCRATCH38_0_WORD_COUNT 0x1 |
| 3232 #define APBDEV_PMC_SCRATCH38_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3233 #define APBDEV_PMC_SCRATCH38_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3234 #define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3235 #define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3236 #define APBDEV_PMC_SCRATCH38_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3237 #define APBDEV_PMC_SCRATCH38_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3238 // General purpose register storage |
| 3239 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT _MK_SHIFT_CONST(
0) |
| 3240 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT) |
| 3241 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_RANGE 31:0 |
| 3242 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_WOFFSET 0x0 |
| 3243 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT _MK_MASK
_CONST(0x0) |
| 3244 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3245 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3246 #define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3247 |
| 3248 |
| 3249 // Register APBDEV_PMC_SCRATCH39_0 // Scratch register |
| 3250 #define APBDEV_PMC_SCRATCH39_0 _MK_ADDR_CONST(0x138) |
| 3251 #define APBDEV_PMC_SCRATCH39_0_SECURE 0x0 |
| 3252 #define APBDEV_PMC_SCRATCH39_0_WORD_COUNT 0x1 |
| 3253 #define APBDEV_PMC_SCRATCH39_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3254 #define APBDEV_PMC_SCRATCH39_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3255 #define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3256 #define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3257 #define APBDEV_PMC_SCRATCH39_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3258 #define APBDEV_PMC_SCRATCH39_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3259 // General purpose register storage |
| 3260 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT _MK_SHIFT_CONST(
0) |
| 3261 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT) |
| 3262 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_RANGE 31:0 |
| 3263 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_WOFFSET 0x0 |
| 3264 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT _MK_MASK
_CONST(0x0) |
| 3265 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3266 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3267 #define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3268 |
| 3269 |
| 3270 // Register APBDEV_PMC_SCRATCH40_0 // Scratch register |
| 3271 #define APBDEV_PMC_SCRATCH40_0 _MK_ADDR_CONST(0x13c) |
| 3272 #define APBDEV_PMC_SCRATCH40_0_SECURE 0x0 |
| 3273 #define APBDEV_PMC_SCRATCH40_0_WORD_COUNT 0x1 |
| 3274 #define APBDEV_PMC_SCRATCH40_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3275 #define APBDEV_PMC_SCRATCH40_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3276 #define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3277 #define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3278 #define APBDEV_PMC_SCRATCH40_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3279 #define APBDEV_PMC_SCRATCH40_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3280 // General purpose register storage |
| 3281 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT _MK_SHIFT_CONST(
0) |
| 3282 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT) |
| 3283 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_RANGE 31:0 |
| 3284 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_WOFFSET 0x0 |
| 3285 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT _MK_MASK
_CONST(0x0) |
| 3286 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3287 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3288 #define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3289 |
| 3290 |
| 3291 // Register APBDEV_PMC_SCRATCH41_0 // Scratch register |
| 3292 #define APBDEV_PMC_SCRATCH41_0 _MK_ADDR_CONST(0x140) |
| 3293 #define APBDEV_PMC_SCRATCH41_0_SECURE 0x0 |
| 3294 #define APBDEV_PMC_SCRATCH41_0_WORD_COUNT 0x1 |
| 3295 #define APBDEV_PMC_SCRATCH41_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3296 #define APBDEV_PMC_SCRATCH41_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3297 #define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3298 #define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3299 #define APBDEV_PMC_SCRATCH41_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3300 #define APBDEV_PMC_SCRATCH41_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3301 // General purpose register storage |
| 3302 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT _MK_SHIFT_CONST(
0) |
| 3303 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT) |
| 3304 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_RANGE 31:0 |
| 3305 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_WOFFSET 0x0 |
| 3306 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT _MK_MASK
_CONST(0x0) |
| 3307 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3308 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3309 #define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3310 |
| 3311 |
| 3312 // Register APBDEV_PMC_SCRATCH42_0 // Scratch register |
| 3313 #define APBDEV_PMC_SCRATCH42_0 _MK_ADDR_CONST(0x144) |
| 3314 #define APBDEV_PMC_SCRATCH42_0_SECURE 0x0 |
| 3315 #define APBDEV_PMC_SCRATCH42_0_WORD_COUNT 0x1 |
| 3316 #define APBDEV_PMC_SCRATCH42_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3317 #define APBDEV_PMC_SCRATCH42_0_RESET_MASK _MK_MASK_CONST(0
x0) |
| 3318 #define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3319 #define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3320 #define APBDEV_PMC_SCRATCH42_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3321 #define APBDEV_PMC_SCRATCH42_0_WRITE_MASK _MK_MASK_CONST(0
xffffffff) |
| 3322 // General purpose register storage |
| 3323 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT _MK_SHIFT_CONST(
0) |
| 3324 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_FIELD (_MK_MASK_CONST(
0xffffffff) << APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT) |
| 3325 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_RANGE 31:0 |
| 3326 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_WOFFSET 0x0 |
| 3327 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT _MK_MASK
_CONST(0x0) |
| 3328 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3329 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT _MK_MASK
_CONST(0x0) |
| 3330 #define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3331 |
| 3332 |
| 3333 // Register APBDEV_PMC_BONDOUT_MIRROR0_0 // Secure scratch register |
| 3334 #define APBDEV_PMC_BONDOUT_MIRROR0_0 _MK_ADDR_CONST(0x148) |
| 3335 #define APBDEV_PMC_BONDOUT_MIRROR0_0_SECURE 0x0 |
| 3336 #define APBDEV_PMC_BONDOUT_MIRROR0_0_WORD_COUNT 0x1 |
| 3337 #define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3338 #define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 3339 #define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 3340 #define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3341 #define APBDEV_PMC_BONDOUT_MIRROR0_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3342 #define APBDEV_PMC_BONDOUT_MIRROR0_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 3343 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIFT
_MK_SHIFT_CONST(0) |
| 3344 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIF
T) |
| 3345 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_RANGE
31:0 |
| 3346 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_WOFFSET
0x0 |
| 3347 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT
_MK_MASK_CONST(0x0) |
| 3348 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3349 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 3350 #define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3351 |
| 3352 |
| 3353 // Register APBDEV_PMC_BONDOUT_MIRROR1_0 // Secure scratch register |
| 3354 #define APBDEV_PMC_BONDOUT_MIRROR1_0 _MK_ADDR_CONST(0x14c) |
| 3355 #define APBDEV_PMC_BONDOUT_MIRROR1_0_SECURE 0x0 |
| 3356 #define APBDEV_PMC_BONDOUT_MIRROR1_0_WORD_COUNT 0x1 |
| 3357 #define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3358 #define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 3359 #define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 3360 #define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3361 #define APBDEV_PMC_BONDOUT_MIRROR1_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3362 #define APBDEV_PMC_BONDOUT_MIRROR1_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 3363 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIFT
_MK_SHIFT_CONST(0) |
| 3364 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIF
T) |
| 3365 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_RANGE
31:0 |
| 3366 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_WOFFSET
0x0 |
| 3367 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT
_MK_MASK_CONST(0x0) |
| 3368 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3369 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 3370 #define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3371 |
| 3372 |
| 3373 // Register APBDEV_PMC_BONDOUT_MIRROR2_0 // Secure scratch register |
| 3374 #define APBDEV_PMC_BONDOUT_MIRROR2_0 _MK_ADDR_CONST(0x150) |
| 3375 #define APBDEV_PMC_BONDOUT_MIRROR2_0_SECURE 0x0 |
| 3376 #define APBDEV_PMC_BONDOUT_MIRROR2_0_WORD_COUNT 0x1 |
| 3377 #define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3378 #define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_MASK _MK_MASK
_CONST(0x0) |
| 3379 #define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_VAL _MK_MASK
_CONST(0x0) |
| 3380 #define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3381 #define APBDEV_PMC_BONDOUT_MIRROR2_0_READ_MASK _MK_MASK_CONST(0
xffffffff) |
| 3382 #define APBDEV_PMC_BONDOUT_MIRROR2_0_WRITE_MASK _MK_MASK
_CONST(0xffffffff) |
| 3383 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIFT
_MK_SHIFT_CONST(0) |
| 3384 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_FIELD
(_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIF
T) |
| 3385 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_RANGE
31:0 |
| 3386 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_WOFFSET
0x0 |
| 3387 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT
_MK_MASK_CONST(0x0) |
| 3388 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3389 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 3390 #define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3391 |
| 3392 |
| 3393 // Register APBDEV_PMC_SYS_33V_EN_0 |
| 3394 #define APBDEV_PMC_SYS_33V_EN_0 _MK_ADDR_CONST(0x154) |
| 3395 #define APBDEV_PMC_SYS_33V_EN_0_SECURE 0x0 |
| 3396 #define APBDEV_PMC_SYS_33V_EN_0_WORD_COUNT 0x1 |
| 3397 #define APBDEV_PMC_SYS_33V_EN_0_RESET_VAL _MK_MASK_CONST(0
x0) |
| 3398 #define APBDEV_PMC_SYS_33V_EN_0_RESET_MASK _MK_MASK_CONST(0
x1) |
| 3399 #define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3400 #define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3401 #define APBDEV_PMC_SYS_33V_EN_0_READ_MASK _MK_MASK_CONST(0
x1) |
| 3402 #define APBDEV_PMC_SYS_33V_EN_0_WRITE_MASK _MK_MASK_CONST(0
x1) |
| 3403 // 1 - 3.3v, 0 - 1.8v |
| 3404 #define APBDEV_PMC_SYS_33V_EN_0_val_SHIFT _MK_SHIFT_CONST(
0) |
| 3405 #define APBDEV_PMC_SYS_33V_EN_0_val_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_SYS_33V_EN_0_val_SHIFT) |
| 3406 #define APBDEV_PMC_SYS_33V_EN_0_val_RANGE 0:0 |
| 3407 #define APBDEV_PMC_SYS_33V_EN_0_val_WOFFSET 0x0 |
| 3408 #define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT _MK_MASK_CONST(0
x0) |
| 3409 #define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 3410 #define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 3411 #define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3412 |
| 3413 |
| 3414 // Register APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0 |
| 3415 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0 _MK_ADDR_CONST(0
x158) |
| 3416 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SECURE 0x0 |
| 3417 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WORD_COUNT 0x1 |
| 3418 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_VAL _MK_MASK
_CONST(0x0) |
| 3419 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_MASK _MK_MASK
_CONST(0x3) |
| 3420 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_VAL
_MK_MASK_CONST(0x0) |
| 3421 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3422 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_READ_MASK _MK_MASK
_CONST(0x3) |
| 3423 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WRITE_MASK _MK_MASK
_CONST(0x3) |
| 3424 // disable write to bondout secure registers |
| 3425 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT _MK_SHIF
T_CONST(0) |
| 3426 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT) |
| 3427 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_RANGE 0:0 |
| 3428 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_WOFFSET
0x0 |
| 3429 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT
_MK_MASK_CONST(0x0) |
| 3430 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 3431 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 3432 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3433 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_OFF _MK_ENUM
_CONST(0) |
| 3434 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_ON _MK_ENUM
_CONST(1) |
| 3435 |
| 3436 // disable read from bondout secure registers |
| 3437 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT _MK_SHIF
T_CONST(1) |
| 3438 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_FIELD (_MK_MAS
K_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT) |
| 3439 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_RANGE 1:1 |
| 3440 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_WOFFSET
0x0 |
| 3441 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT
_MK_MASK_CONST(0x0) |
| 3442 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT_MASK
_MK_MASK_CONST(0x1) |
| 3443 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT
_MK_MASK_CONST(0x0) |
| 3444 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT_MASK
_MK_MASK_CONST(0x0) |
| 3445 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_OFF _MK_ENUM
_CONST(0) |
| 3446 #define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_ON _MK_ENUM
_CONST(1) |
| 3447 |
| 3448 |
| 3449 // Register APBDEV_PMC_GATE_0 |
| 3450 #define APBDEV_PMC_GATE_0 _MK_ADDR_CONST(0x15c) |
| 3451 #define APBDEV_PMC_GATE_0_SECURE 0x0 |
| 3452 #define APBDEV_PMC_GATE_0_WORD_COUNT 0x1 |
| 3453 #define APBDEV_PMC_GATE_0_RESET_VAL _MK_MASK_CONST(0x0) |
| 3454 #define APBDEV_PMC_GATE_0_RESET_MASK _MK_MASK_CONST(0x1) |
| 3455 #define APBDEV_PMC_GATE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0
x0) |
| 3456 #define APBDEV_PMC_GATE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0
x0) |
| 3457 #define APBDEV_PMC_GATE_0_READ_MASK _MK_MASK_CONST(0x1) |
| 3458 #define APBDEV_PMC_GATE_0_WRITE_MASK _MK_MASK_CONST(0x1) |
| 3459 #define APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT _MK_SHIFT_CONST(
0) |
| 3460 #define APBDEV_PMC_GATE_0_GATE_WAKE_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT) |
| 3461 #define APBDEV_PMC_GATE_0_GATE_WAKE_RANGE 0:0 |
| 3462 #define APBDEV_PMC_GATE_0_GATE_WAKE_WOFFSET 0x0 |
| 3463 #define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT _MK_MASK_CONST(0
x0) |
| 3464 #define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 3465 #define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 3466 #define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3467 #define APBDEV_PMC_GATE_0_GATE_WAKE_OFF _MK_ENUM_CONST(0) |
| 3468 #define APBDEV_PMC_GATE_0_GATE_WAKE_ON _MK_ENUM_CONST(1) |
| 3469 |
| 3470 #define APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT _MK_SHIFT_CONST(
0) |
| 3471 #define APBDEV_PMC_GATE_0_GATE_DBNS_FIELD (_MK_MASK_CONST(
0x1) << APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT) |
| 3472 #define APBDEV_PMC_GATE_0_GATE_DBNS_RANGE 0:0 |
| 3473 #define APBDEV_PMC_GATE_0_GATE_DBNS_WOFFSET 0x0 |
| 3474 #define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT _MK_MASK_CONST(0
x0) |
| 3475 #define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT_MASK _MK_MASK
_CONST(0x1) |
| 3476 #define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT _MK_MASK_CONST(0
x0) |
| 3477 #define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT_MASK _MK_MASK
_CONST(0x0) |
| 3478 #define APBDEV_PMC_GATE_0_GATE_DBNS_OFF _MK_ENUM_CONST(0) |
| 3479 #define APBDEV_PMC_GATE_0_GATE_DBNS_ON _MK_ENUM_CONST(1) |
| 3480 |
| 3481 |
| 3482 // |
| 3483 // REGISTER LIST |
| 3484 // |
| 3485 #define LIST_ARAPBPM_REGS(_op_) \ |
| 3486 _op_(APBDEV_PMC_CNTRL_0) \ |
| 3487 _op_(APBDEV_PMC_SEC_DISABLE_0) \ |
| 3488 _op_(APBDEV_PMC_PMC_SWRST_0) \ |
| 3489 _op_(APBDEV_PMC_WAKE_MASK_0) \ |
| 3490 _op_(APBDEV_PMC_WAKE_LVL_0) \ |
| 3491 _op_(APBDEV_PMC_WAKE_STATUS_0) \ |
| 3492 _op_(APBDEV_PMC_SW_WAKE_STATUS_0) \ |
| 3493 _op_(APBDEV_PMC_DPD_PADS_ORIDE_0) \ |
| 3494 _op_(APBDEV_PMC_DPD_SAMPLE_0) \ |
| 3495 _op_(APBDEV_PMC_DPD_ENABLE_0) \ |
| 3496 _op_(APBDEV_PMC_PWRGATE_TIMER_OFF_0) \ |
| 3497 _op_(APBDEV_PMC_PWRGATE_TIMER_ON_0) \ |
| 3498 _op_(APBDEV_PMC_PWRGATE_TOGGLE_0) \ |
| 3499 _op_(APBDEV_PMC_REMOVE_CLAMPING_CMD_0) \ |
| 3500 _op_(APBDEV_PMC_PWRGATE_STATUS_0) \ |
| 3501 _op_(APBDEV_PMC_PWRGOOD_TIMER_0) \ |
| 3502 _op_(APBDEV_PMC_BLINK_TIMER_0) \ |
| 3503 _op_(APBDEV_PMC_NO_IOPOWER_0) \ |
| 3504 _op_(APBDEV_PMC_PWR_DET_0) \ |
| 3505 _op_(APBDEV_PMC_PWR_DET_LATCH_0) \ |
| 3506 _op_(APBDEV_PMC_SCRATCH0_0) \ |
| 3507 _op_(APBDEV_PMC_SCRATCH1_0) \ |
| 3508 _op_(APBDEV_PMC_SCRATCH2_0) \ |
| 3509 _op_(APBDEV_PMC_SCRATCH3_0) \ |
| 3510 _op_(APBDEV_PMC_SCRATCH4_0) \ |
| 3511 _op_(APBDEV_PMC_SCRATCH5_0) \ |
| 3512 _op_(APBDEV_PMC_SCRATCH6_0) \ |
| 3513 _op_(APBDEV_PMC_SCRATCH7_0) \ |
| 3514 _op_(APBDEV_PMC_SCRATCH8_0) \ |
| 3515 _op_(APBDEV_PMC_SCRATCH9_0) \ |
| 3516 _op_(APBDEV_PMC_SCRATCH10_0) \ |
| 3517 _op_(APBDEV_PMC_SCRATCH11_0) \ |
| 3518 _op_(APBDEV_PMC_SCRATCH12_0) \ |
| 3519 _op_(APBDEV_PMC_SCRATCH13_0) \ |
| 3520 _op_(APBDEV_PMC_SCRATCH14_0) \ |
| 3521 _op_(APBDEV_PMC_SCRATCH15_0) \ |
| 3522 _op_(APBDEV_PMC_SCRATCH16_0) \ |
| 3523 _op_(APBDEV_PMC_SCRATCH17_0) \ |
| 3524 _op_(APBDEV_PMC_SCRATCH18_0) \ |
| 3525 _op_(APBDEV_PMC_SCRATCH19_0) \ |
| 3526 _op_(APBDEV_PMC_SCRATCH20_0) \ |
| 3527 _op_(APBDEV_PMC_SCRATCH21_0) \ |
| 3528 _op_(APBDEV_PMC_SCRATCH22_0) \ |
| 3529 _op_(APBDEV_PMC_SCRATCH23_0) \ |
| 3530 _op_(APBDEV_PMC_SECURE_SCRATCH0_0) \ |
| 3531 _op_(APBDEV_PMC_SECURE_SCRATCH1_0) \ |
| 3532 _op_(APBDEV_PMC_SECURE_SCRATCH2_0) \ |
| 3533 _op_(APBDEV_PMC_SECURE_SCRATCH3_0) \ |
| 3534 _op_(APBDEV_PMC_SECURE_SCRATCH4_0) \ |
| 3535 _op_(APBDEV_PMC_SECURE_SCRATCH5_0) \ |
| 3536 _op_(APBDEV_PMC_CPUPWRGOOD_TIMER_0) \ |
| 3537 _op_(APBDEV_PMC_CPUPWROFF_TIMER_0) \ |
| 3538 _op_(APBDEV_PMC_PG_MASK_0) \ |
| 3539 _op_(APBDEV_PMC_PG_MASK_1_0) \ |
| 3540 _op_(APBDEV_PMC_AUTO_WAKE_LVL_0) \ |
| 3541 _op_(APBDEV_PMC_AUTO_WAKE_LVL_MASK_0) \ |
| 3542 _op_(APBDEV_PMC_WAKE_DELAY_0) \ |
| 3543 _op_(APBDEV_PMC_PWR_DET_VAL_0) \ |
| 3544 _op_(APBDEV_PMC_DDR_PWR_0) \ |
| 3545 _op_(APBDEV_PMC_USB_DEBOUNCE_DEL_0) \ |
| 3546 _op_(APBDEV_PMC_USB_AO_0) \ |
| 3547 _op_(APBDEV_PMC_CRYPTO_OP_0) \ |
| 3548 _op_(APBDEV_PMC_PLLP_WB0_OVERRIDE_0) \ |
| 3549 _op_(APBDEV_PMC_SCRATCH24_0) \ |
| 3550 _op_(APBDEV_PMC_SCRATCH25_0) \ |
| 3551 _op_(APBDEV_PMC_SCRATCH26_0) \ |
| 3552 _op_(APBDEV_PMC_SCRATCH27_0) \ |
| 3553 _op_(APBDEV_PMC_SCRATCH28_0) \ |
| 3554 _op_(APBDEV_PMC_SCRATCH29_0) \ |
| 3555 _op_(APBDEV_PMC_SCRATCH30_0) \ |
| 3556 _op_(APBDEV_PMC_SCRATCH31_0) \ |
| 3557 _op_(APBDEV_PMC_SCRATCH32_0) \ |
| 3558 _op_(APBDEV_PMC_SCRATCH33_0) \ |
| 3559 _op_(APBDEV_PMC_SCRATCH34_0) \ |
| 3560 _op_(APBDEV_PMC_SCRATCH35_0) \ |
| 3561 _op_(APBDEV_PMC_SCRATCH36_0) \ |
| 3562 _op_(APBDEV_PMC_SCRATCH37_0) \ |
| 3563 _op_(APBDEV_PMC_SCRATCH38_0) \ |
| 3564 _op_(APBDEV_PMC_SCRATCH39_0) \ |
| 3565 _op_(APBDEV_PMC_SCRATCH40_0) \ |
| 3566 _op_(APBDEV_PMC_SCRATCH41_0) \ |
| 3567 _op_(APBDEV_PMC_SCRATCH42_0) \ |
| 3568 _op_(APBDEV_PMC_BONDOUT_MIRROR0_0) \ |
| 3569 _op_(APBDEV_PMC_BONDOUT_MIRROR1_0) \ |
| 3570 _op_(APBDEV_PMC_BONDOUT_MIRROR2_0) \ |
| 3571 _op_(APBDEV_PMC_SYS_33V_EN_0) \ |
| 3572 _op_(APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0) \ |
| 3573 _op_(APBDEV_PMC_GATE_0) |
| 3574 |
| 3575 |
| 3576 // |
| 3577 // ADDRESS SPACES |
| 3578 // |
| 3579 |
| 3580 #define BASE_ADDRESS_APBDEV_PMC 0x00000000 |
| 3581 |
| 3582 // |
| 3583 // ARAPBPM REGISTER BANKS |
| 3584 // |
| 3585 |
| 3586 #define APBDEV_PMC0_FIRST_REG 0x0000 // APBDEV_PMC_CNTRL_0 |
| 3587 #define APBDEV_PMC0_LAST_REG 0x015c // APBDEV_PMC_GATE_0 |
| 3588 |
| 3589 #ifndef _MK_SHIFT_CONST |
| 3590 #define _MK_SHIFT_CONST(_constant_) _constant_ |
| 3591 #endif |
| 3592 #ifndef _MK_MASK_CONST |
| 3593 #define _MK_MASK_CONST(_constant_) _constant_ |
| 3594 #endif |
| 3595 #ifndef _MK_ENUM_CONST |
| 3596 #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) |
| 3597 #endif |
| 3598 #ifndef _MK_ADDR_CONST |
| 3599 #define _MK_ADDR_CONST(_constant_) _constant_ |
| 3600 #endif |
| 3601 |
| 3602 #endif // ifndef ___ARAPBPM_H_INC_ |
| OLD | NEW |
|---|
Chromium Code Reviews
Issue 3256004:
[ARM] tegra: add nvos/nvrm/nvmap drivers (Closed)
Base URL: ssh://git@gitrw.chromium.org/kernel.git