ARM: add AArch32 support and new vcvt instructions

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index 540c4014cde7a36fb2b8362f699ce35c6589fefe..e4f7a6597d3025b03fb7941d0f97a97e85db00fd 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1617,6 +1617,39 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
         Unknown(instr);
       }
       break;
+    case 0x1D:
+      if ((instr->Bits(21, 18) == 0xF) && (instr->Bits(11, 9) == 5) &&
+          (instr->Bit(6) == 1) && (instr->Bit(4) == 0)) {
+        // AArch32 vcvt instructions.
+        int size = instr->Bit(8);
+        int Vd = instr->VFPDRegValue(kSinglePrecision);
+        int Vm = instr->VFPMRegValue(static_cast<VFPRegPrecision>(size));
+        int rounding_mode = instr->Bits(17, 16);
+        int data_type = instr->Bit(7);
+        char rounding_name;
+        switch (rounding_mode) {
+          case kVcvtTiesToAway: rounding_name = 'a'; break;
+          case kVcvtTiesToEven: rounding_name = 'n'; break;
+          case kVcvtTowardPlusInfinity: rounding_name = 'p'; break;
+          case kVcvtTowardMinusInfinity: rounding_name = 'm'; break;
+          default: UNREACHABLE();
+        }
+        char data_name = (data_type == 0) ? 'u' : 's';
+        if (size == 0) {
+          out_buffer_pos_ +=
+              OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                           "vcvt%c.%c32.f32 s%d, s%d", rounding_name, data_name,
+                           Vd, Vm);
+        } else {
+          out_buffer_pos_ +=
+              OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                           "vcvt%c.%c32.f64 s%d, d%d", rounding_name, data_name,
+                           Vd, Vm);
+        }
+      } else {
+        Unknown(instr);
+      }
+      break;
     default:
       Unknown(instr);
       break;