ARM: add AArch32 support and new vcvt instructions

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1599 matching lines @@
           out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                           "pld [r%d, #-%d]", Rn, offset);
         } else {
           out_buffer_pos_ += OS::SNPrintF(out_buffer_ + out_buffer_pos_,
                                           "pld [r%d, #+%d]", Rn, offset);
         }
       } else {
         Unknown(instr);
       }
       break;
+    case 0x1D:
+      if ((instr->Bits(21, 18) == 0xF) && (instr->Bits(11, 9) == 5) &&
+          (instr->Bit(6) == 1) && (instr->Bit(4) == 0)) {
+        // AArch32 vcvt instructions.
+        int size = instr->Bit(8);
+        int Vd = instr->VFPDRegValue(kSinglePrecision);
+        int Vm = instr->VFPMRegValue(static_cast<VFPRegPrecision>(size));
+        int rounding_mode = instr->Bits(17, 16);
+        int data_type = instr->Bit(7);
+        char rounding_name;
+        switch (rounding_mode) {
+          case kVcvtTiesToAway: rounding_name = 'a'; break;
+          case kVcvtTiesToEven: rounding_name = 'n'; break;
+          case kVcvtTowardPlusInfinity: rounding_name = 'p'; break;
+          case kVcvtTowardMinusInfinity: rounding_name = 'm'; break;
+          default: UNREACHABLE();
+        }
+        char data_name = (data_type == 0) ? 'u' : 's';
+        if (size == 0) {
+          out_buffer_pos_ +=
+              OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                           "vcvt%c.%c32.f32 s%d, s%d", rounding_name, data_name,
+                           Vd, Vm);
+        } else {
+          out_buffer_pos_ +=
+              OS::SNPrintF(out_buffer_ + out_buffer_pos_,
+                           "vcvt%c.%c32.f64 s%d, d%d", rounding_name, data_name,
+                           Vd, Vm);
+        }
+      } else {
+        Unknown(instr);
+      }
+      break;
     default:
       Unknown(instr);
       break;
   }
 }
 
 #undef VERIFIY
 
 bool Decoder::IsConstantPoolAt(byte* instr_ptr) {
   int instruction_bits = *(reinterpret_cast<int*>(instr_ptr));
@@ skipping 152 matching lines @@
     v8::internal::PrintF(
         f, "%p    %08x      %s\n",
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM