Add a few Subzero intrinsics (not the atomic ones yet).

src/IceInstX8632.def

Index: src/IceInstX8632.def
diff --git a/src/IceInstX8632.def b/src/IceInstX8632.def
index d5e99c30afa51723461a595ac9835a909d1fad71..491a0b5139e8716dfc1d0e5f2a3f02f06103c7a1 100644
--- a/src/IceInstX8632.def
+++ b/src/IceInstX8632.def
@@ -38,6 +38,16 @@
 //#define X(val, init, name, name16, name8, scratch, preserved, stackptr,
 //          frameptr, isI8, isInt, isFP)
 
+// X86 segment registers.
+#define SEG_REGX8632_TABLE  \
+  /* enum value, name */    \
+  X(Reg_CS, "cs")           \

[Jim Stichnoth, 2014/06/12 20:52:07]

Maybe we could use a prefix other than "Reg_" for the enum values?  Just to
convey the fact that segment registers are a very different register class than
the other Reg_* registers, e.g. segment registers can't be used for register
allocation.

I'd suggest Sreg_ or SegReg_, and be consistent with SegReg_NUM (which could
mean renaming this to Sreg_NUM).

[jvoung (off chromium), 2014/06/16 20:51:59]

Changing to SegReg_ (and matches the table's name SEG_REG)

+  X(Reg_DS, "ds")           \
+  X(Reg_ES, "es")           \
+  X(Reg_SS, "ss")           \
+  X(Reg_FS, "fs")           \
+  X(Reg_GS, "gs")           \
+//#define X(val, name)
 
 #define ICEINSTX8632BR_TABLE   \
   /* enum value, dump, emit */ \