Add a few Subzero intrinsics (not the atomic ones yet).

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 740 matching lines @@
     split64(Var);
     return Var->getLo();
   }
   if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
     uint64_t Mask = (1ull << 32) - 1;
     return Ctx->getConstantInt(IceType_i32, Const->getValue() & Mask);
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(),
                                    Mem->getOffset(), Mem->getIndex(),
-                                   Mem->getShift());
+                                   Mem->getShift(), Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
   return NULL;
 }
 
 Operand *TargetX8632::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
   if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getHi();
   }
   if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
     return Ctx->getConstantInt(IceType_i32, Const->getValue() >> 32);
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     Constant *Offset = Mem->getOffset();
     if (Offset == NULL)
       Offset = Ctx->getConstantInt(IceType_i32, 4);
     else if (ConstantInteger *IntOffset =
                  llvm::dyn_cast<ConstantInteger>(Offset)) {
       Offset = Ctx->getConstantInt(IceType_i32, 4 + IntOffset->getValue());
     } else if (ConstantRelocatable *SymOffset =
                    llvm::dyn_cast<ConstantRelocatable>(Offset)) {
       Offset = Ctx->getConstantSym(IceType_i32, 4 + SymOffset->getOffset(),
                                    SymOffset->getName());
     }
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(), Offset,
-                                   Mem->getIndex(), Mem->getShift());
+                                   Mem->getIndex(), Mem->getShift(),
+                                   Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
   return NULL;
 }
 
 llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(Reg_NUM);
 
 #define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
@@ skipping 955 matching lines @@
       legalize(Src0, IsSrc1ImmOrReg ? Legal_All : Legal_Reg, true);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
   _cmp(Src0New, Src1);
   _mov(Dest, One);
   _br(getIcmp32Mapping(Inst->getCondition()), Label);
   Context.insert(InstFakeUse::create(Func, Dest));
   _mov(Dest, Zero);
   Context.insert(Label);
 }
 
+void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
+  switch (Instr->getIntrinsicInfo().ID) {
+    case AtomicCmpxchg:
+    case AtomicFence:
+    case AtomicFenceAll:
+    case AtomicIsLockFree:
+    case AtomicLoad:
+    case AtomicRMW:
+    case AtomicStore:
+    case Bswap:
+    case Ctlz:
+    case Ctpop:
+    case Cttz:
+      Func->setError("Unhandled intrinsic");
+      return;
+    case Longjmp: {
+      InstCall *Call = makeHelperCall("longjmp", NULL, 2);
+      Call->addArg(Instr->getSrc(1));
+      Call->addArg(Instr->getSrc(2));
+      lowerCall(Call);
+      break;
+    }
+    case Memcpy: {
+      // In the future, we could potentially emit an inline memcpy/memset, etc.
+      // for intrinsic calls w/ a known length.
+      InstCall *Call = makeHelperCall("memcpy", NULL, 3);
+      Call->addArg(Instr->getSrc(1));
+      Call->addArg(Instr->getSrc(2));
+      Call->addArg(Instr->getSrc(3));
+      lowerCall(Call);
+      break;
+    }
+    case Memmove: {
+      InstCall *Call = makeHelperCall("memmove", NULL, 3);
+      Call->addArg(Instr->getSrc(1));
+      Call->addArg(Instr->getSrc(2));
+      Call->addArg(Instr->getSrc(3));
+      lowerCall(Call);
+      break;
+    }
+    case Memset: {
+      InstCall *Call = makeHelperCall("memset", NULL, 3);
+      Call->addArg(Instr->getSrc(1));
+      Call->addArg(Instr->getSrc(2));

[jvoung (off chromium), 2014/06/12 05:48:30]

Should this code be responsible for "widening" the type to a stack slot size? W/
intrinsics, we can violate the rule that PNaCl function parameters are at least
i32 =(

I believe I ran into a .s file attempting to "push byte ptr [...]" which isn't
allowed. Will have to check again.

[Jim Stichnoth, 2014/06/12 17:04:44]

The Subzero lowering code assumes the simplification pass that widens i1/i8/i16
function args and return values to i32.  If this hasn't happened for some
intrinsics, then yeah, we'll probably end up with illegal push or other
instructions.

It would probably be best to fix this up on a per-arg basis in lowerCall(), and
even better if there's a clean way to fix-up for specific intrinsics and assert
for everything else.

[jvoung (off chromium), 2014/06/16 20:51:58]

Added a movzx for this case.

Was going to add a debug assert in InstX8632Push::emit, but looks like some
tests currently don't handle that yet?

====

Assert from push::emit:

${FOO}/toolchain_build/src/subzero/llvm2ice -O2 --verbose none
${FOO}/toolchain_build/src/subzero/tests_lit/llvm2ice_tests/cmp-opt.ll -o - |
llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj -o=MyObj.o  -

<stdin>:27:7: error: invalid operand for instruction
        push    dl
                ^~
<stdin>:37:7: error: invalid operand for instruction
        push    bl
                ^~

=====

Assert from lowerCall:

${FOO}/toolchain_build/src/subzero/llvm2ice -O2 --verbose none
${FOO}/toolchain_build/src/subzero/tests_lit/llvm2ice_tests/bool-opt.ll -o - |
llvm-mc -arch=x86 -x86-asm-syntax=intel -filetype=obj -o=MyObj.o  -
<stdin>:16:7: error: invalid operand for instruction
        push    al
                ^~
	call	use

[Jim Stichnoth, 2014/06/16 23:05:15]

Hmm, looks like those two tests are not valid PNaCl bitcode since their use()
function is declared to take an i1 arg. :(

[jvoung (off chromium), 2014/06/17 17:36:18]

Ah right, I should have looked at what the test was doing =)

I'll send a separate fix for the tests.

+      Call->addArg(Instr->getSrc(3));
+      lowerCall(Call);
+      break;
+    }
+    case NaClReadTP: {
+      Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+      Operand *Src = OperandX8632Mem::create(
+          Func, IceType_i32, NULL, Zero, NULL, 0,
+          OperandX8632Mem::Reg_GS);
+      Variable *Dest = Instr->getDest();
+      Variable *T = NULL;
+      _mov(T, Src);
+      _mov(Dest, T);
+      break;
+    }
+    case Setjmp: {
+      InstCall *Call = makeHelperCall("setjmp", Instr->getDest(), 1);
+      Call->addArg(Instr->getSrc(1));
+      lowerCall(Call);
+      break;
+    }
+    case Sqrt:
+    case Stacksave:
+    case Stackrestore:
+      Func->setError("Unhandled intrinsic");
+      return;
+    case Trap:
+      _ud2();
+      break;
+    case UnknownIntrinsic:
+      Func->setError("Should not be lowering UnknownIntrinsic");
+      return;
+  }
+  return;
+}
+
 namespace {
 
 bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
 }
 
-void computeAddressOpt(Variable *&Base, Variable *&Index, int32_t &Shift,
+void computeAddressOpt(Variable *&Base, Variable *&Index, uint16_t &Shift,
                        int32_t &Offset) {
   (void)Offset; // TODO: pattern-match for non-zero offsets.
   if (Base == NULL)
     return;
   // If the Base has more than one use or is live across multiple
   // blocks, then don't go further.  Alternatively (?), never consider
   // a transformation that would change a variable that is currently
   // *not* live across basic block boundaries into one that *is*.
   if (Base->isMultiblockLife() /* || Base->getUseCount() > 1*/)
     return;
@@ skipping 160 matching lines @@
 
   InstAssign *Assign = InstAssign::create(Func, Inst->getDest(), Src0);
   lowerAssign(Assign);
 }
 
 void TargetX8632::doAddressOptLoad() {
   Inst *Inst = *Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = NULL;
-  int32_t Shift = 0;
+  uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
+  // At the ICE level, load instructions should not use the
+  // segment registers, and computeAddressOpt only works at the level
+  // of Variables and Constants, not other OperandX8632Mem, so there
+  // should be no mention of segment registers there either.
+  OperandX8632Mem::SegmentRegisters SegmentReg =
+      OperandX8632Mem::DefaultSegment;
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   computeAddressOpt(Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Constant *OffsetOp = Ctx->getConstantInt(IceType_i32, Offset);
     Addr = OperandX8632Mem::create(Func, Dest->getType(), Base, OffsetOp, Index,
-                                   Shift);
+                                   Shift, SegmentReg);
     Inst->setDeleted();
     Context.insert(InstLoad::create(Func, Dest, Addr));
   }
 }
 
 void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
@@ skipping 88 matching lines @@
     Value = legalize(Value, Legal_Reg | Legal_Imm, true);
     _store(Value, NewAddr);
   }
 }
 
 void TargetX8632::doAddressOptStore() {
   InstStore *Inst = llvm::cast<InstStore>(*Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
   Variable *Index = NULL;
-  int32_t Shift = 0;
+  uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
+  // At the ICE level, load instructions should not use the
+  // segment registers, and computeAddressOpt only works at the level
+  // of Variables and Constants, not other OperandX8632Mem, so there
+  // should be no mention of segment registers there either.
+  OperandX8632Mem::SegmentRegisters SegmentReg =
+      OperandX8632Mem::DefaultSegment;
   computeAddressOpt(Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Constant *OffsetOp = Ctx->getConstantInt(IceType_i32, Offset);
     Addr = OperandX8632Mem::create(Func, Data->getType(), Base, OffsetOp, Index,
-                                   Shift);
+                                   Shift, SegmentReg);
     Inst->setDeleted();
     Context.insert(InstStore::create(Func, Data, Addr));
   }
 }
 
 void TargetX8632::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
@@ skipping 40 matching lines @@
     Variable *RegIndex = NULL;
     if (Base) {
       RegBase = legalizeToVar(Base, true);
     }
     if (Index) {
       RegIndex = legalizeToVar(Index, true);
     }
     if (Base != RegBase || Index != RegIndex) {
       From =
           OperandX8632Mem::create(Func, Mem->getType(), RegBase,
-                                  Mem->getOffset(), RegIndex, Mem->getShift());
+                                  Mem->getOffset(), RegIndex, Mem->getShift(),
+                                  Mem->getSegmentRegister());
     }
 
     if (!(Allowed & Legal_Mem)) {
       Variable *Reg = makeReg(From->getType(), RegNum);
       _mov(Reg, From, RegNum);
       From = Reg;
     }
     return From;
   }
   if (llvm::isa<Constant>(From)) {
@@ skipping 106 matching lines @@
   // llvm-mc doesn't parse "dword ptr [.L$foo]".
   Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
 }
 
 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
   Ostream &Str = Ctx->getStrEmit();
   Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
 }
 
 } // end of namespace Ice