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Issue 321993002: Add a few Subzero intrinsics (not the atomic ones yet). (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: remove TODO Created 6 years, 6 months ago
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1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// 1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of lowered x86-32 instructions in the 10 // This file defines properties of lowered x86-32 instructions in the
(...skipping 20 matching lines...) Expand all
31 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 31 X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
32 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 32 X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
33 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 33 X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
34 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 34 X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
35 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 35 X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
36 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 36 X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
37 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ 37 X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
38 //#define X(val, init, name, name16, name8, scratch, preserved, stackptr, 38 //#define X(val, init, name, name16, name8, scratch, preserved, stackptr,
39 // frameptr, isI8, isInt, isFP) 39 // frameptr, isI8, isInt, isFP)
40 40
41 // X86 segment registers.
42 #define SEG_REGX8632_TABLE \
43 /* enum value, name */ \
44 X(SegReg_CS, "cs") \
45 X(SegReg_DS, "ds") \
46 X(SegReg_ES, "es") \
47 X(SegReg_SS, "ss") \
48 X(SegReg_FS, "fs") \
49 X(SegReg_GS, "gs") \
50 //#define X(val, name)
41 51
42 #define ICEINSTX8632BR_TABLE \ 52 #define ICEINSTX8632BR_TABLE \
43 /* enum value, dump, emit */ \ 53 /* enum value, dump, emit */ \
44 X(Br_a, "a", "ja") \ 54 X(Br_a, "a", "ja") \
45 X(Br_ae, "ae", "jae") \ 55 X(Br_ae, "ae", "jae") \
46 X(Br_b, "b", "jb") \ 56 X(Br_b, "b", "jb") \
47 X(Br_be, "be", "jbe") \ 57 X(Br_be, "be", "jbe") \
48 X(Br_e, "e", "je") \ 58 X(Br_e, "e", "je") \
49 X(Br_g, "g", "jg") \ 59 X(Br_g, "g", "jg") \
50 X(Br_ge, "ge", "jge") \ 60 X(Br_ge, "ge", "jge") \
(...skipping 10 matching lines...) Expand all
61 X(IceType_i1, "i", "" , "byte ptr") \ 71 X(IceType_i1, "i", "" , "byte ptr") \
62 X(IceType_i8, "i", "" , "byte ptr") \ 72 X(IceType_i8, "i", "" , "byte ptr") \
63 X(IceType_i16, "i", "" , "word ptr") \ 73 X(IceType_i16, "i", "" , "word ptr") \
64 X(IceType_i32, "i", "" , "dword ptr") \ 74 X(IceType_i32, "i", "" , "dword ptr") \
65 X(IceType_i64, "i", "" , "qword ptr") \ 75 X(IceType_i64, "i", "" , "qword ptr") \
66 X(IceType_f32, "s", "ss", "dword ptr") \ 76 X(IceType_f32, "s", "ss", "dword ptr") \
67 X(IceType_f64, "d", "sd", "qword ptr") \ 77 X(IceType_f64, "d", "sd", "qword ptr") \
68 //#define X(tag, cvt, sdss, width) 78 //#define X(tag, cvt, sdss, width)
69 79
70 #endif // SUBZERO_SRC_ICEINSTX8632_DEF 80 #endif // SUBZERO_SRC_ICEINSTX8632_DEF
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