Add a few Subzero intrinsics (not the atomic ones yet).

src/IceTargetLoweringX8632.cpp

 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX8632 class, which
@@ skipping 413 matching lines @@
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64);
     OperandX8632Mem *Mem = OperandX8632Mem::create(
         Func, Ty, FramePtr,
         Ctx->getConstantInt(IceType_i32, Arg->getStackOffset()));
     _mov(Arg, Mem);
   }
   InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
 }
 
+// static
+Type TargetX8632::stackSlotType() { return IceType_i32; }
+
 void TargetX8632::addProlog(CfgNode *Node) {
   // If SimpleCoalescing is false, each variable without a register
   // gets its own unique stack slot, which leads to large stack
   // frames.  If SimpleCoalescing is true, then each "global" variable
   // without a register gets its own slot, but "local" variable slots
   // are reused across basic blocks.  E.g., if A and B are local to
   // block 1 and C is local to block 2, then C may share a slot with A
   // or B.
   const bool SimpleCoalescing = true;
   size_t InArgsSizeBytes = 0;
@@ skipping 309 matching lines @@
     split64(Var);
     return Var->getLo();
   }
   if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
     uint64_t Mask = (1ull << 32) - 1;
     return Ctx->getConstantInt(IceType_i32, Const->getValue() & Mask);
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(),
                                    Mem->getOffset(), Mem->getIndex(),
-                                   Mem->getShift());
+                                   Mem->getShift(), Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
   return NULL;
 }
 
 Operand *TargetX8632::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64);
   if (Operand->getType() != IceType_i64)
     return Operand;
   if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getHi();
   }
   if (ConstantInteger *Const = llvm::dyn_cast<ConstantInteger>(Operand)) {
     return Ctx->getConstantInt(IceType_i32, Const->getValue() >> 32);
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     Constant *Offset = Mem->getOffset();
     if (Offset == NULL)
       Offset = Ctx->getConstantInt(IceType_i32, 4);
     else if (ConstantInteger *IntOffset =
                  llvm::dyn_cast<ConstantInteger>(Offset)) {
       Offset = Ctx->getConstantInt(IceType_i32, 4 + IntOffset->getValue());
     } else if (ConstantRelocatable *SymOffset =
                    llvm::dyn_cast<ConstantRelocatable>(Offset)) {
       Offset = Ctx->getConstantSym(IceType_i32, 4 + SymOffset->getOffset(),
                                    SymOffset->getName());
     }
     return OperandX8632Mem::create(Func, IceType_i32, Mem->getBase(), Offset,
-                                   Mem->getIndex(), Mem->getShift());
+                                   Mem->getIndex(), Mem->getShift(),
+                                   Mem->getSegmentRegister());
   }
   llvm_unreachable("Unsupported operand type");
   return NULL;
 }
 
 llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(Reg_NUM);
 
 #define X(val, init, name, name16, name8, scratch, preserved, stackptr,        \
@@ skipping 955 matching lines @@
       legalize(Src0, IsSrc1ImmOrReg ? Legal_All : Legal_Reg, true);
   InstX8632Label *Label = InstX8632Label::create(Func, this);
   _cmp(Src0New, Src1);
   _mov(Dest, One);
   _br(getIcmp32Mapping(Inst->getCondition()), Label);
   Context.insert(InstFakeUse::create(Func, Dest));
   _mov(Dest, Zero);
   Context.insert(Label);
 }
 
+void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
+  switch (Instr->getIntrinsicInfo().ID) {
+  case Intrinsics::AtomicCmpxchg:
+  case Intrinsics::AtomicFence:
+  case Intrinsics::AtomicFenceAll:
+  case Intrinsics::AtomicIsLockFree:
+  case Intrinsics::AtomicLoad:
+  case Intrinsics::AtomicRMW:
+  case Intrinsics::AtomicStore:
+  case Intrinsics::Bswap:
+  case Intrinsics::Ctlz:
+  case Intrinsics::Ctpop:
+  case Intrinsics::Cttz:
+    Func->setError("Unhandled intrinsic");
+    return;
+  case Intrinsics::Longjmp: {
+    InstCall *Call = makeHelperCall("longjmp", NULL, 2);
+    Call->addArg(Instr->getArg(0));
+    Call->addArg(Instr->getArg(1));
+    lowerCall(Call);
+    break;
+  }
+  case Intrinsics::Memcpy: {
+    // In the future, we could potentially emit an inline memcpy/memset, etc.
+    // for intrinsic calls w/ a known length.
+    InstCall *Call = makeHelperCall("memcpy", NULL, 3);
+    Call->addArg(Instr->getArg(0));
+    Call->addArg(Instr->getArg(1));
+    Call->addArg(Instr->getArg(2));
+    lowerCall(Call);
+    break;
+  }
+  case Intrinsics::Memmove: {
+    InstCall *Call = makeHelperCall("memmove", NULL, 3);
+    Call->addArg(Instr->getArg(0));
+    Call->addArg(Instr->getArg(1));
+    Call->addArg(Instr->getArg(2));
+    lowerCall(Call);
+    break;
+  }
+  case Intrinsics::Memset: {
+    // The value operand needs to be extended to a stack slot size
+    // because we "push" only works for a specific operand size.
+    Operand *ValOp = Instr->getArg(1);
+    assert(ValOp->getType() == IceType_i8);
+    Variable *ValExt = makeReg(stackSlotType());
+    _movzx(ValExt, ValOp);
+    InstCall *Call = makeHelperCall("memset", NULL, 3);
+    Call->addArg(Instr->getArg(0));
+    Call->addArg(ValExt);
+    Call->addArg(Instr->getArg(2));
+    lowerCall(Call);
+    break;
+  }
+  case Intrinsics::NaClReadTP: {
+    Constant *Zero = Ctx->getConstantInt(IceType_i32, 0);
+    Operand *Src = OperandX8632Mem::create(Func, IceType_i32, NULL, Zero, NULL,
+                                           0, OperandX8632Mem::SegReg_GS);
+    Variable *Dest = Instr->getDest();
+    Variable *T = NULL;
+    _mov(T, Src);
+    _mov(Dest, T);
+    break;
+  }
+  case Intrinsics::Setjmp: {
+    InstCall *Call = makeHelperCall("setjmp", Instr->getDest(), 1);
+    Call->addArg(Instr->getArg(0));
+    lowerCall(Call);
+    break;
+  }
+  case Intrinsics::Sqrt:
+  case Intrinsics::Stacksave:
+  case Intrinsics::Stackrestore:
+    Func->setError("Unhandled intrinsic");
+    return;
+  case Intrinsics::Trap:
+    _ud2();
+    break;
+  case Intrinsics::UnknownIntrinsic:
+    Func->setError("Should not be lowering UnknownIntrinsic");
+    return;
+  }
+  return;
+}
+
 namespace {
 
 bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
 }
 
-void computeAddressOpt(Variable *&Base, Variable *&Index, int32_t &Shift,
+void computeAddressOpt(Variable *&Base, Variable *&Index, uint16_t &Shift,
                        int32_t &Offset) {
   (void)Offset; // TODO: pattern-match for non-zero offsets.
   if (Base == NULL)
     return;
   // If the Base has more than one use or is live across multiple
   // blocks, then don't go further.  Alternatively (?), never consider
   // a transformation that would change a variable that is currently
   // *not* live across basic block boundaries into one that *is*.
   if (Base->isMultiblockLife() /* || Base->getUseCount() > 1*/)
     return;
@@ skipping 160 matching lines @@
 
   InstAssign *Assign = InstAssign::create(Func, Inst->getDest(), Src0);
   lowerAssign(Assign);
 }
 
 void TargetX8632::doAddressOptLoad() {
   Inst *Inst = *Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = NULL;
-  int32_t Shift = 0;
+  uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
+  // Vanilla ICE load instructions should not use the segment registers,
+  // and computeAddressOpt only works at the level of Variables and Constants,
+  // not other OperandX8632Mem, so there should be no mention of segment
+  // registers there either.
+  const OperandX8632Mem::SegmentRegisters SegmentReg =
+      OperandX8632Mem::DefaultSegment;
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   computeAddressOpt(Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Constant *OffsetOp = Ctx->getConstantInt(IceType_i32, Offset);
     Addr = OperandX8632Mem::create(Func, Dest->getType(), Base, OffsetOp, Index,
-                                   Shift);
+                                   Shift, SegmentReg);
     Inst->setDeleted();
     Context.insert(InstLoad::create(Func, Dest, Addr));
   }
 }
 
 void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetX8632::lowerRet(const InstRet *Inst) {
@@ skipping 88 matching lines @@
     Value = legalize(Value, Legal_Reg | Legal_Imm, true);
     _store(Value, NewAddr);
   }
 }
 
 void TargetX8632::doAddressOptStore() {
   InstStore *Inst = llvm::cast<InstStore>(*Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
   Variable *Index = NULL;
-  int32_t Shift = 0;
+  uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
+  // Vanilla ICE load instructions should not use the segment registers,

[Jim Stichnoth, 2014/06/16 23:05:16]

load --> store

[jvoung (off chromium), 2014/06/17 17:36:19]

Done.

+  // and computeAddressOpt only works at the level of Variables and Constants,
+  // not other OperandX8632Mem, so there should be no mention of segment
+  // registers there either.
+  const OperandX8632Mem::SegmentRegisters SegmentReg =
+      OperandX8632Mem::DefaultSegment;
   computeAddressOpt(Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Constant *OffsetOp = Ctx->getConstantInt(IceType_i32, Offset);
     Addr = OperandX8632Mem::create(Func, Data->getType(), Base, OffsetOp, Index,
-                                   Shift);
+                                   Shift, SegmentReg);
     Inst->setDeleted();
     Context.insert(InstStore::create(Func, Data, Addr));
   }
 }
 
 void TargetX8632::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
@@ skipping 38 matching lines @@
     Variable *Index = Mem->getIndex();
     Variable *RegBase = NULL;
     Variable *RegIndex = NULL;
     if (Base) {
       RegBase = legalizeToVar(Base, true);
     }
     if (Index) {
       RegIndex = legalizeToVar(Index, true);
     }
     if (Base != RegBase || Index != RegIndex) {
-      From =
-          OperandX8632Mem::create(Func, Mem->getType(), RegBase,
-                                  Mem->getOffset(), RegIndex, Mem->getShift());
+      From = OperandX8632Mem::create(
+          Func, Mem->getType(), RegBase, Mem->getOffset(), RegIndex,
+          Mem->getShift(), Mem->getSegmentRegister());
     }
 
     if (!(Allowed & Legal_Mem)) {
       Variable *Reg = makeReg(From->getType(), RegNum);
       _mov(Reg, From, RegNum);
       From = Reg;
     }
     return From;
   }
   if (llvm::isa<Constant>(From)) {
@@ skipping 106 matching lines @@
   // llvm-mc doesn't parse "dword ptr [.L$foo]".
   Str << "dword ptr [L$" << IceType_f32 << "$" << getPoolEntryID() << "]";
 }
 
 template <> void ConstantDouble::emit(GlobalContext *Ctx) const {
   Ostream &Str = Ctx->getStrEmit();
   Str << "qword ptr [L$" << IceType_f64 << "$" << getPoolEntryID() << "]";
 }
 
 } // end of namespace Ice