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Issue 321733002: PNaCl SIMD: allow element-aligned vector load/store (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-llvm.git@master
Patch Set: Add alloca test. Created 6 years, 6 months ago
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« lib/Transforms/NaCl/StripAttributes.cpp ('K') | « lib/Transforms/NaCl/StripAttributes.cpp ('k') | test/NaCl/PNaClABI/instructions.ll » ('j') | no next file with comments »
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1 ; Tests that vector operations survive through PNaCl bitcode files. 1 ; Tests that vector operations survive through PNaCl bitcode files.
2 2
3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \ 3 ; RUN: llvm-as < %s | pnacl-freeze | pnacl-thaw | llvm-dis - \
4 ; RUN: | FileCheck %s 4 ; RUN: | FileCheck %s
5 5
6 define internal void @loadstore(i32 %addr) { ; CHECK-LABEL: loadstore
7 %ptr16xi8 = inttoptr i32 %addr to <16 x i8>* ; CHECK-NEXT: %[[ptr16xi8: [0-9]+]] = inttoptr i32 %[[addr:[0-9]+]] to <16 x i8>*
8 %l16xi8 = load <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: %[[l16xi8:[0 -9]+]] = load <16 x i8>* %[[ptr16xi8]], align 1
9 %ptr8xi16 = inttoptr i32 %addr to <8 x i16>* ; CHECK-NEXT: %[[ptr8xi16: [0-9]+]] = inttoptr i32 %[[addr]] to <8 x i16>*
10 %l8xi16 = load <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: %[[l8xi16:[0 -9]+]] = load <8 x i16>* %[[ptr8xi16]], align 2
11 %ptr4xi32 = inttoptr i32 %addr to <4 x i32>* ; CHECK-NEXT: %[[ptr4xi32: [0-9]+]] = inttoptr i32 %[[addr]] to <4 x i32>*
12 %l4xi32 = load <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: %[[l4xi32:[0 -9]+]] = load <4 x i32>* %[[ptr4xi32]], align 4
13 %ptr4xfloat = inttoptr i32 %addr to <4 x float>* ; CHECK-NEXT: %[[ptr4xfloa t:[0-9]+]] = inttoptr i32 %[[addr]] to <4 x float>*
14 %l4xfloat = load <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: %[[l4xfloat: [0-9]+]] = load <4 x float>* %[[ptr4xfloat]], align 4
15
16 store <16 x i8> undef, <16 x i8>* %ptr16xi8, align 1 ; CHECK-NEXT: store <16 x i8> undef, <16 x i8>* %[[ptr16xi8]], align 1
17 store <8 x i16> undef, <8 x i16>* %ptr8xi16, align 2 ; CHECK-NEXT: store <8 x i16> undef, <8 x i16>* %[[ptr8xi16]], align 2
18 store <4 x i32> undef, <4 x i32>* %ptr4xi32, align 4 ; CHECK-NEXT: store <4 x i32> undef, <4 x i32>* %[[ptr4xi32]], align 4
19 store <4 x float> undef, <4 x float>* %ptr4xfloat, align 4 ; CHECK-NEXT: store <4 x float> undef, <4 x float>* %[[ptr4xfloat]], align 4
20
21 ret void ; CHECK-NEXT: ret void
22 }
23
6 define internal void @binops() { ; CHECK-LABEL: binops 24 define internal void @binops() { ; CHECK-LABEL: binops
7 %1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, un def 25 %1 = add <4 x i32> undef, undef ; CHECK-NEXT: %1 = add <4 x i32> undef, un def
8 %2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef, undef 26 %2 = fadd <4 x float> undef, undef ; CHECK-NEXT: %2 = fadd <4 x float> undef, undef
9 %3 = sub <4 x i32> undef, undef ; CHECK-NEXT: %3 = sub <4 x i32> undef, un def 27 %3 = sub <4 x i32> undef, undef ; CHECK-NEXT: %3 = sub <4 x i32> undef, un def
10 %4 = fsub <4 x float> undef, undef ; CHECK-NEXT: %4 = fsub <4 x float> undef, undef 28 %4 = fsub <4 x float> undef, undef ; CHECK-NEXT: %4 = fsub <4 x float> undef, undef
11 %5 = mul <4 x i32> undef, undef ; CHECK-NEXT: %5 = mul <4 x i32> undef, un def 29 %5 = mul <4 x i32> undef, undef ; CHECK-NEXT: %5 = mul <4 x i32> undef, un def
12 %6 = fmul <4 x float> undef, undef ; CHECK-NEXT: %6 = fmul <4 x float> undef, undef 30 %6 = fmul <4 x float> undef, undef ; CHECK-NEXT: %6 = fmul <4 x float> undef, undef
13 %7 = udiv <4 x i32> undef, undef ; CHECK-NEXT: %7 = udiv <4 x i32> undef, u ndef 31 %7 = udiv <4 x i32> undef, undef ; CHECK-NEXT: %7 = udiv <4 x i32> undef, u ndef
14 %8 = sdiv <4 x i32> undef, undef ; CHECK-NEXT: %8 = sdiv <4 x i32> undef, u ndef 32 %8 = sdiv <4 x i32> undef, undef ; CHECK-NEXT: %8 = sdiv <4 x i32> undef, u ndef
15 %9 = fdiv <4 x float> undef, undef ; CHECK-NEXT: %9 = fdiv <4 x float> undef, undef 33 %9 = fdiv <4 x float> undef, undef ; CHECK-NEXT: %9 = fdiv <4 x float> undef, undef
(...skipping 14 matching lines...) Expand all
30 %1 = extractelement <4 x i32> undef, i32 0 ; CHECK-NEXT: %1 = extractele ment <4 x i32> undef, i32 0 48 %1 = extractelement <4 x i32> undef, i32 0 ; CHECK-NEXT: %1 = extractele ment <4 x i32> undef, i32 0
31 %2 = extractelement <4 x i32> undef, i32 1 ; CHECK-NEXT: %2 = extractele ment <4 x i32> undef, i32 1 49 %2 = extractelement <4 x i32> undef, i32 1 ; CHECK-NEXT: %2 = extractele ment <4 x i32> undef, i32 1
32 %3 = extractelement <4 x i32> undef, i32 2 ; CHECK-NEXT: %3 = extractele ment <4 x i32> undef, i32 2 50 %3 = extractelement <4 x i32> undef, i32 2 ; CHECK-NEXT: %3 = extractele ment <4 x i32> undef, i32 2
33 %4 = extractelement <4 x i32> undef, i32 3 ; CHECK-NEXT: %4 = extractele ment <4 x i32> undef, i32 3 51 %4 = extractelement <4 x i32> undef, i32 3 ; CHECK-NEXT: %4 = extractele ment <4 x i32> undef, i32 3
34 %5 = insertelement <4 x i32> undef, i32 1, i32 0 ; CHECK-NEXT: %5 = insertelem ent <4 x i32> undef, i32 1, i32 0 52 %5 = insertelement <4 x i32> undef, i32 1, i32 0 ; CHECK-NEXT: %5 = insertelem ent <4 x i32> undef, i32 1, i32 0
35 %6 = insertelement <4 x i32> undef, i32 1, i32 1 ; CHECK-NEXT: %6 = insertelem ent <4 x i32> undef, i32 1, i32 1 53 %6 = insertelement <4 x i32> undef, i32 1, i32 1 ; CHECK-NEXT: %6 = insertelem ent <4 x i32> undef, i32 1, i32 1
36 %7 = insertelement <4 x i32> undef, i32 1, i32 2 ; CHECK-NEXT: %7 = insertelem ent <4 x i32> undef, i32 1, i32 2 54 %7 = insertelement <4 x i32> undef, i32 1, i32 2 ; CHECK-NEXT: %7 = insertelem ent <4 x i32> undef, i32 1, i32 2
37 %8 = insertelement <4 x i32> undef, i32 1, i32 3 ; CHECK-NEXT: %8 = insertelem ent <4 x i32> undef, i32 1, i32 3 55 %8 = insertelement <4 x i32> undef, i32 1, i32 3 ; CHECK-NEXT: %8 = insertelem ent <4 x i32> undef, i32 1, i32 3
38 ret void ; CHECK-NEXT: ret void 56 ret void ; CHECK-NEXT: ret void
39 } 57 }
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« lib/Transforms/NaCl/StripAttributes.cpp ('K') | « lib/Transforms/NaCl/StripAttributes.cpp ('k') | test/NaCl/PNaClABI/instructions.ll » ('j') | no next file with comments »

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