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Issue 321123002: Make presubmit script happy again. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebased Created 6 years, 6 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #include "src/v8.h" 7 #include "src/v8.h"
8 8
9 #if V8_TARGET_ARCH_MIPS 9 #if V8_TARGET_ARCH_MIPS
10 10
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860 860
861 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) { 861 void MacroAssembler::Pref(int32_t hint, const MemOperand& rs) {
862 if (kArchVariant == kLoongson) { 862 if (kArchVariant == kLoongson) {
863 lw(zero_reg, rs); 863 lw(zero_reg, rs);
864 } else { 864 } else {
865 pref(hint, rs); 865 pref(hint, rs);
866 } 866 }
867 } 867 }
868 868
869 869
870 //------------Pseudo-instructions------------- 870 // ------------Pseudo-instructions-------------
871 871
872 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) { 872 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) {
873 lwr(rd, rs); 873 lwr(rd, rs);
874 lwl(rd, MemOperand(rs.rm(), rs.offset() + 3)); 874 lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
875 } 875 }
876 876
877 877
878 void MacroAssembler::Usw(Register rd, const MemOperand& rs) { 878 void MacroAssembler::Usw(Register rd, const MemOperand& rs) {
879 swr(rd, rs); 879 swr(rd, rs);
880 swl(rd, MemOperand(rs.rm(), rs.offset() + 3)); 880 swl(rd, MemOperand(rs.rm(), rs.offset() + 3));
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5756 } 5756 }
5757 if (ms.shift() > 0) sra(result, result, ms.shift()); 5757 if (ms.shift() > 0) sra(result, result, ms.shift());
5758 srl(at, dividend, 31); 5758 srl(at, dividend, 31);
5759 Addu(result, result, Operand(at)); 5759 Addu(result, result, Operand(at));
5760 } 5760 }
5761 5761
5762 5762
5763 } } // namespace v8::internal 5763 } } // namespace v8::internal
5764 5764
5765 #endif // V8_TARGET_ARCH_MIPS 5765 #endif // V8_TARGET_ARCH_MIPS
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