ARM64: Clean up support for explicit literal load.

src/arm64/assembler-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
 #define V8_ARM64_ASSEMBLER_ARM64_H_
 
 #include <list>
 #include <map>
 
@@ skipping 581 matching lines @@
 
 // AAPCS64 callee-saved registers.
 #define kCalleeSaved CPURegList::GetCalleeSaved()
 #define kCalleeSavedFP CPURegList::GetCalleeSavedFP()
 
 
 // AAPCS64 caller-saved registers. Note that this includes lr.
 #define kCallerSaved CPURegList::GetCallerSaved()
 #define kCallerSavedFP CPURegList::GetCallerSavedFP()
 
+// -----------------------------------------------------------------------------
+// Immediates.
+class Immediate {
+ public:
+  template<typename T>
+  inline explicit Immediate(Handle<T> handle);
+
+  // This is allowed to be an implicit constructor because Immediate is
+  // a wrapper class that doesn't normally perform any type conversion.
+  template<typename T>
+  inline Immediate(T value);  // NOLINT(runtime/explicit)
+
+  template<typename T>
+  inline Immediate(T value, RelocInfo::Mode rmode);
+
+  int64_t value() const { return value_; }
+  RelocInfo::Mode rmode() const { return rmode_; }
+
+ private:
+  void InitializeHandle(Handle<Object> value);
+
+  int64_t value_;
+  RelocInfo::Mode rmode_;
+};
+
 
 // -----------------------------------------------------------------------------
 // Operands.
 const int kSmiShift = kSmiTagSize + kSmiShiftSize;
 const uint64_t kSmiShiftMask = (1UL << kSmiShift) - 1;
 
 // Represents an operand in a machine instruction.
 class Operand {
   // TODO(all): If necessary, study more in details which methods
   // TODO(all): should be inlined or not.
@@ skipping 15 matching lines @@
                  unsigned shift_amount = 0);
 
   template<typename T>
   inline explicit Operand(Handle<T> handle);
 
   // Implicit constructor for all int types, ExternalReference, and Smi.
   template<typename T>
   inline Operand(T t);  // NOLINT(runtime/explicit)
 
   // Implicit constructor for int types.
-  template<typename int_t>
-  inline Operand(int_t t, RelocInfo::Mode rmode);
+  template<typename T>
+  inline Operand(T t, RelocInfo::Mode rmode);
 
   inline bool IsImmediate() const;
   inline bool IsShiftedRegister() const;
   inline bool IsExtendedRegister() const;
   inline bool IsZero() const;
 
   // This returns an LSL shift (<= 4) operand as an equivalent extend operand,
   // which helps in the encoding of instructions that use the stack pointer.
   inline Operand ToExtendedRegister() const;
 
-  inline int64_t immediate() const;
+  inline Immediate immediate() const;
+  inline int64_t ImmediateValue() const;
   inline Register reg() const;
   inline Shift shift() const;
   inline Extend extend() const;
   inline unsigned shift_amount() const;
 
   // Relocation information.
-  RelocInfo::Mode rmode() const { return rmode_; }
-  void set_rmode(RelocInfo::Mode rmode) { rmode_ = rmode; }
   bool NeedsRelocation(const Assembler* assembler) const;
 
   // Helpers
   inline static Operand UntagSmi(Register smi);
   inline static Operand UntagSmiAndScale(Register smi, int scale);
 
  private:
-  void initialize_handle(Handle<Object> value);
-  int64_t immediate_;
+  Immediate immediate_;
   Register reg_;
   Shift shift_;
   Extend extend_;
   unsigned shift_amount_;
-  RelocInfo::Mode rmode_;
 };
 
 
 // MemOperand represents a memory operand in a load or store instruction.
 class MemOperand {
  public:
   inline explicit MemOperand();
   inline explicit MemOperand(Register base,
                              ptrdiff_t offset = 0,
                              AddrMode addrmode = Offset);
@@ skipping 680 matching lines @@
   // Bit count, bit reverse and endian reverse.
   void rbit(const Register& rd, const Register& rn);
   void rev16(const Register& rd, const Register& rn);
   void rev32(const Register& rd, const Register& rn);
   void rev(const Register& rd, const Register& rn);
   void clz(const Register& rd, const Register& rn);
   void cls(const Register& rd, const Register& rn);
 
   // Memory instructions.
 
-  // Load literal from pc + offset_from_pc.
-  void LoadLiteral(const CPURegister& rt, int offset_from_pc);
-
   // Load integer or FP register.
   void ldr(const CPURegister& rt, const MemOperand& src);
 
   // Store integer or FP register.
   void str(const CPURegister& rt, const MemOperand& dst);
 
   // Load word with sign extension.
   void ldrsw(const Register& rt, const MemOperand& src);
 
   // Load byte.
@@ skipping 26 matching lines @@
   void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
 
   // Load integer or FP register pair, non-temporal.
   void ldnp(const CPURegister& rt, const CPURegister& rt2,
             const MemOperand& src);
 
   // Store integer or FP register pair, non-temporal.
   void stnp(const CPURegister& rt, const CPURegister& rt2,
             const MemOperand& dst);
 
+  // Load literal to register from a pc relative address.
+  void ldr_pcrel(const CPURegister& rt, int imm19);
+
   // Load literal to register.
-  void ldr(const Register& rt, uint64_t imm);
-
-  // Load literal to FP register.
-  void ldr(const FPRegister& ft, double imm);
-  void ldr(const FPRegister& ft, float imm);
+  void ldr(const CPURegister& rt, const Immediate& imm);
 
   // Move instructions. The default shift of -1 indicates that the move
   // instruction will calculate an appropriate 16-bit immediate and left shift
   // that is equal to the 64-bit immediate argument. If an explicit left shift
   // is specified (0, 16, 32 or 48), the immediate must be a 16-bit value.
   //
   // For movk, an explicit shift can be used to indicate which half word should
   // be overwritten, eg. movk(x0, 0, 0) will overwrite the least-significant
   // half word with zero, whereas movk(x0, 0, 48) will overwrite the
   // most-significant.
@@ skipping 397 matching lines @@
   // If need_protection is true, the veneers are protected by a branch jumping
   // over the code.
   void EmitVeneers(bool force_emit, bool need_protection,
                    int margin = kVeneerDistanceMargin);
   void EmitVeneersGuard() { EmitPoolGuard(); }
   // Checks whether veneers need to be emitted at this point.
   // If force_emit is set, a veneer is generated for *all* unresolved branches.
   void CheckVeneerPool(bool force_emit, bool require_jump,
                        int margin = kVeneerDistanceMargin);
 
-
   class BlockPoolsScope {
    public:
     explicit BlockPoolsScope(Assembler* assem) : assem_(assem) {
       assem_->StartBlockPools();
     }
     ~BlockPoolsScope() {
       assem_->EndBlockPools();
     }
 
    private:
     Assembler* assem_;
 
     DISALLOW_IMPLICIT_CONSTRUCTORS(BlockPoolsScope);
   };
 
-  // Available for constrained code generation scopes. Prefer
-  // MacroAssembler::Mov() when possible.
-  inline void LoadRelocated(const CPURegister& rt, const Operand& operand);
-
  protected:
   inline const Register& AppropriateZeroRegFor(const CPURegister& reg) const;
 
   void LoadStore(const CPURegister& rt,
                  const MemOperand& addr,
                  LoadStoreOp op);
   static bool IsImmLSUnscaled(ptrdiff_t offset);
   static bool IsImmLSScaled(ptrdiff_t offset, LSDataSize size);
 
   void Logical(const Register& rd,
@@ skipping 46 matching lines @@
   static inline LoadStoreOp LoadOpFor(const CPURegister& rt);
   static inline LoadStorePairOp LoadPairOpFor(const CPURegister& rt,
                                               const CPURegister& rt2);
   static inline LoadStoreOp StoreOpFor(const CPURegister& rt);
   static inline LoadStorePairOp StorePairOpFor(const CPURegister& rt,
                                                const CPURegister& rt2);
   static inline LoadStorePairNonTemporalOp LoadPairNonTemporalOpFor(
     const CPURegister& rt, const CPURegister& rt2);
   static inline LoadStorePairNonTemporalOp StorePairNonTemporalOpFor(
     const CPURegister& rt, const CPURegister& rt2);
+  static inline LoadLiteralOp LoadLiteralOpFor(const CPURegister& rt);
 
   // Remove the specified branch from the unbound label link chain.
   // If available, a veneer for this label can be used for other branches in the
   // chain if the link chain cannot be fixed up without this branch.
   void RemoveBranchFromLabelLinkChain(Instruction* branch,
                                       Label* label,
                                       Instruction* label_veneer = NULL);
 
  private:
   // Instruction helpers.
@@ skipping 12 matching lines @@
                                 FlagsUpdate S,
                                 Instr op);
   void LoadStorePair(const CPURegister& rt,
                      const CPURegister& rt2,
                      const MemOperand& addr,
                      LoadStorePairOp op);
   void LoadStorePairNonTemporal(const CPURegister& rt,
                                 const CPURegister& rt2,
                                 const MemOperand& addr,
                                 LoadStorePairNonTemporalOp op);
-  // Register the relocation information for the operand and load its value
-  // into rt.
-  void LoadRelocatedValue(const CPURegister& rt,
-                          const Operand& operand,
-                          LoadLiteralOp op);
   void ConditionalSelect(const Register& rd,
                          const Register& rn,
                          const Register& rm,
                          Condition cond,
                          ConditionalSelectOp op);
   void DataProcessing1Source(const Register& rd,
                              const Register& rn,
                              DataProcessing1SourceOp op);
   void DataProcessing3Source(const Register& rd,
                              const Register& rn,
@@ skipping 261 matching lines @@
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBufferSpace();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_H_