ARM64: Clean up support for explicit literal load.

src/arm64/assembler-arm64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_INL_H_
 #define V8_ARM64_ASSEMBLER_ARM64_INL_H_
 
 #include "src/arm64/assembler-arm64.h"
 #include "src/cpu.h"
 #include "src/debug.h"
@@ skipping 243 matching lines @@
   return FPRegister::SRegFromCode(reg_code);
 }
 
 
 inline FPRegister CPURegister::D() const {
   ASSERT(IsValidFPRegister());
   return FPRegister::DRegFromCode(reg_code);
 }
 
 
-// Operand.
+// Immediate.
+// Default initializer is for int types
 template<typename T>
-Operand::Operand(Handle<T> value) : reg_(NoReg) {
-  initialize_handle(value);
-}
-
-
-// Default initializer is for int types
-template<typename int_t>
-struct OperandInitializer {
+struct ImmediateInitializer {
   static const bool kIsIntType = true;
-  static inline RelocInfo::Mode rmode_for(int_t) {
-    return sizeof(int_t) == 8 ? RelocInfo::NONE64 : RelocInfo::NONE32;
+  static inline RelocInfo::Mode rmode_for(T) {
+    return sizeof(T) == 8 ? RelocInfo::NONE64 : RelocInfo::NONE32;
   }
-  static inline int64_t immediate_for(int_t t) {
-    STATIC_ASSERT(sizeof(int_t) <= 8);
+  static inline int64_t immediate_for(T t) {
+    STATIC_ASSERT(sizeof(T) <= 8);
     return t;
   }
 };
 
 
 template<>
-struct OperandInitializer<Smi*> {
+struct ImmediateInitializer<Smi*> {
   static const bool kIsIntType = false;
   static inline RelocInfo::Mode rmode_for(Smi* t) {
     return RelocInfo::NONE64;
   }
   static inline int64_t immediate_for(Smi* t) {;
     return reinterpret_cast<int64_t>(t);
   }
 };
 
 
 template<>
-struct OperandInitializer<ExternalReference> {
+struct ImmediateInitializer<ExternalReference> {
   static const bool kIsIntType = false;
   static inline RelocInfo::Mode rmode_for(ExternalReference t) {
     return RelocInfo::EXTERNAL_REFERENCE;
   }
   static inline int64_t immediate_for(ExternalReference t) {;
     return reinterpret_cast<int64_t>(t.address());
   }
 };
 
 
 template<typename T>
-Operand::Operand(T t)
-    : immediate_(OperandInitializer<T>::immediate_for(t)),
-      reg_(NoReg),
-      rmode_(OperandInitializer<T>::rmode_for(t)) {}
+Immediate::Immediate(Handle<T> value) {
+  InitializeHandle(value);
+}
+
+
+template<typename T>
+Immediate::Immediate(T t)
+    : value_(ImmediateInitializer<T>::immediate_for(t)),
+      rmode_(ImmediateInitializer<T>::rmode_for(t)) {}
+
+
+template<typename T>
+Immediate::Immediate(T t, RelocInfo::Mode rmode)
+    : value_(ImmediateInitializer<T>::immediate_for(t)),
+      rmode_(rmode) {
+  STATIC_ASSERT(ImmediateInitializer<T>::kIsIntType);
+}
+
+
+// Operand.
+template<typename T>
+Operand::Operand(Handle<T> value) : immediate_(value), reg_(NoReg) {}
+
+
+template<typename T>
+Operand::Operand(T t) : immediate_(t), reg_(NoReg) {}
 
 
 template<typename T>
 Operand::Operand(T t, RelocInfo::Mode rmode)
-    : immediate_(OperandInitializer<T>::immediate_for(t)),
-      reg_(NoReg),
-      rmode_(rmode) {
-  STATIC_ASSERT(OperandInitializer<T>::kIsIntType);
-}
+    : immediate_(t, rmode),
+      reg_(NoReg) {}
 
 
 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
-    : reg_(reg),
+    : immediate_(0),
+      reg_(reg),
       shift_(shift),
       extend_(NO_EXTEND),
-      shift_amount_(shift_amount),
-      rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
+      shift_amount_(shift_amount) {
   ASSERT(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
   ASSERT(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
   ASSERT(!reg.IsSP());
 }
 
 
 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
-    : reg_(reg),
+    : immediate_(0),
+      reg_(reg),
       shift_(NO_SHIFT),
       extend_(extend),
-      shift_amount_(shift_amount),
-      rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
+      shift_amount_(shift_amount) {
   ASSERT(reg.IsValid());
   ASSERT(shift_amount <= 4);
   ASSERT(!reg.IsSP());
 
   // Extend modes SXTX and UXTX require a 64-bit register.
   ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
 }
 
 
 bool Operand::IsImmediate() const {
   return reg_.Is(NoReg);
 }
 
 
 bool Operand::IsShiftedRegister() const {
   return reg_.IsValid() && (shift_ != NO_SHIFT);
 }
 
 
 bool Operand::IsExtendedRegister() const {
   return reg_.IsValid() && (extend_ != NO_EXTEND);
 }
 
 
 bool Operand::IsZero() const {
   if (IsImmediate()) {
-    return immediate() == 0;
+    return ImmediateValue() == 0;
   } else {
     return reg().IsZero();
   }
 }
 
 
 Operand Operand::ToExtendedRegister() const {
   ASSERT(IsShiftedRegister());
   ASSERT((shift_ == LSL) && (shift_amount_ <= 4));
   return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
 }
 
 
-int64_t Operand::immediate() const {
+Immediate Operand::immediate() const {
   ASSERT(IsImmediate());
   return immediate_;
 }
 
 
+int64_t Operand::ImmediateValue() const {
+  ASSERT(IsImmediate());
+  return immediate_.value();
+}
+
+
 Register Operand::reg() const {
   ASSERT(IsShiftedRegister() || IsExtendedRegister());
   return reg_;
 }
 
 
 Shift Operand::shift() const {
   ASSERT(IsShiftedRegister());
   return shift_;
 }
@@ skipping 67 matching lines @@
   ASSERT(regoffset.Is64Bits() && !regoffset.IsSP());
   ASSERT(shift == LSL);
 }
 
 
 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
   : base_(base), addrmode_(addrmode) {
   ASSERT(base.Is64Bits() && !base.IsZero());
 
   if (offset.IsImmediate()) {
-    offset_ = offset.immediate();
+    offset_ = offset.ImmediateValue();
 
     regoffset_ = NoReg;
   } else if (offset.IsShiftedRegister()) {
     ASSERT(addrmode == Offset);
 
     regoffset_ = offset.reg();
     shift_= offset.shift();
     shift_amount_ = offset.shift_amount();
 
     extend_ = NO_EXTEND;
@@ skipping 450 matching lines @@
   USE(rt2);
   if (rt.IsRegister()) {
     return rt.Is64Bits() ? STNP_x : STNP_w;
   } else {
     ASSERT(rt.IsFPRegister());
     return rt.Is64Bits() ? STNP_d : STNP_s;
   }
 }
 
 
+LoadLiteralOp Assembler::LoadLiteralOpFor(const CPURegister& rt) {
+  if (rt.IsRegister()) {
+    return rt.Is64Bits() ? LDR_x_lit : LDR_w_lit;
+  } else {
+    ASSERT(rt.IsFPRegister());
+    return rt.Is64Bits() ? LDR_d_lit : LDR_s_lit;
+  }
+}
+
+
 int Assembler::LinkAndGetInstructionOffsetTo(Label* label) {
   ASSERT(kStartOfLabelLinkChain == 0);
   int offset = LinkAndGetByteOffsetTo(label);
   ASSERT(IsAligned(offset, kInstructionSize));
   return offset >> kInstructionSizeLog2;
 }
 
 
 Instr Assembler::Flags(FlagsUpdate S) {
   if (S == SetFlags) {
@@ skipping 236 matching lines @@
   ASSERT(is_uint6(scale));
   return scale << FPScale_offset;
 }
 
 
 const Register& Assembler::AppropriateZeroRegFor(const CPURegister& reg) const {
   return reg.Is64Bits() ? xzr : wzr;
 }
 
 
-void Assembler::LoadRelocated(const CPURegister& rt, const Operand& operand) {
-  LoadRelocatedValue(rt, operand, LDR_x_lit);
-}
-
-
 inline void Assembler::CheckBufferSpace() {
   ASSERT(pc_ < (buffer_ + buffer_size_));
   if (buffer_space() < kGap) {
     GrowBuffer();
   }
 }
 
 
 inline void Assembler::CheckBuffer() {
   CheckBufferSpace();
@@ skipping 13 matching lines @@
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_INL_H_