Rename InvertCondition and ReverseConditionForCmp on arm64 to be consistent with the other ports.

src/arm64/assembler-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
@@ skipping 1112 matching lines @@
                       const Register& rn,
                       const Register& rm,
                       Condition cond) {
   ConditionalSelect(rd, rn, rm, cond, CSNEG);
 }
 
 
 void Assembler::cset(const Register &rd, Condition cond) {
   ASSERT((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
-  csinc(rd, zr, zr, InvertCondition(cond));
+  csinc(rd, zr, zr, NegateCondition(cond));
 }
 
 
 void Assembler::csetm(const Register &rd, Condition cond) {
   ASSERT((cond != al) && (cond != nv));
   Register zr = AppropriateZeroRegFor(rd);
-  csinv(rd, zr, zr, InvertCondition(cond));
+  csinv(rd, zr, zr, NegateCondition(cond));
 }
 
 
 void Assembler::cinc(const Register &rd, const Register &rn, Condition cond) {
   ASSERT((cond != al) && (cond != nv));
-  csinc(rd, rn, rn, InvertCondition(cond));
+  csinc(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) {
   ASSERT((cond != al) && (cond != nv));
-  csinv(rd, rn, rn, InvertCondition(cond));
+  csinv(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::cneg(const Register &rd, const Register &rn, Condition cond) {
   ASSERT((cond != al) && (cond != nv));
-  csneg(rd, rn, rn, InvertCondition(cond));
+  csneg(rd, rn, rn, NegateCondition(cond));
 }
 
 
 void Assembler::ConditionalSelect(const Register& rd,
                                   const Register& rn,
                                   const Register& rm,
                                   Condition cond,
                                   ConditionalSelectOp op) {
   ASSERT(rd.SizeInBits() == rn.SizeInBits());
   ASSERT(rd.SizeInBits() == rm.SizeInBits());
@@ skipping 1738 matching lines @@
     adr(rd, 0);
     MovInt64(scratch, target_offset);
     add(rd, rd, scratch);
   }
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_ARM64