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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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410 // register r is not encoded. | 410 // register r is not encoded. |
411 const Instr kPushRegPattern = | 411 const Instr kPushRegPattern = |
412 al | B26 | 4 | NegPreIndex | kRegister_sp_Code * B16; | 412 al | B26 | 4 | NegPreIndex | kRegister_sp_Code * B16; |
413 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) | 413 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) |
414 // register r is not encoded. | 414 // register r is not encoded. |
415 const Instr kPopRegPattern = | 415 const Instr kPopRegPattern = |
416 al | B26 | L | 4 | PostIndex | kRegister_sp_Code * B16; | 416 al | B26 | L | 4 | PostIndex | kRegister_sp_Code * B16; |
417 // mov lr, pc | 417 // mov lr, pc |
418 const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12; | 418 const Instr kMovLrPc = al | MOV | kRegister_pc_Code | kRegister_lr_Code * B12; |
419 // ldr rd, [pc, #offset] | 419 // ldr rd, [pc, #offset] |
420 const Instr kLdrPCMask = 15 * B24 | 7 * B20 | 15 * B16; | 420 const Instr kLdrPCImmedMask = 15 * B24 | 7 * B20 | 15 * B16; |
421 const Instr kLdrPCPattern = 5 * B24 | L | kRegister_pc_Code * B16; | 421 const Instr kLdrPCImmedPattern = 5 * B24 | L | kRegister_pc_Code * B16; |
422 // ldr rd, [pp, #offset] | 422 // ldr rd, [pp, #offset] |
423 const Instr kLdrPpMask = 15 * B24 | 7 * B20 | 15 * B16; | 423 const Instr kLdrPpImmedMask = 15 * B24 | 7 * B20 | 15 * B16; |
424 const Instr kLdrPpPattern = 5 * B24 | L | kRegister_r8_Code * B16; | 424 const Instr kLdrPpImmedPattern = 5 * B24 | L | kRegister_r8_Code * B16; |
425 // vldr dd, [pc, #offset] | 425 // vldr dd, [pc, #offset] |
426 const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8; | 426 const Instr kVldrDPCMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8; |
427 const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8; | 427 const Instr kVldrDPCPattern = 13 * B24 | L | kRegister_pc_Code * B16 | 11 * B8; |
428 // vldr dd, [pp, #offset] | 428 // vldr dd, [pp, #offset] |
429 const Instr kVldrDPpMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8; | 429 const Instr kVldrDPpMask = 15 * B24 | 3 * B20 | 15 * B16 | 15 * B8; |
430 const Instr kVldrDPpPattern = 13 * B24 | L | kRegister_r8_Code * B16 | 11 * B8; | 430 const Instr kVldrDPpPattern = 13 * B24 | L | kRegister_r8_Code * B16 | 11 * B8; |
431 // blxcc rm | 431 // blxcc rm |
432 const Instr kBlxRegMask = | 432 const Instr kBlxRegMask = |
433 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; | 433 15 * B24 | 15 * B20 | 15 * B16 | 15 * B12 | 15 * B8 | 15 * B4; |
434 const Instr kBlxRegPattern = | 434 const Instr kBlxRegPattern = |
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632 } | 632 } |
633 | 633 |
634 | 634 |
635 Register Assembler::GetRm(Instr instr) { | 635 Register Assembler::GetRm(Instr instr) { |
636 Register reg; | 636 Register reg; |
637 reg.code_ = Instruction::RmValue(instr); | 637 reg.code_ = Instruction::RmValue(instr); |
638 return reg; | 638 return reg; |
639 } | 639 } |
640 | 640 |
641 | 641 |
| 642 Instr Assembler::GetConsantPoolLoadPattern() { |
| 643 if (FLAG_enable_ool_constant_pool) { |
| 644 return kLdrPpImmedPattern; |
| 645 } else { |
| 646 return kLdrPCImmedPattern; |
| 647 } |
| 648 } |
| 649 |
| 650 |
642 bool Assembler::IsPush(Instr instr) { | 651 bool Assembler::IsPush(Instr instr) { |
643 return ((instr & ~kRdMask) == kPushRegPattern); | 652 return ((instr & ~kRdMask) == kPushRegPattern); |
644 } | 653 } |
645 | 654 |
646 | 655 |
647 bool Assembler::IsPop(Instr instr) { | 656 bool Assembler::IsPop(Instr instr) { |
648 return ((instr & ~kRdMask) == kPopRegPattern); | 657 return ((instr & ~kRdMask) == kPopRegPattern); |
649 } | 658 } |
650 | 659 |
651 | 660 |
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665 | 674 |
666 | 675 |
667 bool Assembler::IsLdrRegFpNegOffset(Instr instr) { | 676 bool Assembler::IsLdrRegFpNegOffset(Instr instr) { |
668 return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern); | 677 return ((instr & kLdrStrInstrTypeMask) == kLdrRegFpNegOffsetPattern); |
669 } | 678 } |
670 | 679 |
671 | 680 |
672 bool Assembler::IsLdrPcImmediateOffset(Instr instr) { | 681 bool Assembler::IsLdrPcImmediateOffset(Instr instr) { |
673 // Check the instruction is indeed a | 682 // Check the instruction is indeed a |
674 // ldr<cond> <Rd>, [pc +/- offset_12]. | 683 // ldr<cond> <Rd>, [pc +/- offset_12]. |
675 return (instr & kLdrPCMask) == kLdrPCPattern; | 684 return (instr & kLdrPCImmedMask) == kLdrPCImmedPattern; |
676 } | 685 } |
677 | 686 |
678 | 687 |
679 bool Assembler::IsLdrPpImmediateOffset(Instr instr) { | 688 bool Assembler::IsLdrPpImmediateOffset(Instr instr) { |
680 // Check the instruction is indeed a | 689 // Check the instruction is indeed a |
681 // ldr<cond> <Rd>, [pp +/- offset_12]. | 690 // ldr<cond> <Rd>, [pp +/- offset_12]. |
682 return (instr & kLdrPpMask) == kLdrPpPattern; | 691 return (instr & kLdrPpImmedMask) == kLdrPpImmedPattern; |
683 } | 692 } |
684 | 693 |
685 | 694 |
686 bool Assembler::IsVldrDPcImmediateOffset(Instr instr) { | 695 bool Assembler::IsVldrDPcImmediateOffset(Instr instr) { |
687 // Check the instruction is indeed a | 696 // Check the instruction is indeed a |
688 // vldr<cond> <Dd>, [pc +/- offset_10]. | 697 // vldr<cond> <Dd>, [pc +/- offset_10]. |
689 return (instr & kVldrDPCMask) == kVldrDPCPattern; | 698 return (instr & kVldrDPCMask) == kVldrDPCPattern; |
690 } | 699 } |
691 | 700 |
692 | 701 |
693 bool Assembler::IsVldrDPpImmediateOffset(Instr instr) { | 702 bool Assembler::IsVldrDPpImmediateOffset(Instr instr) { |
694 // Check the instruction is indeed a | 703 // Check the instruction is indeed a |
695 // vldr<cond> <Dd>, [pp +/- offset_10]. | 704 // vldr<cond> <Dd>, [pp +/- offset_10]. |
696 return (instr & kVldrDPpMask) == kVldrDPpPattern; | 705 return (instr & kVldrDPpMask) == kVldrDPpPattern; |
697 } | 706 } |
698 | 707 |
699 | 708 |
| 709 bool Assembler::IsBlxReg(Instr instr) { |
| 710 // Check the instruction is indeed a |
| 711 // blxcc <Rm> |
| 712 return (instr & kBlxRegMask) == kBlxRegPattern; |
| 713 } |
| 714 |
| 715 |
| 716 bool Assembler::IsBlxIp(Instr instr) { |
| 717 // Check the instruction is indeed a |
| 718 // blx ip |
| 719 return instr == kBlxIp; |
| 720 } |
| 721 |
| 722 |
700 bool Assembler::IsTstImmediate(Instr instr) { | 723 bool Assembler::IsTstImmediate(Instr instr) { |
701 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == | 724 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask)) == |
702 (I | TST | S); | 725 (I | TST | S); |
703 } | 726 } |
704 | 727 |
705 | 728 |
706 bool Assembler::IsCmpRegister(Instr instr) { | 729 bool Assembler::IsCmpRegister(Instr instr) { |
707 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) == | 730 return (instr & (B27 | B26 | I | kOpCodeMask | S | kRdMask | B4)) == |
708 (CMP | S); | 731 (CMP | S); |
709 } | 732 } |
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3662 ASSERT((index_64bit == count_of_64bit_) && | 3685 ASSERT((index_64bit == count_of_64bit_) && |
3663 (index_code_ptr == (index_64bit + count_of_code_ptr_)) && | 3686 (index_code_ptr == (index_64bit + count_of_code_ptr_)) && |
3664 (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) && | 3687 (index_heap_ptr == (index_code_ptr + count_of_heap_ptr_)) && |
3665 (index_32bit == (index_heap_ptr + count_of_32bit_))); | 3688 (index_32bit == (index_heap_ptr + count_of_32bit_))); |
3666 } | 3689 } |
3667 | 3690 |
3668 | 3691 |
3669 } } // namespace v8::internal | 3692 } } // namespace v8::internal |
3670 | 3693 |
3671 #endif // V8_TARGET_ARCH_ARM | 3694 #endif // V8_TARGET_ARCH_ARM |
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