Move atomic ops and related files to base library

src/base/atomicops_internals_arm_gcc.h

 // Copyright 2010 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // This file is an internal atomic implementation, use atomicops.h instead.
 //
 // LinuxKernelCmpxchg and Barrier_AtomicIncrement are from Google Gears.
 
-#ifndef V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
-#define V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
+#ifndef V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
+#define V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_
 
 #if defined(__QNXNTO__)
 #include <sys/cpuinline.h>
 #endif
 
 namespace v8 {
-namespace internal {
+namespace base {
 
 // Memory barriers on ARM are funky, but the kernel is here to help:
 //
 // * ARMv5 didn't support SMP, there is no memory barrier instruction at
 //   all on this architecture, or when targeting its machine code.
 //
 // * Some ARMv6 CPUs support SMP. A full memory barrier can be produced by
 //   writing a random value to a very specific coprocessor register.
 //
 // * On ARMv7, the "dmb" instruction is used to perform a full memory
@@ skipping 261 matching lines @@
 }
 
 // Byte accessors.
 
 inline void NoBarrier_Store(volatile Atomic8* ptr, Atomic8 value) {
   *ptr = value;
 }
 
 inline Atomic8 NoBarrier_Load(volatile const Atomic8* ptr) { return *ptr; }
 
-} }  // namespace v8::internal
+} }  // namespace v8::bae

[Jakob Kummerow, 2014/06/05 11:49:06]

nit: typo

 
-#endif  // V8_ATOMICOPS_INTERNALS_ARM_GCC_H_
+#endif  // V8_BASE_ATOMICOPS_INTERNALS_ARM_GCC_H_