Index: src/mips/assembler-mips.cc |
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc |
index 9b07a435afa94b35116f24c797e40ea0354cf9c6..6716ecda9656b8887cdece9e695ab2ba18f8d7ab 100644 |
--- a/src/mips/assembler-mips.cc |
+++ b/src/mips/assembler-mips.cc |
@@ -250,28 +250,30 @@ static const int kNegOffset = 0x00008000; |
// addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) |
// operations as post-increment of sp. |
const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift) |
- | (kRegister_sp_Code << kRtShift) | (kPointerSize & kImm16Mask); |
+ | (kRegister_sp_Code << kRtShift) |
+ | (kPointerSize & kImm16Mask); // NOLINT |
// addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. |
const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift) |
- | (kRegister_sp_Code << kRtShift) | (-kPointerSize & kImm16Mask); |
+ | (kRegister_sp_Code << kRtShift) |
+ | (-kPointerSize & kImm16Mask); // NOLINT |
// sw(r, MemOperand(sp, 0)) |
const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift) |
- | (0 & kImm16Mask); |
+ | (0 & kImm16Mask); // NOLINT |
// lw(r, MemOperand(sp, 0)) |
const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift) |
- | (0 & kImm16Mask); |
+ | (0 & kImm16Mask); // NOLINT |
const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
- | (0 & kImm16Mask); |
+ | (0 & kImm16Mask); // NOLINT |
const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
- | (0 & kImm16Mask); |
+ | (0 & kImm16Mask); // NOLINT |
const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
- | (kNegOffset & kImm16Mask); |
+ | (kNegOffset & kImm16Mask); // NOLINT |
const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
- | (kNegOffset & kImm16Mask); |
+ | (kNegOffset & kImm16Mask); // NOLINT |
// A mask for the Rt register for push, pop, lw, sw instructions. |
const Instr kRtMask = kRtFieldMask; |
const Instr kLwSwInstrTypeMask = 0xffe00000; |