Add LoadTaggedClassIdMayBeSmi to assembly and improve performance of inline cache stubs.

runtime/vm/stub_code_mips.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_MIPS)
 
 #include "vm/assembler.h"
 #include "vm/code_generator.h"
 #include "vm/compiler.h"
@@ skipping 1427 matching lines @@
     __ addiu(SP, SP, Immediate(2 * kWordSize));
     __ LeaveStubFrame();
     __ Bind(&not_stepping);
   }
 
   // Load argument descriptor into S4.
   __ lw(S4, FieldAddress(S5, ICData::arguments_descriptor_offset()));
   // Preserve return address, since RA is needed for subroutine call.
   __ mov(T2, RA);
   // Loop that checks if there is an IC data match.
-  Label loop, update, test, found, get_class_id_as_smi;
+  Label loop, update, test, found;
   // S5: IC data object (preserved).
   __ lw(T0, FieldAddress(S5, ICData::ic_data_offset()));
   // T0: ic_data_array with check entries: classes and target functions.
   __ AddImmediate(T0, Array::data_offset() - kHeapObjectTag);
   // T0: points directly to the first ic data array element.
 
   // Get the receiver's class ID (first read number of arguments from
   // arguments descriptor array and then access the receiver from the stack).
   __ lw(T1, FieldAddress(S4, ArgumentsDescriptor::count_offset()));
   __ LoadImmediate(TMP, Smi::RawValue(1));
   __ subu(T1, T1, TMP);
   __ sll(T3, T1, 1);  // T1 (argument_count - 1) is smi.
   __ addu(T3, T3, SP);
-  __ bal(&get_class_id_as_smi);
-  __ delay_slot()->lw(T3, Address(T3));
+  __ lw(T3, Address(T3));
+  __ LoadTaggedClassIdMayBeSmi(T3, T3);
+
   // T1: argument_count - 1 (smi).
   // T3: receiver's class ID (smi).
   __ b(&test);
   __ delay_slot()->lw(T4, Address(T0));  // First class id (smi) to check.
 
   __ Bind(&loop);
   for (int i = 0; i < num_args; i++) {
     if (i > 0) {
       // If not the first, load the next argument's class ID.
       __ LoadImmediate(T3, Smi::RawValue(-i));
       __ addu(T3, T1, T3);
       __ sll(T3, T3, 1);
       __ addu(T3, SP, T3);
-      __ bal(&get_class_id_as_smi);
-      __ delay_slot()->lw(T3, Address(T3));
+      __ lw(T3, Address(T3));
+      __ LoadTaggedClassIdMayBeSmi(T3, T3);
       // T3: next argument class ID (smi).
       __ lw(T4, Address(T0, i * kWordSize));
       // T4: next class ID to check (smi).
     }
     if (i < (num_args - 1)) {
       __ bne(T3, T4, &update);  // Continue.
     } else {
       // Last check, all checks before matched.
       Label skip;
       __ bne(T3, T4, &skip);
       __ b(&found);  // Break.
       __ delay_slot()->mov(RA, T2);  // Restore return address if found.
       __ Bind(&skip);
     }
   }
   __ Bind(&update);
   // Reload receiver class ID.  It has not been destroyed when num_args == 1.
   if (num_args > 1) {
     __ sll(T3, T1, 1);
     __ addu(T3, T3, SP);
-    __ bal(&get_class_id_as_smi);
-    __ delay_slot()->lw(T3, Address(T3));
+    __ lw(T3, Address(T3));
+    __ LoadTaggedClassIdMayBeSmi(T3, T3);
   }
 
   const intptr_t entry_size = ICData::TestEntryLengthFor(num_args) * kWordSize;
   __ AddImmediate(T0, entry_size);  // Next entry.
   __ lw(T4, Address(T0));  // Next class ID.
 
   __ Bind(&test);
   __ BranchNotEqual(T4, Smi::RawValue(kIllegalCid), &loop);  // Done?
 
   // IC miss.
@@ skipping 54 matching lines @@
   __ LoadImmediate(T1, Smi::RawValue(Smi::kMaxValue));
   __ sw(T1, Address(T0, count_offset));
 
   __ Bind(&call_target_function);
   // T0 <- T3: Target function.
   __ mov(T0, T3);
   Label is_compiled;
   __ lw(T4, FieldAddress(T0, Function::instructions_offset()));
   __ AddImmediate(T4, Instructions::HeaderSize() - kHeapObjectTag);
   __ jr(T4);
-
-  // Instance in T3, return its class-id in T3 as Smi.
-  __ Bind(&get_class_id_as_smi);
-  Label not_smi;
-  // Test if Smi -> load Smi class for comparison.
-  __ andi(CMPRES1, T3, Immediate(kSmiTagMask));
-  __ bne(CMPRES1, ZR, &not_smi);
-  __ jr(RA);
-  __ delay_slot()->addiu(T3, ZR, Immediate(Smi::RawValue(kSmiCid)));
-
-  __ Bind(&not_smi);
-  __ LoadClassId(T3, T3);
-  __ jr(RA);
-  __ delay_slot()->SmiTag(T3);
 }
 
 
 // Use inline cache data array to invoke the target or continue in inline
 // cache miss handler. Stub for 1-argument check (receiver class).
 //  RA: Return address.
 //  S5: Inline cache data object.
 // Inline cache data object structure:
 // 0: function-name
 // 1: N, number of arguments checked.
@@ skipping 493 matching lines @@
   const Register right = T0;
   __ lw(left, Address(SP, 1 * kWordSize));
   __ lw(right, Address(SP, 0 * kWordSize));
   GenerateIdenticalWithNumberCheckStub(assembler, left, right, temp1, temp2);
   __ Ret();
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_MIPS