Add LoadTaggedClassIdMayBeSmi to assembly and improve performance of inline cache stubs.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 1667 matching lines @@
 
 
 void Assembler::CompareClassId(Register object,
                                intptr_t class_id,
                                Register scratch) {
   LoadClassId(scratch, object);
   CompareImmediate(scratch, class_id);
 }
 
 
+void Assembler::LoadTaggedClassIdMayBeSmi(Register result, Register object) {

[zra, 2014/06/04 18:55:00]

tst(object, Operand(kSmiTagMask));
LoadImmediate(result, Smi::RawValue(kSmiCid), EQ);
LoadClassId(result, object, NE);
SmiTag(result, NE);

[srdjan, 2014/06/04 20:08:04]

Done and added condition to LoadClassId

+  Label load, done;
+  tst(object, Operand(kSmiTagMask));
+  b(&load, NE);
+  LoadImmediate(result, Smi::RawValue(kSmiCid));
+  b(&done);
+  Bind(&load);
+  LoadClassId(result, object);
+  SmiTag(result);
+  Bind(&done);
+}
+
+
 static bool CanEncodeBranchOffset(int32_t offset) {
   ASSERT(Utils::IsAligned(offset, 4));
   return Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset);
 }
 
 
 int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
   // The offset is off by 8 due to the way the ARM CPUs read PC.
   offset -= Instr::kPCReadOffset;
 
@@ skipping 1493 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM