ARM: Use the shifter operand to merge in previous shift instructions.

src/arm/lithium-codegen-arm.cc

Index: src/arm/lithium-codegen-arm.cc
diff --git a/src/arm/lithium-codegen-arm.cc b/src/arm/lithium-codegen-arm.cc
index 40747c868c36751f0b76c105bbf0c2abf972683b..bff8a2431b37584318135e513535692074afe068 100644
--- a/src/arm/lithium-codegen-arm.cc
+++ b/src/arm/lithium-codegen-arm.cc
@@ -480,6 +480,19 @@ bool LCodeGen::IsInteger32(LConstantOperand* op) const {
 }
 
 
+template<class LI>
+Operand LCodeGen::ToShiftedRightOperand(LOperand* right, LI* shift_info) {
+  if (shift_info->shift() == NO_SHIFT) {
+    return ToOperand(right);
+  } else {
+    return Operand(
+        ToRegister(right),
+        shift_info->shift(),
+        JSShiftAmountFromLConstant(shift_info->shift_amount()));
+  }
+}
+
+
 bool LCodeGen::IsSmi(LConstantOperand* op) const {
   return chunk_->LookupLiteralRepresentation(op).IsSmi();
 }
@@ -1710,11 +1723,15 @@ void LCodeGen::DoBitI(LBitI* instr) {
   Register result = ToRegister(instr->result());
   Operand right(no_reg);
 
+  ASSERT(right_op->IsRegister() || (instr->shift() == NO_SHIFT));
+
   if (right_op->IsStackSlot()) {
     right = Operand(EmitLoadRegister(right_op, ip));
-  } else {
-    ASSERT(right_op->IsRegister() || right_op->IsConstantOperand());
+  } else if (right_op->IsConstantOperand()) {
     right = ToOperand(right_op);

[ulan, 2014/06/10 11:53:37]

Doesn't ToShiftedRightOperand take care of this case?

[Alexandre Rames, 2014/06/11 10:19:40]

It does. Removed the constant case.

+  } else {
+    ASSERT(right_op->IsRegister());
+    right = ToShiftedRightOperand(right_op, instr);
   }
 
   switch (instr->op()) {
@@ -1833,12 +1850,15 @@ void LCodeGen::DoSubI(LSubI* instr) {
   bool can_overflow = instr->hydrogen()->CheckFlag(HValue::kCanOverflow);
   SBit set_cond = can_overflow ? SetCC : LeaveCC;
 
+  ASSERT(right->IsRegister() || (instr->shift() == NO_SHIFT));
+
   if (right->IsStackSlot()) {
     Register right_reg = EmitLoadRegister(right, ip);
     __ sub(ToRegister(result), ToRegister(left), Operand(right_reg), set_cond);
   } else {
     ASSERT(right->IsRegister() || right->IsConstantOperand());
-    __ sub(ToRegister(result), ToRegister(left), ToOperand(right), set_cond);
+    __ sub(ToRegister(result), ToRegister(left),
+           ToShiftedRightOperand(right, instr), set_cond);
   }
 
   if (can_overflow) {
@@ -2027,12 +2047,15 @@ void LCodeGen::DoAddI(LAddI* instr) {
   bool can_overflow = instr->hydrogen()->CheckFlag(HValue::kCanOverflow);
   SBit set_cond = can_overflow ? SetCC : LeaveCC;
 
+  ASSERT(right->IsRegister() || (instr->shift() == NO_SHIFT));
+
   if (right->IsStackSlot()) {
     Register right_reg = EmitLoadRegister(right, ip);
     __ add(ToRegister(result), ToRegister(left), Operand(right_reg), set_cond);
   } else {
     ASSERT(right->IsRegister() || right->IsConstantOperand());
-    __ add(ToRegister(result), ToRegister(left), ToOperand(right), set_cond);
+    __ add(ToRegister(result), ToRegister(left),
+           ToShiftedRightOperand(right, instr), set_cond);
   }
 
   if (can_overflow) {