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Issue 312173002: ARM: Use the shifter operand to merge in previous shift instructions. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Address Ulan's comments Created 6 years, 6 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM_CONSTANTS_ARM_H_ 5 #ifndef V8_ARM_CONSTANTS_ARM_H_
6 #define V8_ARM_CONSTANTS_ARM_H_ 6 #define V8_ARM_CONSTANTS_ARM_H_
7 7
8 // ARM EABI is required. 8 // ARM EABI is required.
9 #if defined(__arm__) && !defined(__ARM_EABI__) 9 #if defined(__arm__) && !defined(__ARM_EABI__)
10 #error ARM EABI support is required. 10 #error ARM EABI support is required.
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229 LSL = 0 << 5, // Logical shift left. 229 LSL = 0 << 5, // Logical shift left.
230 LSR = 1 << 5, // Logical shift right. 230 LSR = 1 << 5, // Logical shift right.
231 ASR = 2 << 5, // Arithmetic shift right. 231 ASR = 2 << 5, // Arithmetic shift right.
232 ROR = 3 << 5, // Rotate right. 232 ROR = 3 << 5, // Rotate right.
233 233
234 // RRX is encoded as ROR with shift_imm == 0. 234 // RRX is encoded as ROR with shift_imm == 0.
235 // Use a special code to make the distinction. The RRX ShiftOp is only used 235 // Use a special code to make the distinction. The RRX ShiftOp is only used
236 // as an argument, and will never actually be encoded. The Assembler will 236 // as an argument, and will never actually be encoded. The Assembler will
237 // detect it and emit the correct ROR shift operand with shift_imm == 0. 237 // detect it and emit the correct ROR shift operand with shift_imm == 0.
238 RRX = -1, 238 RRX = -1,
239 NO_SHIFT = -2,
239 kNumberOfShifts = 4 240 kNumberOfShifts = 4
240 }; 241 };
241 242
242 243
243 // Status register fields. 244 // Status register fields.
244 enum SRegisterField { 245 enum SRegisterField {
245 CPSR_c = CPSR | 1 << 16, 246 CPSR_c = CPSR | 1 << 16,
246 CPSR_x = CPSR | 1 << 17, 247 CPSR_x = CPSR | 1 << 17,
247 CPSR_s = CPSR | 1 << 18, 248 CPSR_s = CPSR | 1 << 18,
248 CPSR_f = CPSR | 1 << 19, 249 CPSR_f = CPSR | 1 << 19,
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741 static int Number(const char* name, bool* is_double); 742 static int Number(const char* name, bool* is_double);
742 743
743 private: 744 private:
744 static const char* names_[kNumVFPRegisters]; 745 static const char* names_[kNumVFPRegisters];
745 }; 746 };
746 747
747 748
748 } } // namespace v8::internal 749 } } // namespace v8::internal
749 750
750 #endif // V8_ARM_CONSTANTS_ARM_H_ 751 #endif // V8_ARM_CONSTANTS_ARM_H_
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