Fixes to run "Hello, world!" on arm64 hardware.

runtime/vm/simulator_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <math.h>  // for isnan.
 #include <setjmp.h>
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
@@ skipping 645 matching lines @@
   Simulator* simulator = Isolate::Current()->simulator();
   if (simulator == NULL) {
     simulator = new Simulator();
     Isolate::Current()->set_simulator(simulator);
   }
   return simulator;
 }
 
 
 // Sets the register in the architecture state.
-void Simulator::set_register(Register reg, int64_t value, R31Type r31t) {
-  // register is in range, and if it is R31, a mode is specified.
+void Simulator::set_register(
+    Instr* instr, Register reg, int64_t value, R31Type r31t) {
+  // Register is in range.
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   if ((reg != R31) || (r31t != R31IsZR)) {
     registers_[reg] = value;
+    // If we're setting CSP, make sure it is 16-byte aligned. In truth, CSP
+    // can store addresses that are not 16-byte aligned, but loads and stores
+    // are not allowed through CSP when it is not aligned. Thus, this check is
+    // more conservative that necessary. However, it will likely be more
+    // useful to find the program locations where CSP is set to a bad value,
+    // than to find only the resulting loads/stores that would cause a fault on
+    // hardware.
+    if ((instr != NULL) && (reg == R31) && !Utils::IsAligned(value, 16)) {
+      UnalignedAccess("CSP set", value, instr);
+    }
   }
 }
 
 
 // Get the register from the architecture state.
 int64_t Simulator::get_register(Register reg, R31Type r31t) const {
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   if ((reg == R31) && (r31t == R31IsZR)) {
     return 0;
   } else {
@@ skipping 346 matching lines @@
 void Simulator::DecodeMoveWide(Instr* instr) {
   const Register rd = instr->RdField();
   const int hw = instr->HWField();
   const int64_t shift = hw << 4;
   const int64_t shifted_imm =
       static_cast<int64_t>(instr->Imm16Field()) << shift;
 
   if (instr->SFField()) {
     if (instr->Bits(29, 2) == 0) {
       // Format(instr, "movn'sf 'rd, 'imm16 'hw");
-      set_register(rd, ~shifted_imm, instr->RdMode());
+      set_register(instr, rd, ~shifted_imm, instr->RdMode());
     } else if (instr->Bits(29, 2) == 2) {
       // Format(instr, "movz'sf 'rd, 'imm16 'hw");
-      set_register(rd, shifted_imm, instr->RdMode());
+      set_register(instr, rd, shifted_imm, instr->RdMode());
     } else if (instr->Bits(29, 2) == 3) {
       // Format(instr, "movk'sf 'rd, 'imm16 'hw");
       const int64_t rd_val = get_register(rd, instr->RdMode());
       const int64_t result = (rd_val & ~(0xffffL << shift)) | shifted_imm;
-      set_register(rd, result, instr->RdMode());
+      set_register(instr, rd, result, instr->RdMode());
     } else {
       UnimplementedInstruction(instr);
     }
   } else if ((hw & 0x2) == 0) {
     if (instr->Bits(29, 2) == 0) {
       // Format(instr, "movn'sf 'rd, 'imm16 'hw");
       set_wregister(rd, ~shifted_imm & kWRegMask,  instr->RdMode());
     } else if (instr->Bits(29, 2) == 2) {
       // Format(instr, "movz'sf 'rd, 'imm16 'hw");
       set_wregister(rd, shifted_imm & kWRegMask, instr->RdMode());
@@ skipping 17 matching lines @@
   // Format(instr, "addi'sf's 'rd, 'rn, 'imm12s");
   // Format(instr, "subi'sf's 'rd, 'rn, 'imm12s");
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
                                              : (instr->Imm12Field());
   if (instr->SFField()) {
     // 64-bit add.
     const int64_t rn_val = get_register(rn, instr->RnMode());
     const int64_t alu_out = addition ? (rn_val + imm) : (rn_val - imm);
-    set_register(rd, alu_out, instr->RdMode());
+    set_register(instr, rd, alu_out, instr->RdMode());
     if (instr->HasS()) {
       SetNZFlagsX(alu_out);
       if (addition) {
         SetCFlag(CarryFromX(rn_val, imm));
       } else {
         SetCFlag(!BorrowFromX(rn_val, imm));
       }
       SetVFlag(OverflowFromX(alu_out, rn_val, imm, addition));
     }
   } else {
@@ skipping 50 matching lines @@
     if (out_size == kXRegSizeInBits) {
       SetNZFlagsX(alu_out);
     } else {
       SetNZFlagsW(alu_out);
     }
     SetCFlag(false);
     SetVFlag(false);
   }
 
   if (out_size == kXRegSizeInBits) {
-    set_register(rd, alu_out, instr->RdMode());
+    set_register(instr, rd, alu_out, instr->RdMode());
   } else {
     set_wregister(rd, alu_out, instr->RdMode());
   }
 }
 
 
 void Simulator::DecodePCRel(Instr* instr) {
   const int op = instr->Bit(31);
   if (op == 0) {
     // Format(instr, "adr 'rd, 'pcrel")
     const Register rd = instr->RdField();
     const int64_t immhi = instr->SImm19Field();
     const int64_t immlo = instr->Bits(29, 2);
     const int64_t off = (immhi << 2) | immlo;
     const int64_t dest = get_pc() + off;
-    set_register(rd, dest, instr->RdMode());
+    set_register(instr, rd, dest, instr->RdMode());
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeDPImmediate(Instr* instr) {
   if (instr->IsMoveWideOp()) {
     DecodeMoveWide(instr);
   } else if (instr->IsAddSubImmOp()) {
@@ skipping 99 matching lines @@
       OS::Print("Call to host function at 0x%" Pd "\n", external);
     }
 
     if ((redirection->call_kind() == kRuntimeCall) ||
         (redirection->call_kind() == kBootstrapNativeCall) ||
         (redirection->call_kind() == kNativeCall)) {
       // Set the top_exit_frame_info of this simulator to the native stack.
       set_top_exit_frame_info(reinterpret_cast<uword>(&buffer));
     }
     if (redirection->call_kind() == kRuntimeCall) {
-      NativeArguments arguments;
-      ASSERT(sizeof(NativeArguments) == 4*kWordSize);
-      arguments.isolate_ = reinterpret_cast<Isolate*>(get_register(R0));
-      arguments.argc_tag_ = get_register(R1);
-      arguments.argv_ = reinterpret_cast<RawObject*(*)[]>(get_register(R2));
-      arguments.retval_ = reinterpret_cast<RawObject**>(get_register(R3));
+      NativeArguments* arguments =
+          reinterpret_cast<NativeArguments*>(get_register(R0));
       SimulatorRuntimeCall target =
           reinterpret_cast<SimulatorRuntimeCall>(external);
-      target(arguments);
-      set_register(R0, icount_);  // Zap result register from void function.
-      set_register(R1, icount_);
+      target(*arguments);
+      // Zap result register from void function.
+      set_register(instr, R0, icount_);
+      set_register(instr, R1, icount_);
     } else if (redirection->call_kind() == kLeafRuntimeCall) {
       ASSERT((0 <= redirection->argument_count()) &&
              (redirection->argument_count() <= 8));
       SimulatorLeafRuntimeCall target =
           reinterpret_cast<SimulatorLeafRuntimeCall>(external);
       const int64_t r0 = get_register(R0);
       const int64_t r1 = get_register(R1);
       const int64_t r2 = get_register(R2);
       const int64_t r3 = get_register(R3);
       const int64_t r4 = get_register(R4);
       const int64_t r5 = get_register(R5);
       const int64_t r6 = get_register(R6);
       const int64_t r7 = get_register(R7);
       const int64_t res = target(r0, r1, r2, r3, r4, r5, r6, r7);
-      set_register(R0, res);  // Set returned result from function.
-      set_register(R1, icount_);  // Zap unused result register.
+      set_register(instr, R0, res);  // Set returned result from function.
+      set_register(instr, R1, icount_);  // Zap unused result register.
     } else if (redirection->call_kind() == kLeafFloatRuntimeCall) {
       ASSERT((0 <= redirection->argument_count()) &&
              (redirection->argument_count() <= 8));
       SimulatorLeafFloatRuntimeCall target =
           reinterpret_cast<SimulatorLeafFloatRuntimeCall>(external);
       const double d0 = bit_cast<double, int64_t>(get_vregisterd(V0, 0));
       const double d1 = bit_cast<double, int64_t>(get_vregisterd(V1, 0));
       const double d2 = bit_cast<double, int64_t>(get_vregisterd(V2, 0));
       const double d3 = bit_cast<double, int64_t>(get_vregisterd(V3, 0));
       const double d4 = bit_cast<double, int64_t>(get_vregisterd(V4, 0));
       const double d5 = bit_cast<double, int64_t>(get_vregisterd(V5, 0));
       const double d6 = bit_cast<double, int64_t>(get_vregisterd(V6, 0));
       const double d7 = bit_cast<double, int64_t>(get_vregisterd(V7, 0));
       const double res = target(d0, d1, d2, d3, d4, d5, d6, d7);
       set_vregisterd(V0, 0, bit_cast<int64_t, double>(res));
       set_vregisterd(V0, 1, 0);
     } else if (redirection->call_kind() == kBootstrapNativeCall) {
       NativeArguments* arguments;
       arguments = reinterpret_cast<NativeArguments*>(get_register(R0));
       SimulatorBootstrapNativeCall target =
           reinterpret_cast<SimulatorBootstrapNativeCall>(external);
       target(arguments);
-      set_register(R0, icount_);  // Zap result register from void function.
+      // Zap result register from void function.
+      set_register(instr, R0, icount_);
     } else {
       ASSERT(redirection->call_kind() == kNativeCall);
       NativeArguments* arguments;
       arguments = reinterpret_cast<NativeArguments*>(get_register(R0));
       uword target_func = get_register(R1);
       SimulatorNativeCall target =
           reinterpret_cast<SimulatorNativeCall>(external);
       target(arguments, target_func);
-      set_register(R0, icount_);  // Zap result register from void function.
-      set_register(R1, icount_);
+      // Zap result register from void function.
+      set_register(instr, R0, icount_);
+      set_register(instr, R1, icount_);
     }
     set_top_exit_frame_info(0);
 
     // Zap caller-saved registers, since the actual runtime call could have
     // used them.
-    set_register(R2, icount_);
-    set_register(R3, icount_);
-    set_register(R4, icount_);
-    set_register(R5, icount_);
-    set_register(R6, icount_);
-    set_register(R7, icount_);
-    set_register(R8, icount_);
-    set_register(R9, icount_);
-    set_register(R10, icount_);
-    set_register(R11, icount_);
-    set_register(R12, icount_);
-    set_register(R13, icount_);
-    set_register(R14, icount_);
-    set_register(R15, icount_);
-    set_register(IP0, icount_);
-    set_register(IP1, icount_);
-    set_register(R18, icount_);
-    set_register(LR, icount_);
+    set_register(instr, R2, icount_);
+    set_register(instr, R3, icount_);
+    set_register(instr, R4, icount_);
+    set_register(instr, R5, icount_);
+    set_register(instr, R6, icount_);
+    set_register(instr, R7, icount_);
+    set_register(instr, R8, icount_);
+    set_register(instr, R9, icount_);
+    set_register(instr, R10, icount_);
+    set_register(instr, R11, icount_);
+    set_register(instr, R12, icount_);
+    set_register(instr, R13, icount_);
+    set_register(instr, R14, icount_);
+    set_register(instr, R15, icount_);
+    set_register(instr, IP0, icount_);
+    set_register(instr, IP1, icount_);
+    set_register(instr, R18, icount_);
+    set_register(instr, LR, icount_);
 
     // TODO(zra): Zap caller-saved fpu registers.
 
     // Return.
     set_pc(saved_lr);
   } else {
     // Coming via long jump from a throw. Continue to exception handler.
     set_top_exit_frame_info(0);
   }
 }
@@ skipping 67 matching lines @@
 }
 
 
 void Simulator::DecodeUnconditionalBranch(Instr* instr) {
   const bool link = instr->Bit(31) == 1;
   const int64_t imm26 = instr->SImm26Field();
   const int64_t dest = get_pc() + (imm26 << 2);
   const int64_t ret = get_pc() + Instr::kInstrSize;
   set_pc(dest);
   if (link) {
-    set_register(LR, ret);
+    set_register(instr, LR, ret);
   }
 }
 
 
 void Simulator::DecodeUnconditionalBranchReg(Instr* instr) {
   if ((instr->Bits(0, 5) == 0) && (instr->Bits(10, 6) == 0) &&
       (instr->Bits(16, 5) == 0x1f)) {
     switch (instr->Bits(21, 4)) {
       case 0: {
         // Format(instr, "br 'rn");
         const Register rn = instr->RnField();
         const int64_t dest = get_register(rn, instr->RnMode());
         set_pc(dest);
         break;
       }
       case 1: {
         // Format(instr, "blr 'rn");
         const Register rn = instr->RnField();
         const int64_t dest = get_register(rn, instr->RnMode());
         const int64_t ret = get_pc() + Instr::kInstrSize;
         set_pc(dest);
-        set_register(LR, ret);
+        set_register(instr, LR, ret);
         break;
       }
       case 2: {
         // Format(instr, "ret 'rn");
         const Register rn = instr->RnField();
         const int64_t rn_val = get_register(rn, instr->RnMode());
         set_pc(rn_val);
         break;
       }
       default:
@@ skipping 203 matching lines @@
           break;
         default:
           UNREACHABLE();
           break;
       }
 
       // Write to register.
       if (use_w) {
         set_wregister(rt, static_cast<int32_t>(val), R31IsZR);
       } else {
-        set_register(rt, val, R31IsZR);
+        set_register(instr, rt, val, R31IsZR);
       }
     }
   }
 
   // Do writeback.
   if (wb) {
-    set_register(rn, wb_address, R31IsSP);
+    set_register(instr, rn, wb_address, R31IsSP);
   }
 }
 
 
 void Simulator::DecodeLoadRegLiteral(Instr* instr) {
   if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) ||
       (instr->Bits(24, 3) != 0)) {
     UnimplementedInstruction(instr);
   }
 
   const Register rt = instr->RtField();
   const int64_t off = instr->SImm19Field() << 2;
   const int64_t pc = reinterpret_cast<int64_t>(instr);
   const int64_t address = pc + off;
   const int64_t val = ReadX(address, instr);
   if (instr->Bit(30)) {
     // Format(instr, "ldrx 'rt, 'pcldr");
-    set_register(rt, val, R31IsZR);
+    set_register(instr, rt, val, R31IsZR);
   } else {
     // Format(instr, "ldrw 'rt, 'pcldr");
     set_wregister(rt, static_cast<int32_t>(val), R31IsZR);
   }
 }
 
 
 void Simulator::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
@@ skipping 102 matching lines @@
   const int64_t rm_val = DecodeShiftExtendOperand(instr);
   if (instr->SFField()) {
     // 64-bit add.
     const int64_t rn_val = get_register(rn, instr->RnMode());
     int64_t alu_out = 0;
     if (subtract) {
       alu_out = rn_val - rm_val;
     } else {
       alu_out = rn_val + rm_val;
     }
-    set_register(rd, alu_out, instr->RdMode());
+    set_register(instr, rd, alu_out, instr->RdMode());
     if (instr->HasS()) {
       SetNZFlagsX(alu_out);
       if (subtract) {
         SetCFlag(!BorrowFromX(rn_val, rm_val));
       } else {
         SetCFlag(CarryFromX(rn_val, rm_val));
       }
       SetVFlag(OverflowFromX(alu_out, rn_val, rm_val, !subtract));
     }
   } else {
@@ skipping 70 matching lines @@
     if (instr->SFField() == 1) {
       SetNZFlagsX(alu_out);
     } else {
       SetNZFlagsW(alu_out);
     }
     SetCFlag(false);
     SetVFlag(false);
   }
 
   if (instr->SFField() == 1) {
-    set_register(rd, alu_out, instr->RdMode());
+    set_register(instr, rd, alu_out, instr->RdMode());
   } else {
     set_wregister(rd, alu_out & kWRegMask, instr->RdMode());
   }
 }
 
 
 static int64_t divide64(int64_t top, int64_t bottom, bool signd) {
   // ARM64 does not trap on integer division by zero. The destination register
   // is instead set to 0.
   if (bottom == 0) {
@@ skipping 52 matching lines @@
   const int64_t rm_val64 = get_register(rm, R31IsZR);
   const int32_t rn_val32 = get_wregister(rn, R31IsZR);
   const int32_t rm_val32 = get_wregister(rm, R31IsZR);
   switch (op) {
     case 2:
     case 3: {
       // Format(instr, "udiv'sf 'rd, 'rn, 'rm");
       // Format(instr, "sdiv'sf 'rd, 'rn, 'rm");
       const bool signd = instr->Bit(10) == 1;
       if (instr->SFField() == 1) {
-        set_register(rd, divide64(rn_val64, rm_val64, signd), R31IsZR);
+        set_register(instr, rd, divide64(rn_val64, rm_val64, signd), R31IsZR);
       } else {
         set_wregister(rd, divide32(rn_val32, rm_val32, signd), R31IsZR);
       }
       break;
     }
     case 8: {
       // Format(instr, "lsl'sf 'rd, 'rn, 'rm");
       if (instr->SFField() == 1) {
         const int64_t alu_out = rn_val64 << (rm_val64 & (kXRegSizeInBits - 1));
-        set_register(rd, alu_out, R31IsZR);
+        set_register(instr, rd, alu_out, R31IsZR);
       } else {
         const int32_t alu_out = rn_val32 << (rm_val32 & (kXRegSizeInBits - 1));
         set_wregister(rd, alu_out, R31IsZR);
       }
       break;
     }
     case 9: {
       // Format(instr, "lsr'sf 'rd, 'rn, 'rm");
       if (instr->SFField() == 1) {
         const uint64_t rn_u64 = static_cast<uint64_t>(rn_val64);
         const int64_t alu_out = rn_u64 >> (rm_val64 & (kXRegSizeInBits - 1));
-        set_register(rd, alu_out, R31IsZR);
+        set_register(instr, rd, alu_out, R31IsZR);
       } else {
         const uint32_t rn_u32 = static_cast<uint32_t>(rn_val32);
         const int32_t alu_out = rn_u32 >> (rm_val32 & (kXRegSizeInBits - 1));
         set_wregister(rd, alu_out, R31IsZR);
       }
       break;
     }
     case 10: {
       // Format(instr, "asr'sf 'rd, 'rn, 'rm");
       if (instr->SFField() == 1) {
         const int64_t alu_out = rn_val64 >> (rm_val64 & (kXRegSizeInBits - 1));
-        set_register(rd, alu_out, R31IsZR);
+        set_register(instr, rd, alu_out, R31IsZR);
       } else {
         const int32_t alu_out = rn_val32 >> (rm_val32 & (kXRegSizeInBits - 1));
         set_wregister(rd, alu_out, R31IsZR);
       }
       break;
     }
     default:
       UnimplementedInstruction(instr);
       break;
   }
 }
 
 
 void Simulator::DecodeMiscDP3Source(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
   const Register ra = instr->RaField();
   if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) &&
       (instr->Bit(15) == 0)) {
     // Format(instr, "madd'sf 'rd, 'rn, 'rm, 'ra");
     if (instr->SFField() == 1) {
       const int64_t rn_val = get_register(rn, R31IsZR);
       const int64_t rm_val = get_register(rm, R31IsZR);
       const int64_t ra_val = get_register(ra, R31IsZR);
       const int64_t alu_out = ra_val + (rn_val * rm_val);
-      set_register(rd, alu_out, R31IsZR);
+      set_register(instr, rd, alu_out, R31IsZR);
     } else {
       const int32_t rn_val = get_wregister(rn, R31IsZR);
       const int32_t rm_val = get_wregister(rm, R31IsZR);
       const int32_t ra_val = get_wregister(ra, R31IsZR);
       const int32_t alu_out = ra_val + (rn_val * rm_val);
       set_wregister(rd, alu_out, R31IsZR);
     }
   } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) &&
              (instr->Bit(15) == 1)) {
     // Format(instr, "msub'sf 'rd, 'rn, 'rm, 'ra");
     if (instr->SFField() == 1) {
       const int64_t rn_val = get_register(rn, R31IsZR);
       const int64_t rm_val = get_register(rm, R31IsZR);
       const int64_t ra_val = get_register(ra, R31IsZR);
       const int64_t alu_out = ra_val - (rn_val * rm_val);
-      set_register(rd, alu_out, R31IsZR);
+      set_register(instr, rd, alu_out, R31IsZR);
     } else {
       const int32_t rn_val = get_wregister(rn, R31IsZR);
       const int32_t rm_val = get_wregister(rm, R31IsZR);
       const int32_t ra_val = get_wregister(ra, R31IsZR);
       const int32_t alu_out = ra_val - (rn_val * rm_val);
       set_wregister(rd, alu_out, R31IsZR);
     }
   } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 2) &&
              (instr->Bit(15) == 0)) {
     // Format(instr, "smulh 'rd, 'rn, 'rm");
     const int64_t rn_val = get_register(rn, R31IsZR);
     const int64_t rm_val = get_register(rm, R31IsZR);
     const __int128 res =
         static_cast<__int128>(rn_val) * static_cast<__int128>(rm_val);
     const int64_t alu_out = static_cast<int64_t>(res >> 64);
-    set_register(rd, alu_out, R31IsZR);
+    set_register(instr, rd, alu_out, R31IsZR);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeConditionalSelect(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
@@ skipping 27 matching lines @@
     if (ConditionallyExecute(instr)) {
       result64 = rn_val64;
       result32 = rn_val32;
     }
   } else {
     UnimplementedInstruction(instr);
     return;
   }
 
   if (instr->SFField() == 1) {
-    set_register(rd, result64, instr->RdMode());
+    set_register(instr, rd, result64, instr->RdMode());
   } else {
     set_wregister(rd, result32, instr->RdMode());
   }
 }
 
 
 void Simulator::DecodeDPRegister(Instr* instr) {
   if (instr->IsAddSubShiftExtOp()) {
     DecodeAddSubShiftExt(instr);
   } else if (instr->IsLogicalShiftOp()) {
@@ skipping 44 matching lines @@
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
   const Register rn = instr->RnField();
   const Register rd = instr->RdField();
   if ((op == 0) && (imm4 == 7)) {
     if (Q == 0) {
       // Format(instr, "vmovrs 'rd, 'vn'idx5");
       set_wregister(rd, get_vregisters(vn, idx5), R31IsZR);
     } else {
       // Format(instr, "vmovrd 'rd, 'vn'idx5");
-      set_register(rd, get_vregisterd(vn, idx5), R31IsZR);
+      set_register(instr, rd, get_vregisterd(vn, idx5), R31IsZR);
     }
   } else if ((Q == 1)  && (op == 0) && (imm4 == 0)) {
     // Format(instr, "vdup'csz 'vd, 'vn'idx5");
     if (element_bytes == 4) {
       for (int i = 0; i < 4; i++) {
         set_vregisters(vd, i, get_vregisters(vn, idx5));
       }
     } else if (element_bytes == 8) {
       for (int i = 0; i < 2; i++) {
         set_vregisterd(vd, i, get_vregisterd(vn, idx5));
@@ skipping 430 matching lines @@
   }
   if (instr->Bits(16, 5) == 2) {
     // Format(instr, "scvtfd 'vd, 'vn");
     const int64_t rn_val = get_register(rn, instr->RnMode());
     const double vn_dbl = static_cast<double>(rn_val);
     set_vregisterd(vd, 0, bit_cast<int64_t, double>(vn_dbl));
     set_vregisterd(vd, 1, 0);
   } else if (instr->Bits(16, 5) == 6) {
     // Format(instr, "fmovrd 'rd, 'vn");
     const int64_t vn_val = get_vregisterd(vn, 0);
-    set_register(rd, vn_val, R31IsZR);
+    set_register(instr, rd, vn_val, R31IsZR);
   } else if (instr->Bits(16, 5) == 7) {
     // Format(instr, "fmovdr 'vd, 'rn");
     const int64_t rn_val = get_register(rn, R31IsZR);
     set_vregisterd(vd, 0, rn_val);
     set_vregisterd(vd, 1, 0);
   } else if (instr->Bits(16, 5) == 24) {
     // Format(instr, "fcvtzds 'rd, 'vn");
     const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
-    set_register(rd, static_cast<int64_t>(vn_val), instr->RdMode());
+    set_register(instr, rd, static_cast<int64_t>(vn_val), instr->RdMode());
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
 
 void Simulator::DecodeFPOneSource(Instr* instr) {
   const int opc = instr->Bits(15, 6);
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
@@ skipping 238 matching lines @@
   if (fp_args) {
     set_vregisterd(V0, 0, parameter0);
     set_vregisterd(V0, 1, 0);
     set_vregisterd(V1, 0, parameter1);
     set_vregisterd(V1, 1, 0);
     set_vregisterd(V2, 0, parameter2);
     set_vregisterd(V2, 1, 0);
     set_vregisterd(V3, 0, parameter3);
     set_vregisterd(V3, 1, 0);
   } else {
-    set_register(R0, parameter0);
-    set_register(R1, parameter1);
-    set_register(R2, parameter2);
-    set_register(R3, parameter3);
+    set_register(NULL, R0, parameter0);
+    set_register(NULL, R1, parameter1);
+    set_register(NULL, R2, parameter2);
+    set_register(NULL, R3, parameter3);
   }
 
   // Make sure the activation frames are properly aligned.
   intptr_t stack_pointer = sp_before_call;
   if (OS::ActivationFrameAlignment() > 1) {
     stack_pointer =
         Utils::RoundDown(stack_pointer, OS::ActivationFrameAlignment());
   }
-  set_register(R31, stack_pointer, R31IsSP);
+  set_register(NULL, R31, stack_pointer, R31IsSP);
 
   // Prepare to execute the code at entry.
   set_pc(entry);
   // Put down marker for end of simulation. The simulator will stop simulation
   // when the PC reaches this value. By saving the "end simulation" value into
   // the LR the simulation stops when returning to this call point.
-  set_register(LR, kEndSimulatingPC);
+  set_register(NULL, LR, kEndSimulatingPC);
 
   // Remember the values of callee-saved registers, and set them up with a
   // known value so that we are able to check that they are preserved
   // properly across Dart execution.
   int64_t preserved_vals[kAbiPreservedCpuRegCount];
   const double dicount = static_cast<double>(icount_);
   const int64_t callee_saved_value = bit_cast<int64_t, double>(dicount);
   for (int i = kAbiFirstPreservedCpuReg; i <= kAbiLastPreservedCpuReg; i++) {
     const Register r = static_cast<Register>(i);
     preserved_vals[i - kAbiFirstPreservedCpuReg] = get_register(r);
-    set_register(r, callee_saved_value);
+    set_register(NULL, r, callee_saved_value);
   }
 
   // Only the bottom half of the V registers must be preserved.
   int64_t preserved_dvals[kAbiPreservedFpuRegCount];
   for (int i = kAbiFirstPreservedFpuReg; i <= kAbiLastPreservedFpuReg; i++) {
     const VRegister r = static_cast<VRegister>(i);
     preserved_dvals[i - kAbiFirstPreservedFpuReg] = get_vregisterd(r, 0);
     set_vregisterd(r, 0, callee_saved_value);
     set_vregisterd(r, 1, 0);
   }
 
   // Start the simulation.
   Execute();
 
   // Check that the callee-saved registers have been preserved,
   // and restore them with the original value.
   for (int i = kAbiFirstPreservedCpuReg; i <= kAbiLastPreservedCpuReg; i++) {
     const Register r = static_cast<Register>(i);
     ASSERT(callee_saved_value == get_register(r));
-    set_register(r, preserved_vals[i - kAbiFirstPreservedCpuReg]);
+    set_register(NULL, r, preserved_vals[i - kAbiFirstPreservedCpuReg]);
   }
 
   for (int i = kAbiFirstPreservedFpuReg; i <= kAbiLastPreservedFpuReg; i++) {
     const VRegister r = static_cast<VRegister>(i);
     ASSERT(callee_saved_value == get_vregisterd(r, 0));
     set_vregisterd(r, 0, preserved_dvals[i - kAbiFirstPreservedFpuReg]);
     set_vregisterd(r, 1, 0);
   }
 
   // Restore the SP register and return R0.
-  set_register(R31, sp_before_call, R31IsSP);
+  set_register(NULL, R31, sp_before_call, R31IsSP);
   int64_t return_value;
   if (fp_return) {
     return_value = get_vregisterd(V0, 0);
   } else {
     return_value = get_register(R0);
   }
   return return_value;
 }
 
 
@@ skipping 15 matching lines @@
   // in the previous C++ frames.
   uword native_sp = buf->native_sp();
   Isolate* isolate = Isolate::Current();
   while (isolate->top_resource() != NULL &&
          (reinterpret_cast<uword>(isolate->top_resource()) < native_sp)) {
     isolate->top_resource()->~StackResource();
   }
 
   // Unwind the C++ stack and continue simulation in the target frame.
   set_pc(static_cast<int64_t>(pc));
-  set_register(R31, static_cast<int64_t>(sp), R31IsSP);
-  set_register(FP, static_cast<int64_t>(fp));
+  set_register(NULL, SP, static_cast<int64_t>(sp));
+  set_register(NULL, FP, static_cast<int64_t>(fp));
 
   ASSERT(raw_exception != Object::null());
-  set_register(kExceptionObjectReg, bit_cast<int64_t>(raw_exception));
-  set_register(kStackTraceObjectReg, bit_cast<int64_t>(raw_stacktrace));
+  set_register(NULL, kExceptionObjectReg, bit_cast<int64_t>(raw_exception));
+  set_register(NULL, kStackTraceObjectReg, bit_cast<int64_t>(raw_stacktrace));
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(HOST_ARCH_ARM64)
 
 #endif  // defined TARGET_ARCH_ARM64