Fixes to run "Hello, world!" on arm64 hardware.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 11 matching lines @@
   R8  =  8,
   R9  =  9,
   R10 = 10,
   R11 = 11,
   R12 = 12,
   R13 = 13,
   R14 = 14,
   R15 = 15,
   R16 = 16,  // IP0 aka TMP
   R17 = 17,  // IP1 aka TMP2
-  R18 = 18,
+  R18 = 18,  // SP in Dart code.
   R19 = 19,
   R20 = 20,
   R21 = 21,
   R22 = 22,
   R23 = 23,
   R24 = 24,
   R25 = 25,
   R26 = 26,
   kLastFreeCpuRegister = 26,
   R27 = 27,  // PP
   R28 = 28,  // CTX
   R29 = 29,  // FP
   R30 = 30,  // LR
-  R31 = 31,  // ZR, SP
+  R31 = 31,  // ZR, CSP
   kNumberOfCpuRegisters = 32,
   kNoRegister = -1,
 
   // These registers both use the encoding R31, but to avoid mistakes we give
   // them different values, and then translate before encoding.
-  SP = 32,
+  CSP = 32,
   ZR = 33,
 
   // Aliases.
   IP0 = R16,
   IP1 = R17,
+  SP = R18,
   FP = R29,
   LR = R30,
 };
 
 enum VRegister {
   V0  =  0,
   V1  =  1,
   V2  =  2,
   V3  =  3,
   V4  =  4,
@@ skipping 37 matching lines @@
 const int kNumberOfFpuRegisters = kNumberOfVRegisters;
 const FpuRegister kNoFpuRegister = kNoVRegister;
 
 // Register aliases.
 const Register TMP = R16;  // Used as scratch register by assembler.
 const Register TMP2 = R17;
 const Register CTX = R28;  // Caches current context in generated code.
 const Register PP = R27;  // Caches object pool pointer in generated code.
 const Register kNoPP = kNoRegister;
 const Register FPREG = FP;  // Frame pointer register.
-const Register SPREG = R31;  // Stack pointer register.
+const Register SPREG = R18;  // Stack pointer register.
 const Register ICREG = R5;  // IC data register.
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = R0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = R1;
 
@@ skipping 22 matching lines @@
 const VRegister kAbiFirstPreservedFpuReg = V8;
 const VRegister kAbiLastPreservedFpuReg = V15;
 const int kAbiPreservedFpuRegCount = 8;
 
 // CPU registers available to Dart allocator.
 const RegList kDartAvailableCpuRegs =
     (1 << R0)  | (1 << R1)  | (1 << R2)  | (1 << R3)  |
     (1 << R4)  | (1 << R5)  | (1 << R6)  | (1 << R7)  |
     (1 << R8)  | (1 << R9)  | (1 << R10) | (1 << R11) |
     (1 << R12) | (1 << R13) | (1 << R14) | (1 << R15) |
-    (1 << R18) | (1 << R19) | (1 << R20) | (1 << R21) |
-    (1 << R22) | (1 << R23) | (1 << R24) | (1 << R25) |
-    (1 << R26);
+    (1 << R19) | (1 << R20) | (1 << R21) | (1 << R22) |
+    (1 << R23) | (1 << R24) | (1 << R25) | (1 << R26);
 
 // Registers available to Dart that are not preserved by runtime calls.
 const RegList kDartVolatileCpuRegs =
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 const Register kDartFirstVolatileCpuReg = R0;
-const Register kDartLastVolatileCpuReg = R18;
-const int kDartVolatileCpuRegCount = 17;  // Excluding R16 and R17.
+const Register kDartLastVolatileCpuReg = R15;
+const int kDartVolatileCpuRegCount = 16;
 const int kDartVolatileFpuRegCount = 24;
 
 static inline Register ConcreteRegister(Register r) {
-  return ((r == ZR) || (r == SP)) ? R31 : r;
+  return ((r == ZR) || (r == CSP)) ? R31 : r;
 }
 
 // Values for the condition field as defined in section A3.2.
 enum Condition {
   kNoCondition = -1,
   EQ =  0,  // equal
   NE =  1,  // not equal
   CS =  2,  // carry set/unsigned higher or same
   CC =  3,  // carry clear/unsigned lower
   MI =  4,  // minus/negative
@@ skipping 718 matching lines @@
 
   // Instruction identification.
   #define IS_OP(op)                                                            \
     inline bool Is##op##Op() const {                                           \
       return ((InstructionBits() & op##Mask) == (op##Fixed & op##Mask)); }
   APPLY_OP_LIST(IS_OP)
   #undef IS_OP
 
   inline bool HasS() const { return (SField() == 1); }
 
-  // Indicate whether Rd can be the SP or ZR. This does not check that the
+  // Indicate whether Rd can be the CSP or ZR. This does not check that the
   // instruction actually has an Rd field.
   R31Type RdMode() const {
-    // The following instructions use SP as Rd:
+    // The following instructions use CSP as Rd:
     //  Add/sub (immediate) when not setting the flags.
     //  Add/sub (extended) when not setting the flags.
     //  Logical (immediate) when not setting the flags.
     // Otherwise, R31 is the ZR.
     if (IsAddSubImmOp() || (IsAddSubShiftExtOp() && IsExtend())) {
       if (HasS()) {
         return R31IsZR;
       } else {
         return R31IsSP;
       }
     }
     // TODO(zra): Handle for logical immediate operations.
     return R31IsZR;
   }
 
-  // Indicate whether Rn can be SP or ZR. This does not check that the
+  // Indicate whether Rn can be CSP or ZR. This does not check that the
   // instruction actually has an Rn field.
   R31Type RnMode() const {
-    // The following instructions use SP as Rn:
+    // The following instructions use CSP as Rn:
     //  All loads and stores.
     //  Add/sub (immediate).
     //  Add/sub (extended).
     // Otherwise, r31 is ZR.
     if (IsLoadStoreOp() ||
         IsAddSubImmOp() ||
         (IsAddSubShiftExtOp() && IsExtend())) {
       return R31IsSP;
     }
     return R31IsZR;
@@ skipping 73 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_