Fixes to run "Hello, world!" on arm64 hardware.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 149 matching lines @@
     Unscaled,
     Scaled,
   };
 
   // Base register rn with offset rm. rm is sign-extended according to ext.
   // If ext is UXTX, rm may be optionally scaled by the
   // Log2OperandSize (specified by the instruction).
   Address(Register rn, Register rm,
           Extend ext = UXTX, Scaling scale = Unscaled) {
     ASSERT((rn != R31) && (rn != ZR));
-    ASSERT((rm != R31) && (rm != SP));
+    ASSERT((rm != R31) && (rm != CSP));
     // Can only scale when ext = UXTX.
     ASSERT((scale != Scaled) || (ext == UXTX));
     ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const int32_t s = (scale == Scaled) ? B12 : 0;
     encoding_ =
         B21 | B11 | s |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
@@ skipping 93 matching lines @@
   Operand(const Operand& other)
       : ValueObject(), encoding_(other.encoding_), type_(other.type_) { }
 
   Operand& operator=(const Operand& other) {
     type_ = other.type_;
     encoding_ = other.encoding_;
     return *this;
   }
 
   explicit Operand(Register rm) {
-    ASSERT((rm != R31) && (rm != SP));
+    ASSERT((rm != R31) && (rm != CSP));
     const Register crm = ConcreteRegister(rm);
     encoding_ = (static_cast<int32_t>(crm) << kRmShift);
     type_ = Shifted;
   }
 
   Operand(Register rm, Shift shift, int32_t imm) {
     ASSERT(Utils::IsUint(6, imm));
-    ASSERT((rm != R31) && (rm != SP));
+    ASSERT((rm != R31) && (rm != CSP));
     const Register crm = ConcreteRegister(rm);
     encoding_ =
         (imm << kImm6Shift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(shift) << kShiftTypeShift);
     type_ = Shifted;
   }
 
   Operand(Register rm, Extend extend, int32_t imm) {
     ASSERT(Utils::IsUint(3, imm));
-    ASSERT((rm != R31) && (rm != SP));
+    ASSERT((rm != R31) && (rm != CSP));
     const Register crm = ConcreteRegister(rm);
     encoding_ =
         B21 |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(extend) << kExtendTypeShift) |
         ((imm & 0x7) << kImm3Shift);
     type_ = Extended;
   }
 
   explicit Operand(int32_t imm) {
@@ skipping 142 matching lines @@
 
   // Emit data (e.g encoded instruction or immediate) in instruction stream.
   void Emit(int32_t value);
 
   // On some other platforms, we draw a distinction between safe and unsafe
   // smis.
   static bool IsSafe(const Object& object) { return true; }
   static bool IsSafeSmi(const Object& object) { return object.IsSmi(); }
 
   // Addition and subtraction.
-  // For add and sub, to use SP for rn, o must be of type Operand::Extend.
+  // For add and sub, to use CSP for rn, o must be of type Operand::Extend.
   // For an unmodified rm in this case, use Operand(rm, UXTX, 0);
   void add(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, false, false, rd, rn, o);
   }
   void adds(Register rd, Register rn, Operand o) {
     AddSubHelper(kDoubleWord, true, false, rd, rn, o);
   }
   void addw(Register rd, Register rn, Operand o) {
     AddSubHelper(kWord, false, false, rd, rn, o);
   }
@@ skipping 88 matching lines @@
   }
   void msub(Register rd, Register rn, Register rm, Register ra) {
     EmitMiscDP3Source(MSUB, rd, rn, rm, ra, kDoubleWord);
   }
   void smulh(Register rd, Register rn, Register rm) {
     EmitMiscDP3Source(SMULH, rd, rn, rm, R0, kDoubleWord);
   }
 
   // Move wide immediate.
   void movk(Register rd, uint16_t imm, int hw_idx) {
-    ASSERT(rd != SP);
+    ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVK, crd, imm, hw_idx, kDoubleWord);
   }
   void movn(Register rd, uint16_t imm, int hw_idx) {
-    ASSERT(rd != SP);
+    ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVN, crd, imm, hw_idx, kDoubleWord);
   }
   void movz(Register rd, uint16_t imm, int hw_idx) {
-    ASSERT(rd != SP);
+    ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitMoveWideOp(MOVZ, crd, imm, hw_idx, kDoubleWord);
   }
 
   // Loads and Stores.
   void ldr(Register rt, Address a, OperandSize sz = kDoubleWord) {
     if (a.type() == Address::PCOffset) {
       ASSERT(sz == kDoubleWord);
       EmitLoadRegLiteral(LDRpc, rt, a, sz);
     } else {
@@ skipping 32 matching lines @@
   }
   void cinv(Register rd, Register rn, Condition cond) {
     csinv(rd, rn, rn, InvertCondition(cond));
   }
   void csetm(Register rd, Condition cond) {
     csinv(rd, ZR, ZR, InvertCondition(cond));
   }
 
   // Comparison.
   // rn cmp o.
-  // For add and sub, to use SP for rn, o must be of type Operand::Extend.
+  // For add and sub, to use CSP for rn, o must be of type Operand::Extend.
   // For an unmodified rm in this case, use Operand(rm, UXTX, 0);
   void cmp(Register rn, Operand o) {
     subs(ZR, rn, o);
   }
   // rn cmp -o.
   void cmn(Register rn, Operand o) {
     adds(ZR, rn, o);
   }
 
   void CompareRegisters(Register rn, Register rm) {
-    if (rn == SP) {
+    if (rn == CSP) {
       // UXTX 0 on a 64-bit register (rm) is a nop, but forces R31 to be
-      // interpreted as SP.
-      cmp(SP, Operand(rm, UXTX, 0));
+      // interpreted as CSP.
+      cmp(CSP, Operand(rm, UXTX, 0));
     } else {
       cmp(rn, Operand(rm));
     }
   }
 
   // Conditional branch.
   void b(Label* label, Condition cond = AL) {
     EmitBranch(BCOND, cond, label);
   }
 
@@ skipping 32 matching lines @@
     const uint8_t imm8 = (bit7 << 7) | (bit6 << 6) | (bit54 << 4) | bit30;
     const int64_t expimm8 = Instr::VFPExpandImm(imm8);
     if (imm64 != expimm8) {
       return false;
     }
     EmitFPImm(FMOVDI, vd, imm8);
     return true;
   }
   void fmovdr(VRegister vd, Register rn) {
     ASSERT(rn != R31);
-    ASSERT(rn != SP);
+    ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(FMOVDR, static_cast<Register>(vd), crn);
   }
   void fmovrd(Register rd, VRegister vn) {
     ASSERT(rd != R31);
-    ASSERT(rd != SP);
+    ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FMOVRD, crd, static_cast<Register>(vn));
   }
   void scvtfd(VRegister vd, Register rn) {
     ASSERT(rn != R31);
-    ASSERT(rn != SP);
+    ASSERT(rn != CSP);
     const Register crn = ConcreteRegister(rn);
     EmitFPIntCvtOp(SCVTFD, static_cast<Register>(vd), crn);
   }
   void fcvtzds(Register rd, VRegister vn) {
     ASSERT(rd != R31);
-    ASSERT(rd != SP);
+    ASSERT(rd != CSP);
     const Register crd = ConcreteRegister(rd);
     EmitFPIntCvtOp(FCVTZDS, crd, static_cast<Register>(vn));
   }
   void fmovdd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FMOVDD, vd, vn);
   }
   void fabsd(VRegister vd, VRegister vn) {
     EmitFPOneSourceOp(FABSD, vd, vn);
   }
   void fnegd(VRegister vd, VRegister vn) {
@@ skipping 192 matching lines @@
     const VRegister vd = static_cast<VRegister>(rd);
     EmitSIMDCopyOp(VMOVW, vd, vn, kWord, 0, sidx);
   }
   void vmovrd(Register rd, VRegister vn, int32_t sidx) {
     const VRegister vd = static_cast<VRegister>(rd);
     EmitSIMDCopyOp(VMOVX, vd, vn, kDoubleWord, 0, sidx);
   }
 
   // Aliases.
   void mov(Register rd, Register rn) {
-    if ((rd == SP) || (rn == SP)) {
+    if ((rd == CSP) || (rn == CSP)) {
       add(rd, rn, Operand(0));
     } else {
       orr(rd, ZR, Operand(rn));
     }
   }
   void vmov(VRegister vd, VRegister vn) {
     vorr(vd, vn, vn);
   }
   void mvn(Register rd, Register rm) {
     orn(rd, ZR, Operand(rm));
@@ skipping 332 matching lines @@
 
   void AddSubHelper(OperandSize os, bool set_flags, bool subtract,
                     Register rd, Register rn, Operand o) {
     ASSERT((rd != R31) && (rn != R31));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     if (o.type() == Operand::Immediate) {
       ASSERT(rn != ZR);
       EmitAddSubImmOp(subtract ? SUBI : ADDI, crd, crn, o, os, set_flags);
     } else if (o.type() == Operand::Shifted) {
-      ASSERT((rd != SP) && (rn != SP));
+      ASSERT((rd != CSP) && (rn != CSP));
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     } else {
       ASSERT(o.type() == Operand::Extended);
-      ASSERT((rd != SP) && (rn != ZR));
+      ASSERT((rd != CSP) && (rn != ZR));
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     }
   }
 
   void EmitAddSubImmOp(AddSubImmOp op, Register rd, Register rn,
                        Operand o, OperandSize sz, bool set_flags) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t s = set_flags ? B29 : 0;
     const int32_t encoding =
         op | size | s |
         (static_cast<int32_t>(rd) << kRdShift) |
         (static_cast<int32_t>(rn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
   void EmitLogicalImmOp(LogicalImmOp op, Register rd, Register rn,
                         Operand o, OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT((rd != R31) && (rn != R31));
-    ASSERT(rn != SP);
+    ASSERT(rn != CSP);
     ASSERT((op == ANDIS) || (rd != ZR));  // op != ANDIS => rd != ZR.
-    ASSERT((op != ANDIS) || (rd != SP));  // op == ANDIS => rd != SP.
+    ASSERT((op != ANDIS) || (rd != CSP));  // op == ANDIS => rd != CSP.
     ASSERT(o.type() == Operand::BitfieldImm);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         o.encoding();
     Emit(encoding);
   }
 
   void EmitLogicalShiftOp(LogicalShiftOp op,
                           Register rd, Register rn, Operand o, OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT((rd != R31) && (rn != R31));
-    ASSERT((rd != SP) && (rn != SP));
+    ASSERT((rd != CSP) && (rn != CSP));
     ASSERT(o.type() == Operand::Shifted);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         o.encoding();
     Emit(encoding);
@@ skipping 46 matching lines @@
 
   int64_t DecodeImm26BranchOffset(int32_t instr) {
     const int32_t off = (((instr & kImm26Mask) >> kImm26Shift) << 6) >> 4;
     return static_cast<int64_t>(off);
   }
 
   void EmitCompareAndBranch(CompareAndBranchOp op, Register rt, int64_t imm,
                             OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     ASSERT(Utils::IsInt(21, imm) && ((imm & 0x3) == 0));
-    ASSERT((rt != SP) && (rt != R31));
+    ASSERT((rt != CSP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoded_offset = EncodeImm19BranchOffset(imm, 0);
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crt) << kRtShift) |
         encoded_offset;
     Emit(encoding);
   }
 
@@ skipping 44 matching lines @@
   }
 
   void EmitUnconditionalBranchOp(UnconditionalBranchOp op, int64_t offset) {
     ASSERT(CanEncodeImm26BranchOffset(offset));
     const int32_t off = (offset >> 2) << kImm26Shift;
     const int32_t encoding = op | off;
     Emit(encoding);
   }
 
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
-    ASSERT((rn != SP) && (rn != R31));
+    ASSERT((rn != CSP) && (rn != R31));
     const Register crn = ConcreteRegister(rn);
     const int32_t encoding =
         op | (static_cast<int32_t>(crn) << kRnShift);
     Emit(encoding);
   }
 
   void EmitExceptionGenOp(ExceptionGenOp op, uint16_t imm) {
     const int32_t encoding =
         op | (static_cast<int32_t>(imm) << kImm16Shift);
     Emit(encoding);
@@ skipping 19 matching lines @@
     const int32_t encoding =
         op | ((size & 0x3) << kSzShift) |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitLoadRegLiteral(LoadRegLiteralOp op, Register rt, Address a,
                           OperandSize sz) {
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
-    ASSERT((rt != SP) && (rt != R31));
+    ASSERT((rt != CSP) && (rt != R31));
     const Register crt = ConcreteRegister(rt);
     const int32_t size = (sz == kDoubleWord) ? B30 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crt) << kRtShift) |
         a.encoding();
     Emit(encoding);
   }
 
   void EmitPCRelOp(PCRelOp op, Register rd, int64_t imm) {
     ASSERT(Utils::IsInt(21, imm));
-    ASSERT((rd != R31) && (rd != SP));
+    ASSERT((rd != R31) && (rd != CSP));
     const Register crd = ConcreteRegister(rd);
     const int32_t loimm = (imm & 0x3) << 29;
     const int32_t hiimm = ((imm >> 2) << kImm19Shift) & kImm19Mask;
     const int32_t encoding =
         op | loimm | hiimm |
         (static_cast<int32_t>(crd) << kRdShift);
     Emit(encoding);
   }
 
   void EmitMiscDP2Source(MiscDP2SourceOp op,
                          Register rd, Register rn, Register rm,
                          OperandSize sz) {
-    ASSERT((rd != SP) && (rn != SP) && (rm != SP));
+    ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift);
     Emit(encoding);
   }
 
   void EmitMiscDP3Source(MiscDP3SourceOp op,
                          Register rd, Register rn, Register rm, Register ra,
                          OperandSize sz) {
-    ASSERT((rd != SP) && (rn != SP) && (rm != SP) && (ra != SP));
+    ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP) && (ra != CSP));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const Register cra = ConcreteRegister(ra);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(cra) << kRaShift);
     Emit(encoding);
   }
 
   void EmitConditionalSelect(ConditionalSelectOp op,
                              Register rd, Register rn, Register rm,
                              Condition cond, OperandSize sz) {
-    ASSERT((rd != SP) && (rn != SP) && (rm != SP));
+    ASSERT((rd != CSP) && (rn != CSP) && (rm != CSP));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
@@ skipping 82 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_