Adds more ARM64 SIMD instructions.

runtime/vm/disassembler_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM64.
 #if defined(TARGET_ARCH_ARM64)
 #include "platform/assert.h"
 
@@ skipping 1070 matching lines @@
   } else if ((U == 0) && (opcode == 0x1a)) {
     if (instr->Bit(23) == 0) {
       Format(instr, "vadd'vsz 'vd, 'vn, 'vm");
     } else {
       Format(instr, "vsub'vsz 'vd, 'vn, 'vm");
     }
   } else if ((U == 1) && (opcode == 0x1b)) {
     Format(instr, "vmul'vsz 'vd, 'vn, 'vm");
   } else if ((U == 1) && (opcode == 0x1f)) {
     Format(instr, "vdiv'vsz 'vd, 'vn, 'vm");
+  } else if ((U == 0) && (opcode == 0x1c)) {
+    Format(instr, "vceq'vsz 'vd, 'vn, 'vm");
+  } else if ((U == 1) && (opcode == 0x1c)) {
+    if (instr->Bit(23) == 1) {
+      Format(instr, "vcgt'vsz 'vd, 'vn, 'vm");
+    } else {
+      Format(instr, "vcge'vsz 'vd, 'vn, 'vm");
+    }
+  } else if ((U == 0) && (opcode == 0x1e)) {
+    if (instr->Bit(23) == 1) {
+      Format(instr, "vmin'vsz 'vd, 'vn, 'vm");
+    } else {
+      Format(instr, "vmax'vsz 'vd, 'vn, 'vm");
+    }
+  } else if ((U == 0) && (opcode == 0x1f)) {
+    if (instr->Bit(23) == 1) {
+      Format(instr, "vrsqrt'vsz 'vd, 'vn, 'vm");
+    } else {
+      Format(instr, "vrecps'vsz 'vd, 'vn, 'vm");
+    }
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeSIMDTwoReg(Instr* instr) {
   const int32_t Q = instr->Bit(30);
   const int32_t U = instr->Bit(29);
   const int32_t op = instr->Bits(12, 5);
@@ skipping 15 matching lines @@
       Unknown(instr);
     }
   } else if ((U == 1) && (op == 0xf)) {
     if (sz == 2) {
       Format(instr, "vnegs 'vd, 'vn");
     } else if (sz == 3) {
       Format(instr, "vnegd 'vd, 'vn");
     } else {
       Unknown(instr);
     }
+  } else if ((U == 1) && (op == 0x1f)) {
+    if (sz == 2) {
+      Format(instr, "vsqrts 'vd, 'vn");
+    } else if (sz == 3) {
+      Format(instr, "vsqrtd 'vd, 'vn");
+    } else {
+      Unknown(instr);
+    }
+  } else if ((U == 0) && (op == 0x1d)) {
+    if (sz != 2) {
+      Unknown(instr);
+      return;
+    }
+    Format(instr, "vrecpes 'vd, 'vn");
+  } else if ((U == 1) && (op == 0x1d)) {
+    if (sz != 2) {
+      Unknown(instr);
+      return;
+    }
+    Format(instr, "vrsqrtes 'vd, 'vn");
   } else {
     Unknown(instr);
   }
 }
 
 
 void ARM64Decoder::DecodeDPSimd1(Instr* instr) {
   if (instr->IsSIMDCopyOp()) {
     DecodeSIMDCopy(instr);
   } else if (instr->IsSIMDThreeSameOp()) {
@@ skipping 208 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM