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Side by Side Diff: runtime/vm/constants_arm64.h

Issue 307523002: Adds more ARM64 SIMD instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 7 months ago
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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_CONSTANTS_ARM64_H_ 5 #ifndef VM_CONSTANTS_ARM64_H_
6 #define VM_CONSTANTS_ARM64_H_ 6 #define VM_CONSTANTS_ARM64_H_
7 7
8 #include "platform/assert.h" 8 #include "platform/assert.h"
9 9
10 namespace dart { 10 namespace dart {
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477 VSUBW = SIMDThreeSameFixed | B30 | B29 | B23 | B15, 477 VSUBW = SIMDThreeSameFixed | B30 | B29 | B23 | B15,
478 VSUBX = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15, 478 VSUBX = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15,
479 VADDS = SIMDThreeSameFixed | B30 | B15 | B14 | B12, 479 VADDS = SIMDThreeSameFixed | B30 | B15 | B14 | B12,
480 VADDD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B12, 480 VADDD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B12,
481 VSUBS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B12, 481 VSUBS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B12,
482 VSUBD = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B12, 482 VSUBD = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B12,
483 VMULS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B12 | B11, 483 VMULS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B12 | B11,
484 VMULD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B12 | B11, 484 VMULD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B12 | B11,
485 VDIVS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 | B12 | B11, 485 VDIVS = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13 | B12 | B11,
486 VDIVD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 | B12 | B11, 486 VDIVD = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13 | B12 | B11,
487 VCEQS = SIMDThreeSameFixed | B30 | B15 | B14 | B13,
488 VCEQD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13,
489 VCGES = SIMDThreeSameFixed | B30 | B29 | B15 | B14 | B13,
490 VCGED = SIMDThreeSameFixed | B30 | B29 | B22 | B15 | B14 | B13,
491 VCGTS = SIMDThreeSameFixed | B30 | B29 | B23 | B15 | B14 | B13,
492 VCGTD = SIMDThreeSameFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13,
493 VMAXS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12,
494 VMAXD = SIMDThreeSameFixed | B30 | B22 | B15 | B14 | B13 | B12,
495 VMINS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12,
496 VMIND = SIMDThreeSameFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12,
497 VRECPSS = SIMDThreeSameFixed | B30 | B15 | B14 | B13 | B12 | B11,
498 VRSQRTSS = SIMDThreeSameFixed | B30 | B23 | B15 | B14 | B13 | B12 | B11,
487 }; 499 };
488 500
489 // C.3.6.17 501 // C.3.6.17
490 enum SIMDTwoRegOp { 502 enum SIMDTwoRegOp {
491 SIMDTwoRegMask = 0x9f3e0c00, 503 SIMDTwoRegMask = 0x9f3e0c00,
492 SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11, 504 SIMDTwoRegFixed = DPSimd1Fixed | B21 | B11,
493 VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12, 505 VNOT = SIMDTwoRegFixed | B30 | B29 | B14 | B12,
494 VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12, 506 VABSS = SIMDTwoRegFixed | B30 | B23 | B15 | B14 | B13 | B12,
495 VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12, 507 VNEGS = SIMDTwoRegFixed | B30 | B29 | B23 | B15 | B14 | B13 | B12,
496 VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12, 508 VABSD = SIMDTwoRegFixed | B30 | B23 | B22 | B15 | B14 | B13 | B12,
497 VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12, 509 VNEGD = SIMDTwoRegFixed | B30 | B29 | B23 | B22 | B15 | B14 | B13 | B12,
510 VSQRTS = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B13 | B12,
511 VSQRTD = SIMDTwoRegFixed | B30 | B29 | B23 | B22
512 | B16 | B15 | B14 | B13 | B12,
513 VRECPES = SIMDTwoRegFixed | B30 | B23 | B16 | B15 | B14 | B12,
514 VRSQRTES = SIMDTwoRegFixed | B30 | B29 | B23 | B16 | B15 | B14 | B12,
498 }; 515 };
499 516
500 // C.3.6.22 517 // C.3.6.22
501 enum FPCompareOp { 518 enum FPCompareOp {
502 FPCompareMask = 0xffa0fc07, 519 FPCompareMask = 0xffa0fc07,
503 FPCompareFixed = FPFixed | B21 | B13, 520 FPCompareFixed = FPFixed | B21 | B13,
504 FCMPD = FPCompareFixed | B22, 521 FCMPD = FPCompareFixed | B22,
505 FCMPZD = FPCompareFixed | B22 | B3, 522 FCMPZD = FPCompareFixed | B22 | B3,
506 }; 523 };
507 524
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998 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } 1015 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
999 1016
1000 private: 1017 private:
1001 DISALLOW_ALLOCATION(); 1018 DISALLOW_ALLOCATION();
1002 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); 1019 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
1003 }; 1020 };
1004 1021
1005 } // namespace dart 1022 } // namespace dart
1006 1023
1007 #endif // VM_CONSTANTS_ARM64_H_ 1024 #endif // VM_CONSTANTS_ARM64_H_
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