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| 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #ifndef VM_ASSEMBLER_ARM64_H_ | 5 #ifndef VM_ASSEMBLER_ARM64_H_ |
| 6 #define VM_ASSEMBLER_ARM64_H_ | 6 #define VM_ASSEMBLER_ARM64_H_ |
| 7 | 7 |
| 8 #ifndef VM_ASSEMBLER_H_ | 8 #ifndef VM_ASSEMBLER_H_ |
| 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. | 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. |
| 10 #endif | 10 #endif |
| (...skipping 759 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 770 } | 770 } |
| 771 void vmuld(VRegister vd, VRegister vn, VRegister vm) { | 771 void vmuld(VRegister vd, VRegister vn, VRegister vm) { |
| 772 EmitSIMDThreeSameOp(VMULD, vd, vn, vm); | 772 EmitSIMDThreeSameOp(VMULD, vd, vn, vm); |
| 773 } | 773 } |
| 774 void vdivs(VRegister vd, VRegister vn, VRegister vm) { | 774 void vdivs(VRegister vd, VRegister vn, VRegister vm) { |
| 775 EmitSIMDThreeSameOp(VDIVS, vd, vn, vm); | 775 EmitSIMDThreeSameOp(VDIVS, vd, vn, vm); |
| 776 } | 776 } |
| 777 void vdivd(VRegister vd, VRegister vn, VRegister vm) { | 777 void vdivd(VRegister vd, VRegister vn, VRegister vm) { |
| 778 EmitSIMDThreeSameOp(VDIVD, vd, vn, vm); | 778 EmitSIMDThreeSameOp(VDIVD, vd, vn, vm); |
| 779 } | 779 } |
| 780 void vceqs(VRegister vd, VRegister vn, VRegister vm) { |
| 781 EmitSIMDThreeSameOp(VCEQS, vd, vn, vm); |
| 782 } |
| 783 void vceqd(VRegister vd, VRegister vn, VRegister vm) { |
| 784 EmitSIMDThreeSameOp(VCEQD, vd, vn, vm); |
| 785 } |
| 786 void vcgts(VRegister vd, VRegister vn, VRegister vm) { |
| 787 EmitSIMDThreeSameOp(VCGTS, vd, vn, vm); |
| 788 } |
| 789 void vcgtd(VRegister vd, VRegister vn, VRegister vm) { |
| 790 EmitSIMDThreeSameOp(VCGTD, vd, vn, vm); |
| 791 } |
| 792 void vcges(VRegister vd, VRegister vn, VRegister vm) { |
| 793 EmitSIMDThreeSameOp(VCGES, vd, vn, vm); |
| 794 } |
| 795 void vcged(VRegister vd, VRegister vn, VRegister vm) { |
| 796 EmitSIMDThreeSameOp(VCGED, vd, vn, vm); |
| 797 } |
| 798 void vmins(VRegister vd, VRegister vn, VRegister vm) { |
| 799 EmitSIMDThreeSameOp(VMINS, vd, vn, vm); |
| 800 } |
| 801 void vmind(VRegister vd, VRegister vn, VRegister vm) { |
| 802 EmitSIMDThreeSameOp(VMIND, vd, vn, vm); |
| 803 } |
| 804 void vmaxs(VRegister vd, VRegister vn, VRegister vm) { |
| 805 EmitSIMDThreeSameOp(VMAXS, vd, vn, vm); |
| 806 } |
| 807 void vmaxd(VRegister vd, VRegister vn, VRegister vm) { |
| 808 EmitSIMDThreeSameOp(VMAXD, vd, vn, vm); |
| 809 } |
| 810 void vrecpss(VRegister vd, VRegister vn, VRegister vm) { |
| 811 EmitSIMDThreeSameOp(VRECPSS, vd, vn, vm); |
| 812 } |
| 813 void vrsqrtss(VRegister vd, VRegister vn, VRegister vm) { |
| 814 EmitSIMDThreeSameOp(VRSQRTSS, vd, vn, vm); |
| 815 } |
| 780 void vnot(VRegister vd, VRegister vn) { | 816 void vnot(VRegister vd, VRegister vn) { |
| 781 EmitSIMDTwoRegOp(VNOT, vd, vn); | 817 EmitSIMDTwoRegOp(VNOT, vd, vn); |
| 782 } | 818 } |
| 783 void vabss(VRegister vd, VRegister vn) { | 819 void vabss(VRegister vd, VRegister vn) { |
| 784 EmitSIMDTwoRegOp(VABSS, vd, vn); | 820 EmitSIMDTwoRegOp(VABSS, vd, vn); |
| 785 } | 821 } |
| 786 void vabsd(VRegister vd, VRegister vn) { | 822 void vabsd(VRegister vd, VRegister vn) { |
| 787 EmitSIMDTwoRegOp(VABSD, vd, vn); | 823 EmitSIMDTwoRegOp(VABSD, vd, vn); |
| 788 } | 824 } |
| 789 void vnegs(VRegister vd, VRegister vn) { | 825 void vnegs(VRegister vd, VRegister vn) { |
| 790 EmitSIMDTwoRegOp(VNEGS, vd, vn); | 826 EmitSIMDTwoRegOp(VNEGS, vd, vn); |
| 791 } | 827 } |
| 792 void vnegd(VRegister vd, VRegister vn) { | 828 void vnegd(VRegister vd, VRegister vn) { |
| 793 EmitSIMDTwoRegOp(VNEGD, vd, vn); | 829 EmitSIMDTwoRegOp(VNEGD, vd, vn); |
| 794 } | 830 } |
| 831 void vsqrts(VRegister vd, VRegister vn) { |
| 832 EmitSIMDTwoRegOp(VSQRTS, vd, vn); |
| 833 } |
| 834 void vsqrtd(VRegister vd, VRegister vn) { |
| 835 EmitSIMDTwoRegOp(VSQRTD, vd, vn); |
| 836 } |
| 837 void vrecpes(VRegister vd, VRegister vn) { |
| 838 EmitSIMDTwoRegOp(VRECPES, vd, vn); |
| 839 } |
| 840 void vrsqrtes(VRegister vd, VRegister vn) { |
| 841 EmitSIMDTwoRegOp(VRSQRTES, vd, vn); |
| 842 } |
| 795 void vdupw(VRegister vd, Register rn) { | 843 void vdupw(VRegister vd, Register rn) { |
| 796 const VRegister vn = static_cast<VRegister>(rn); | 844 const VRegister vn = static_cast<VRegister>(rn); |
| 797 EmitSIMDCopyOp(VDUPI, vd, vn, kWord, 0, 0); | 845 EmitSIMDCopyOp(VDUPI, vd, vn, kWord, 0, 0); |
| 798 } | 846 } |
| 799 void vdupx(VRegister vd, Register rn) { | 847 void vdupx(VRegister vd, Register rn) { |
| 800 const VRegister vn = static_cast<VRegister>(rn); | 848 const VRegister vn = static_cast<VRegister>(rn); |
| 801 EmitSIMDCopyOp(VDUPI, vd, vn, kDoubleWord, 0, 0); | 849 EmitSIMDCopyOp(VDUPI, vd, vn, kDoubleWord, 0, 0); |
| 802 } | 850 } |
| 803 void vdups(VRegister vd, VRegister vn, int32_t idx) { | 851 void vdups(VRegister vd, VRegister vn, int32_t idx) { |
| 804 EmitSIMDCopyOp(VDUP, vd, vn, kSWord, 0, idx); | 852 EmitSIMDCopyOp(VDUP, vd, vn, kSWord, 0, idx); |
| (...skipping 99 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 904 add(rd, ZR, Operand(rn, LSR, shift)); | 952 add(rd, ZR, Operand(rn, LSR, shift)); |
| 905 } | 953 } |
| 906 void Lsrw(Register rd, Register rn, int shift) { | 954 void Lsrw(Register rd, Register rn, int shift) { |
| 907 ASSERT((shift >= 0) && (shift < 32)); | 955 ASSERT((shift >= 0) && (shift < 32)); |
| 908 addw(rd, ZR, Operand(rn, LSR, shift)); | 956 addw(rd, ZR, Operand(rn, LSR, shift)); |
| 909 } | 957 } |
| 910 void Asr(Register rd, Register rn, int shift) { | 958 void Asr(Register rd, Register rn, int shift) { |
| 911 add(rd, ZR, Operand(rn, ASR, shift)); | 959 add(rd, ZR, Operand(rn, ASR, shift)); |
| 912 } | 960 } |
| 913 | 961 |
| 962 void VRecps(VRegister vd, VRegister vn); |
| 963 void VRSqrts(VRegister vd, VRegister vn); |
| 964 |
| 914 void SmiUntag(Register reg) { | 965 void SmiUntag(Register reg) { |
| 915 Asr(reg, reg, kSmiTagSize); | 966 Asr(reg, reg, kSmiTagSize); |
| 916 } | 967 } |
| 917 void SmiTag(Register reg) { | 968 void SmiTag(Register reg) { |
| 918 Lsl(reg, reg, kSmiTagSize); | 969 Lsl(reg, reg, kSmiTagSize); |
| 919 } | 970 } |
| 920 | 971 |
| 921 // Branching to ExternalLabels. | 972 // Branching to ExternalLabels. |
| 922 void Branch(const ExternalLabel* label, Register pp) { | 973 void Branch(const ExternalLabel* label, Register pp) { |
| 923 LoadExternalLabel(TMP, label, kNotPatchable, pp); | 974 LoadExternalLabel(TMP, label, kNotPatchable, pp); |
| (...skipping 628 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 1552 Register value, | 1603 Register value, |
| 1553 Label* no_update); | 1604 Label* no_update); |
| 1554 | 1605 |
| 1555 DISALLOW_ALLOCATION(); | 1606 DISALLOW_ALLOCATION(); |
| 1556 DISALLOW_COPY_AND_ASSIGN(Assembler); | 1607 DISALLOW_COPY_AND_ASSIGN(Assembler); |
| 1557 }; | 1608 }; |
| 1558 | 1609 |
| 1559 } // namespace dart | 1610 } // namespace dart |
| 1560 | 1611 |
| 1561 #endif // VM_ASSEMBLER_ARM64_H_ | 1612 #endif // VM_ASSEMBLER_ARM64_H_ |
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