| OLD | NEW |
| 1 ; Simple test of signed and unsigned integer conversions. | 1 ; Simple test of signed and unsigned integer conversions. |
| 2 | 2 |
| 3 ; RUIN: %llvm2ice -O2 --verbose none %s | FileCheck %s | 3 ; RUN: %llvm2ice -O2 --verbose none %s | FileCheck %s |
| 4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck --check-prefix=OPTM1 %s | 4 ; RUN: %llvm2ice -Om1 --verbose none %s | FileCheck %s |
| 5 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s | 5 ; RUN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s |
| 6 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s | 6 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s |
| 7 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ | 7 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \ |
| 8 ; RUN: | FileCheck --check-prefix=DUMP %s | 8 ; RUN: | FileCheck --check-prefix=DUMP %s |
| 9 | 9 |
| 10 @i8v = global [1 x i8] zeroinitializer, align 1 | 10 @i8v = global [1 x i8] zeroinitializer, align 1 |
| 11 @i16v = global [2 x i8] zeroinitializer, align 2 | 11 @i16v = global [2 x i8] zeroinitializer, align 2 |
| 12 @i32v = global [4 x i8] zeroinitializer, align 4 | 12 @i32v = global [4 x i8] zeroinitializer, align 4 |
| 13 @i64v = global [8 x i8] zeroinitializer, align 8 | 13 @i64v = global [8 x i8] zeroinitializer, align 8 |
| 14 @u8v = global [1 x i8] zeroinitializer, align 1 | 14 @u8v = global [1 x i8] zeroinitializer, align 1 |
| (...skipping 10 matching lines...) Expand all Loading... |
| 25 store i16 %v1, i16* %__3, align 1 | 25 store i16 %v1, i16* %__3, align 1 |
| 26 %v2 = sext i8 %v0 to i32 | 26 %v2 = sext i8 %v0 to i32 |
| 27 %__5 = bitcast [4 x i8]* @i32v to i32* | 27 %__5 = bitcast [4 x i8]* @i32v to i32* |
| 28 store i32 %v2, i32* %__5, align 1 | 28 store i32 %v2, i32* %__5, align 1 |
| 29 %v3 = sext i8 %v0 to i64 | 29 %v3 = sext i8 %v0 to i64 |
| 30 %__7 = bitcast [8 x i8]* @i64v to i64* | 30 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 31 store i64 %v3, i64* %__7, align 1 | 31 store i64 %v3, i64* %__7, align 1 |
| 32 ret void | 32 ret void |
| 33 } | 33 } |
| 34 ; CHECK: from_int8: | 34 ; CHECK: from_int8: |
| 35 ; CHECK: mov al, byte ptr [ | 35 ; CHECK: mov {{.*}}, byte ptr [ |
| 36 ; CHECK-NEXT: movsx cx, al | 36 ; CHECK: movsx |
| 37 ; CHECK-NEXT: mov word ptr [ | 37 ; CHECK: mov word ptr [ |
| 38 ; CHECK-NEXT: movsx ecx, al | 38 ; CHECK: movsx |
| 39 ; CHECK-NEXT: mov dword ptr [ | 39 ; CHECK: mov dword ptr [ |
| 40 ; CHECK-NEXT: movsx ecx, al | 40 ; CHECK: movsx |
| 41 ; CHECK-NEXT: sar eax, 31 | 41 ; CHECK: sar {{.*}}, 31 |
| 42 ; CHECK-NEXT: mov dword ptr [i64v+4], | 42 ; CHECK: i64v |
| 43 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 44 ; | |
| 45 ; OPTM1: from_int8: | |
| 46 ; OPTM1: mov {{.*}}, byte ptr [ | |
| 47 ; OPTM1: movsx | |
| 48 ; OPTM1: mov word ptr [ | |
| 49 ; OPTM1: movsx | |
| 50 ; OPTM1: mov dword ptr [ | |
| 51 ; OPTM1: movsx | |
| 52 ; OPTM1: sar {{.*}}, 31 | |
| 53 ; OPTM1: i64v | |
| 54 | 43 |
| 55 define void @from_int16() { | 44 define void @from_int16() { |
| 56 entry: | 45 entry: |
| 57 %__0 = bitcast [2 x i8]* @i16v to i16* | 46 %__0 = bitcast [2 x i8]* @i16v to i16* |
| 58 %v0 = load i16* %__0, align 1 | 47 %v0 = load i16* %__0, align 1 |
| 59 %v1 = trunc i16 %v0 to i8 | 48 %v1 = trunc i16 %v0 to i8 |
| 60 %__3 = bitcast [1 x i8]* @i8v to i8* | 49 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 61 store i8 %v1, i8* %__3, align 1 | 50 store i8 %v1, i8* %__3, align 1 |
| 62 %v2 = sext i16 %v0 to i32 | 51 %v2 = sext i16 %v0 to i32 |
| 63 %__5 = bitcast [4 x i8]* @i32v to i32* | 52 %__5 = bitcast [4 x i8]* @i32v to i32* |
| 64 store i32 %v2, i32* %__5, align 1 | 53 store i32 %v2, i32* %__5, align 1 |
| 65 %v3 = sext i16 %v0 to i64 | 54 %v3 = sext i16 %v0 to i64 |
| 66 %__7 = bitcast [8 x i8]* @i64v to i64* | 55 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 67 store i64 %v3, i64* %__7, align 1 | 56 store i64 %v3, i64* %__7, align 1 |
| 68 ret void | 57 ret void |
| 69 } | 58 } |
| 70 ; CHECK: from_int16: | 59 ; CHECK: from_int16: |
| 71 ; CHECK: mov ax, word ptr [ | 60 ; CHECK: mov {{.*}}, word ptr [ |
| 72 ; CHECK-NEXT: mov cx, ax | 61 ; CHECK: i8v |
| 73 ; CHECK-NEXT: mov byte ptr [ | 62 ; CHECK: movsx |
| 74 ; CHECK-NEXT: movsx ecx, ax | 63 ; CHECK: i32v |
| 75 ; CHECK-NEXT: mov dword ptr [ | 64 ; CHECK: movsx |
| 76 ; CHECK-NEXT: movsx ecx, ax | 65 ; CHECK: sar {{.*}}, 31 |
| 77 ; CHECK-NEXT: sar eax, 31 | 66 ; CHECK: i64v |
| 78 ; CHECK-NEXT: mov dword ptr [i64v+4], | |
| 79 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 80 ; | |
| 81 ; OPTM1: from_int16: | |
| 82 ; OPTM1: mov {{.*}}, word ptr [ | |
| 83 ; OPTM1: i8v | |
| 84 ; OPTM1: movsx | |
| 85 ; OPTM1: i32v | |
| 86 ; OPTM1: movsx | |
| 87 ; OPTM1: sar {{.*}}, 31 | |
| 88 ; OPTM1: i64v | |
| 89 | 67 |
| 90 define void @from_int32() { | 68 define void @from_int32() { |
| 91 entry: | 69 entry: |
| 92 %__0 = bitcast [4 x i8]* @i32v to i32* | 70 %__0 = bitcast [4 x i8]* @i32v to i32* |
| 93 %v0 = load i32* %__0, align 1 | 71 %v0 = load i32* %__0, align 1 |
| 94 %v1 = trunc i32 %v0 to i8 | 72 %v1 = trunc i32 %v0 to i8 |
| 95 %__3 = bitcast [1 x i8]* @i8v to i8* | 73 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 96 store i8 %v1, i8* %__3, align 1 | 74 store i8 %v1, i8* %__3, align 1 |
| 97 %v2 = trunc i32 %v0 to i16 | 75 %v2 = trunc i32 %v0 to i16 |
| 98 %__5 = bitcast [2 x i8]* @i16v to i16* | 76 %__5 = bitcast [2 x i8]* @i16v to i16* |
| 99 store i16 %v2, i16* %__5, align 1 | 77 store i16 %v2, i16* %__5, align 1 |
| 100 %v3 = sext i32 %v0 to i64 | 78 %v3 = sext i32 %v0 to i64 |
| 101 %__7 = bitcast [8 x i8]* @i64v to i64* | 79 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 102 store i64 %v3, i64* %__7, align 1 | 80 store i64 %v3, i64* %__7, align 1 |
| 103 ret void | 81 ret void |
| 104 } | 82 } |
| 105 ; CHECK: from_int32: | 83 ; CHECK: from_int32: |
| 106 ; CHECK: mov eax, dword ptr [ | 84 ; CHECK: i32v |
| 107 ; CHECK-NEXT: mov ecx, eax | 85 ; CHECK: i8v |
| 108 ; CHECK-NEXT: mov byte ptr [ | 86 ; CHECK: i16v |
| 109 ; CHECK-NEXT: mov ecx, eax | 87 ; CHECK: sar {{.*}}, 31 |
| 110 ; CHECK-NEXT: mov word ptr [ | 88 ; CHECK: i64v |
| 111 ; CHECK-NEXT: mov ecx, eax | |
| 112 ; CHECK-NEXT: sar eax, 31 | |
| 113 ; CHECK-NEXT: mov dword ptr [i64v+4], | |
| 114 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 115 ; | |
| 116 ; OPTM1: from_int32: | |
| 117 ; OPTM1: i32v | |
| 118 ; OPTM1: i8v | |
| 119 ; OPTM1: i16v | |
| 120 ; OPTM1: sar {{.*}}, 31 | |
| 121 ; OPTM1: i64v | |
| 122 | 89 |
| 123 define void @from_int64() { | 90 define void @from_int64() { |
| 124 entry: | 91 entry: |
| 125 %__0 = bitcast [8 x i8]* @i64v to i64* | 92 %__0 = bitcast [8 x i8]* @i64v to i64* |
| 126 %v0 = load i64* %__0, align 1 | 93 %v0 = load i64* %__0, align 1 |
| 127 %v1 = trunc i64 %v0 to i8 | 94 %v1 = trunc i64 %v0 to i8 |
| 128 %__3 = bitcast [1 x i8]* @i8v to i8* | 95 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 129 store i8 %v1, i8* %__3, align 1 | 96 store i8 %v1, i8* %__3, align 1 |
| 130 %v2 = trunc i64 %v0 to i16 | 97 %v2 = trunc i64 %v0 to i16 |
| 131 %__5 = bitcast [2 x i8]* @i16v to i16* | 98 %__5 = bitcast [2 x i8]* @i16v to i16* |
| 132 store i16 %v2, i16* %__5, align 1 | 99 store i16 %v2, i16* %__5, align 1 |
| 133 %v3 = trunc i64 %v0 to i32 | 100 %v3 = trunc i64 %v0 to i32 |
| 134 %__7 = bitcast [4 x i8]* @i32v to i32* | 101 %__7 = bitcast [4 x i8]* @i32v to i32* |
| 135 store i32 %v3, i32* %__7, align 1 | 102 store i32 %v3, i32* %__7, align 1 |
| 136 ret void | 103 ret void |
| 137 } | 104 } |
| 138 ; CHECK: from_int64: | 105 ; CHECK: from_int64: |
| 139 ; CHECK: mov eax, dword ptr [ | 106 ; CHECK: i64v |
| 140 ; CHECK-NEXT: mov ecx, eax | 107 ; CHECK: i8v |
| 141 ; CHECK-NEXT: mov byte ptr [ | 108 ; CHECK: i16v |
| 142 ; CHECK-NEXT: mov ecx, eax | 109 ; CHECK: i32v |
| 143 ; CHECK-NEXT: mov word ptr [ | |
| 144 ; CHECK-NEXT: mov dword ptr [ | |
| 145 ; | |
| 146 ; OPTM1: from_int64: | |
| 147 ; OPTM1: i64v | |
| 148 ; OPTM1: i8v | |
| 149 ; OPTM1: i16v | |
| 150 ; OPTM1: i32v | |
| 151 | 110 |
| 152 define void @from_uint8() { | 111 define void @from_uint8() { |
| 153 entry: | 112 entry: |
| 154 %__0 = bitcast [1 x i8]* @u8v to i8* | 113 %__0 = bitcast [1 x i8]* @u8v to i8* |
| 155 %v0 = load i8* %__0, align 1 | 114 %v0 = load i8* %__0, align 1 |
| 156 %v1 = zext i8 %v0 to i16 | 115 %v1 = zext i8 %v0 to i16 |
| 157 %__3 = bitcast [2 x i8]* @i16v to i16* | 116 %__3 = bitcast [2 x i8]* @i16v to i16* |
| 158 store i16 %v1, i16* %__3, align 1 | 117 store i16 %v1, i16* %__3, align 1 |
| 159 %v2 = zext i8 %v0 to i32 | 118 %v2 = zext i8 %v0 to i32 |
| 160 %__5 = bitcast [4 x i8]* @i32v to i32* | 119 %__5 = bitcast [4 x i8]* @i32v to i32* |
| 161 store i32 %v2, i32* %__5, align 1 | 120 store i32 %v2, i32* %__5, align 1 |
| 162 %v3 = zext i8 %v0 to i64 | 121 %v3 = zext i8 %v0 to i64 |
| 163 %__7 = bitcast [8 x i8]* @i64v to i64* | 122 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 164 store i64 %v3, i64* %__7, align 1 | 123 store i64 %v3, i64* %__7, align 1 |
| 165 ret void | 124 ret void |
| 166 } | 125 } |
| 167 ; CHECK: from_uint8: | 126 ; CHECK: from_uint8: |
| 168 ; CHECK: mov al, byte ptr [ | 127 ; CHECK: u8v |
| 169 ; CHECK-NEXT: movzx cx, al | 128 ; CHECK: movzx |
| 170 ; CHECK-NEXT: mov word ptr [ | 129 ; CHECK: i16v |
| 171 ; CHECK-NEXT: movzx ecx, al | 130 ; CHECK: movzx |
| 172 ; CHECK-NEXT: mov dword ptr [ | 131 ; CHECK: i32v |
| 173 ; CHECK-NEXT: movzx eax, al | 132 ; CHECK: movzx |
| 174 ; CHECK-NEXT: mov ecx, 0 | 133 ; CHECK: mov {{.*}}, 0 |
| 175 ; CHECK-NEXT: mov dword ptr [i64v+4], | 134 ; CHECK: i64v |
| 176 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 177 ; | |
| 178 ; OPTM1: from_uint8: | |
| 179 ; OPTM1: u8v | |
| 180 ; OPTM1: movzx | |
| 181 ; OPTM1: i16v | |
| 182 ; OPTM1: movzx | |
| 183 ; OPTM1: i32v | |
| 184 ; OPTM1: movzx | |
| 185 ; OPTM1: mov {{.*}}, 0 | |
| 186 ; OPTM1: i64v | |
| 187 | 135 |
| 188 define void @from_uint16() { | 136 define void @from_uint16() { |
| 189 entry: | 137 entry: |
| 190 %__0 = bitcast [2 x i8]* @u16v to i16* | 138 %__0 = bitcast [2 x i8]* @u16v to i16* |
| 191 %v0 = load i16* %__0, align 1 | 139 %v0 = load i16* %__0, align 1 |
| 192 %v1 = trunc i16 %v0 to i8 | 140 %v1 = trunc i16 %v0 to i8 |
| 193 %__3 = bitcast [1 x i8]* @i8v to i8* | 141 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 194 store i8 %v1, i8* %__3, align 1 | 142 store i8 %v1, i8* %__3, align 1 |
| 195 %v2 = zext i16 %v0 to i32 | 143 %v2 = zext i16 %v0 to i32 |
| 196 %__5 = bitcast [4 x i8]* @i32v to i32* | 144 %__5 = bitcast [4 x i8]* @i32v to i32* |
| 197 store i32 %v2, i32* %__5, align 1 | 145 store i32 %v2, i32* %__5, align 1 |
| 198 %v3 = zext i16 %v0 to i64 | 146 %v3 = zext i16 %v0 to i64 |
| 199 %__7 = bitcast [8 x i8]* @i64v to i64* | 147 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 200 store i64 %v3, i64* %__7, align 1 | 148 store i64 %v3, i64* %__7, align 1 |
| 201 ret void | 149 ret void |
| 202 } | 150 } |
| 203 ; CHECK: from_uint16: | 151 ; CHECK: from_uint16: |
| 204 ; CHECK: mov ax, word ptr [ | 152 ; CHECK: u16v |
| 205 ; CHECK-NEXT: mov cx, ax | 153 ; CHECK: i8v |
| 206 ; CHECK-NEXT: mov byte ptr [ | 154 ; CHECK: movzx |
| 207 ; CHECK-NEXT: movzx ecx, ax | 155 ; CHECK: i32v |
| 208 ; CHECK-NEXT: mov dword ptr [ | 156 ; CHECK: movzx |
| 209 ; CHECK-NEXT: movzx eax, ax | 157 ; CHECK: mov {{.*}}, 0 |
| 210 ; CHECK-NEXT: mov ecx, 0 | 158 ; CHECK: i64v |
| 211 ; CHECK-NEXT: mov dword ptr [i64v+4], | |
| 212 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 213 ; | |
| 214 ; OPTM1: from_uint16: | |
| 215 ; OPTM1: u16v | |
| 216 ; OPTM1: i8v | |
| 217 ; OPTM1: movzx | |
| 218 ; OPTM1: i32v | |
| 219 ; OPTM1: movzx | |
| 220 ; OPTM1: mov {{.*}}, 0 | |
| 221 ; OPTM1: i64v | |
| 222 | 159 |
| 223 define void @from_uint32() { | 160 define void @from_uint32() { |
| 224 entry: | 161 entry: |
| 225 %__0 = bitcast [4 x i8]* @u32v to i32* | 162 %__0 = bitcast [4 x i8]* @u32v to i32* |
| 226 %v0 = load i32* %__0, align 1 | 163 %v0 = load i32* %__0, align 1 |
| 227 %v1 = trunc i32 %v0 to i8 | 164 %v1 = trunc i32 %v0 to i8 |
| 228 %__3 = bitcast [1 x i8]* @i8v to i8* | 165 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 229 store i8 %v1, i8* %__3, align 1 | 166 store i8 %v1, i8* %__3, align 1 |
| 230 %v2 = trunc i32 %v0 to i16 | 167 %v2 = trunc i32 %v0 to i16 |
| 231 %__5 = bitcast [2 x i8]* @i16v to i16* | 168 %__5 = bitcast [2 x i8]* @i16v to i16* |
| 232 store i16 %v2, i16* %__5, align 1 | 169 store i16 %v2, i16* %__5, align 1 |
| 233 %v3 = zext i32 %v0 to i64 | 170 %v3 = zext i32 %v0 to i64 |
| 234 %__7 = bitcast [8 x i8]* @i64v to i64* | 171 %__7 = bitcast [8 x i8]* @i64v to i64* |
| 235 store i64 %v3, i64* %__7, align 1 | 172 store i64 %v3, i64* %__7, align 1 |
| 236 ret void | 173 ret void |
| 237 } | 174 } |
| 238 ; CHECK: from_uint32: | 175 ; CHECK: from_uint32: |
| 239 ; CHECK: mov eax, dword ptr [ | 176 ; CHECK: u32v |
| 240 ; CHECK-NEXT: mov ecx, eax | 177 ; CHECK: i8v |
| 241 ; CHECK-NEXT: mov byte ptr [ | 178 ; CHECK: i16v |
| 242 ; CHECK-NEXT: mov ecx, eax | 179 ; CHECK: mov {{.*}}, 0 |
| 243 ; CHECK-NEXT: mov word ptr [ | 180 ; CHECK: i64v |
| 244 ; CHECK-NEXT: mov ecx, 0 | |
| 245 ; CHECK-NEXT: mov dword ptr [i64v+4], | |
| 246 ; CHECK-NEXT: mov dword ptr [i64v], | |
| 247 ; | |
| 248 ; OPTM1: from_uint32: | |
| 249 ; OPTM1: u32v | |
| 250 ; OPTM1: i8v | |
| 251 ; OPTM1: i16v | |
| 252 ; OPTM1: mov {{.*}}, 0 | |
| 253 ; OPTM1: i64v | |
| 254 | 181 |
| 255 define void @from_uint64() { | 182 define void @from_uint64() { |
| 256 entry: | 183 entry: |
| 257 %__0 = bitcast [8 x i8]* @u64v to i64* | 184 %__0 = bitcast [8 x i8]* @u64v to i64* |
| 258 %v0 = load i64* %__0, align 1 | 185 %v0 = load i64* %__0, align 1 |
| 259 %v1 = trunc i64 %v0 to i8 | 186 %v1 = trunc i64 %v0 to i8 |
| 260 %__3 = bitcast [1 x i8]* @i8v to i8* | 187 %__3 = bitcast [1 x i8]* @i8v to i8* |
| 261 store i8 %v1, i8* %__3, align 1 | 188 store i8 %v1, i8* %__3, align 1 |
| 262 %v2 = trunc i64 %v0 to i16 | 189 %v2 = trunc i64 %v0 to i16 |
| 263 %__5 = bitcast [2 x i8]* @i16v to i16* | 190 %__5 = bitcast [2 x i8]* @i16v to i16* |
| 264 store i16 %v2, i16* %__5, align 1 | 191 store i16 %v2, i16* %__5, align 1 |
| 265 %v3 = trunc i64 %v0 to i32 | 192 %v3 = trunc i64 %v0 to i32 |
| 266 %__7 = bitcast [4 x i8]* @i32v to i32* | 193 %__7 = bitcast [4 x i8]* @i32v to i32* |
| 267 store i32 %v3, i32* %__7, align 1 | 194 store i32 %v3, i32* %__7, align 1 |
| 268 ret void | 195 ret void |
| 269 } | 196 } |
| 270 ; CHECK: from_uint64: | 197 ; CHECK: from_uint64: |
| 271 ; CHECK: mov eax, dword ptr [ | 198 ; CHECK: u64v |
| 272 ; CHECK-NEXT: mov ecx, eax | 199 ; CHECK: i8v |
| 273 ; CHECK-NEXT: mov byte ptr [ | 200 ; CHECK: i16v |
| 274 ; CHECK-NEXT: mov ecx, eax | 201 ; CHECK: i32v |
| 275 ; CHECK-NEXT: mov word ptr [ | |
| 276 ; CHECK-NEXT: mov dword ptr [ | |
| 277 ; | |
| 278 ; OPTM1: from_uint64: | |
| 279 ; OPTM1: u64v | |
| 280 ; OPTM1: i8v | |
| 281 ; OPTM1: i16v | |
| 282 ; OPTM1: i32v | |
| 283 | 202 |
| 284 ; ERRORS-NOT: ICE translation error | 203 ; ERRORS-NOT: ICE translation error |
| 285 ; DUMP-NOT: SZ | 204 ; DUMP-NOT: SZ |
| OLD | NEW |