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Side by Side Diff: src/x64/assembler-x64.h

Issue 300004: X64 Win64: Reimplement fmod so that it works. (Closed)
Patch Set: And it lints. Created 11 years, 2 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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276 // The result of negating a hint is as if the corresponding condition 276 // The result of negating a hint is as if the corresponding condition
277 // were negated by NegateCondition. That is, no_hint is mapped to 277 // were negated by NegateCondition. That is, no_hint is mapped to
278 // itself and not_taken and taken are mapped to each other. 278 // itself and not_taken and taken are mapped to each other.
279 inline Hint NegateHint(Hint hint) { 279 inline Hint NegateHint(Hint hint) {
280 return (hint == no_hint) 280 return (hint == no_hint)
281 ? no_hint 281 ? no_hint
282 : ((hint == not_taken) ? taken : not_taken); 282 : ((hint == not_taken) ? taken : not_taken);
283 } 283 }
284 284
285 285
286 // FPU status word bits
287
288 enum FPUStatus {
289 kInvalidOperandException = 0x01,
290 kDenormalizedOperandException = 0x02,
291 kZeroDivideException = 0x04,
292 kOverflowException = 0x08,
293 kUnderflowException = 0x10,
294 kPrecisionException = 0x20,
295 kAnyExceptionMask = 0x3f, // All of the above.
296 kStackFault = 0x40,
297 kErrorSummary = 0x80,
298 kCondition0 = 0x100,
299 kCondition1 = 0x200,
300 kCondition2 = 0x400,
301 kCondition3 = 0x4000
302 };
303
304
286 // ----------------------------------------------------------------------------- 305 // -----------------------------------------------------------------------------
287 // Machine instruction Immediates 306 // Machine instruction Immediates
288 307
289 class Immediate BASE_EMBEDDED { 308 class Immediate BASE_EMBEDDED {
290 public: 309 public:
291 explicit Immediate(int32_t value) : value_(value) {} 310 explicit Immediate(int32_t value) : value_(value) {}
292 311
293 private: 312 private:
294 int32_t value_; 313 int32_t value_;
295 314
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320 Operand(Register base, 339 Operand(Register base,
321 Register index, 340 Register index,
322 ScaleFactor scale, 341 ScaleFactor scale,
323 int32_t disp); 342 int32_t disp);
324 343
325 // [index*scale + disp/r] 344 // [index*scale + disp/r]
326 Operand(Register index, 345 Operand(Register index,
327 ScaleFactor scale, 346 ScaleFactor scale,
328 int32_t disp); 347 int32_t disp);
329 348
349 // New operand based on previous operand and a fixed displacement.
350 Operand(const Operand& base, int32_t displacement);
351
330 private: 352 private:
331 byte rex_; 353 byte rex_;
332 byte buf_[10]; 354 byte buf_[10];
333 // The number of bytes in buf_. 355 // The number of bytes in buf_.
334 unsigned int len_; 356 unsigned int len_;
335 RelocInfo::Mode rmode_;
336 357
337 // Set the ModR/M byte without an encoded 'reg' register. The 358 // Set the ModR/M byte without an encoded 'reg' register. The
338 // register is encoded later as part of the emit_operand operation. 359 // register is encoded later as part of the emit_operand operation.
339 // set_modrm can be called before or after set_sib and set_disp*. 360 // set_modrm can be called before or after set_sib and set_disp*.
340 inline void set_modrm(int mod, Register rm); 361 inline void set_modrm(int mod, Register rm);
341 362
342 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1. 363 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
343 inline void set_sib(ScaleFactor scale, Register index, Register base); 364 inline void set_sib(ScaleFactor scale, Register index, Register base);
344 365
345 // Adds operand displacement fields (offsets added to the memory address). 366 // Adds operand displacement fields (offsets added to the memory address).
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925 } 946 }
926 947
927 void xor_(const Operand& dst, Register src) { 948 void xor_(const Operand& dst, Register src) {
928 arithmetic_op(0x31, src, dst); 949 arithmetic_op(0x31, src, dst);
929 } 950 }
930 951
931 void xor_(Register dst, Immediate src) { 952 void xor_(Register dst, Immediate src) {
932 immediate_arithmetic_op(0x6, dst, src); 953 immediate_arithmetic_op(0x6, dst, src);
933 } 954 }
934 955
956 void xorl(Register dst, Immediate src) {
957 immediate_arithmetic_op_32(0x6, dst, src);
958 }
959
935 void xor_(const Operand& dst, Immediate src) { 960 void xor_(const Operand& dst, Immediate src) {
936 immediate_arithmetic_op(0x6, dst, src); 961 immediate_arithmetic_op(0x6, dst, src);
937 } 962 }
938 963
939 // Bit operations. 964 // Bit operations.
940 void bt(const Operand& dst, Register src); 965 void bt(const Operand& dst, Register src);
941 void bts(const Operand& dst, Register src); 966 void bts(const Operand& dst, Register src);
942 967
943 // Miscellaneous 968 // Miscellaneous
944 void clc(); 969 void clc();
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999 void fld(int i); 1024 void fld(int i);
1000 1025
1001 void fld1(); 1026 void fld1();
1002 void fldz(); 1027 void fldz();
1003 1028
1004 void fld_s(const Operand& adr); 1029 void fld_s(const Operand& adr);
1005 void fld_d(const Operand& adr); 1030 void fld_d(const Operand& adr);
1006 1031
1007 void fstp_s(const Operand& adr); 1032 void fstp_s(const Operand& adr);
1008 void fstp_d(const Operand& adr); 1033 void fstp_d(const Operand& adr);
1034 void fst_d(const Operand& adr);
1035 void fstp(int stack_slot);
1036 void fst(int stack_slot);
1009 1037
1010 void fild_s(const Operand& adr); 1038 void fild_s(const Operand& adr);
1011 void fild_d(const Operand& adr); 1039 void fild_d(const Operand& adr);
1012 1040
1013 void fist_s(const Operand& adr); 1041 void fist_s(const Operand& adr);
1014 1042
1015 void fistp_s(const Operand& adr); 1043 void fistp_s(const Operand& adr);
1016 void fistp_d(const Operand& adr); 1044 void fistp_d(const Operand& adr);
1017 1045
1018 void fisttp_s(const Operand& adr); 1046 void fisttp_s(const Operand& adr);
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1033 void fmulp(int i = 1); 1061 void fmulp(int i = 1);
1034 void fdivp(int i = 1); 1062 void fdivp(int i = 1);
1035 void fprem(); 1063 void fprem();
1036 void fprem1(); 1064 void fprem1();
1037 1065
1038 void fxch(int i = 1); 1066 void fxch(int i = 1);
1039 void fincstp(); 1067 void fincstp();
1040 void ffree(int i = 0); 1068 void ffree(int i = 0);
1041 1069
1042 void ftst(); 1070 void ftst();
1071 void fucom(int i);
1043 void fucomp(int i); 1072 void fucomp(int i);
1044 void fucompp(); 1073 void fucompp();
1045 void fcompp(); 1074 void fcompp();
1046 void fnstsw_ax(); 1075 void fnstsw_ax();
1047 void fwait(); 1076 void fwait();
1048 void fnclex(); 1077 void fnclex();
1078 void fxam();
1049 1079
1050 void fsin(); 1080 void fsin();
1051 void fcos(); 1081 void fcos();
1052 1082
1053 void frndint(); 1083 void frndint();
1054 1084
1055 void sahf(); 1085 void sahf();
1056 1086
1057 // SSE2 instructions 1087 // SSE2 instructions
1058 void movsd(const Operand& dst, XMMRegister src); 1088 void movsd(const Operand& dst, XMMRegister src);
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1355 private: 1385 private:
1356 Assembler* assembler_; 1386 Assembler* assembler_;
1357 #ifdef DEBUG 1387 #ifdef DEBUG
1358 int space_before_; 1388 int space_before_;
1359 #endif 1389 #endif
1360 }; 1390 };
1361 1391
1362 } } // namespace v8::internal 1392 } } // namespace v8::internal
1363 1393
1364 #endif // V8_X64_ASSEMBLER_X64_H_ 1394 #endif // V8_X64_ASSEMBLER_X64_H_
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