Reduce register pressure on ARM, ARM64, and MIPS.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 594 matching lines @@
         EmitLoadStoreReg(LDR, rt, a, sz);
       }
     }
   }
   void str(Register rt, Address a, OperandSize sz = kDoubleWord) {
     EmitLoadStoreReg(STR, rt, a, sz);
   }
 
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
-    EmitCoditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
+    EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
   }
   void csinc(Register rd, Register rn, Register rm, Condition cond) {
-    EmitCoditionalSelect(CSINC, rd, rn, rm, cond, kDoubleWord);
+    EmitConditionalSelect(CSINC, rd, rn, rm, cond, kDoubleWord);
   }
   void cinc(Register rd, Register rn, Condition cond) {
     csinc(rd, rn, rn, InvertCondition(cond));
   }
   void cset(Register rd, Condition cond) {
     csinc(rd, ZR, ZR, InvertCondition(cond));
   }
+  void csinv(Register rd, Register rn, Register rm, Condition cond) {
+    EmitConditionalSelect(CSINV, rd, rn, rm, cond, kDoubleWord);
+  }
+  void cinv(Register rd, Register rn, Condition cond) {
+    csinv(rd, rn, rn, InvertCondition(cond));
+  }
+  void csetm(Register rd, Condition cond) {
+    csinv(rd, ZR, ZR, InvertCondition(cond));
+  }
 
   // Comparison.
   // rn cmp o.
   // For add and sub, to use SP for rn, o must be of type Operand::Extend.
   // For an unmodified rm in this case, use Operand(rm, UXTX, 0);
   void cmp(Register rn, Operand o) {
     subs(ZR, rn, o);
   }
   // rn cmp -o.
   void cmn(Register rn, Operand o) {
@@ skipping 367 matching lines @@
   void Asr(Register rd, Register rn, int shift) {
     add(rd, ZR, Operand(rn, ASR, shift));
   }
 
   void VRecps(VRegister vd, VRegister vn);
   void VRSqrts(VRegister vd, VRegister vn);
 
   void SmiUntag(Register reg) {
     Asr(reg, reg, kSmiTagSize);
   }
+  void SmiUntag(Register dst, Register src) {
+    Asr(dst, src, kSmiTagSize);
+  }
   void SmiTag(Register reg) {
     Lsl(reg, reg, kSmiTagSize);
   }
 
   // Branching to ExternalLabels.
   void Branch(const ExternalLabel* label, Register pp) {
     LoadExternalLabel(TMP, label, kNotPatchable, pp);
     br(TMP);
   }
 
@@ skipping 519 matching lines @@
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
         (static_cast<int32_t>(crm) << kRmShift) |
         (static_cast<int32_t>(cra) << kRaShift);
     Emit(encoding);
   }
 
-  void EmitCoditionalSelect(ConditionalSelectOp op,
-                            Register rd, Register rn, Register rm,
-                            Condition cond, OperandSize sz) {
+  void EmitConditionalSelect(ConditionalSelectOp op,
+                             Register rd, Register rn, Register rm,
+                             Condition cond, OperandSize sz) {
     ASSERT((rd != SP) && (rn != SP) && (rm != SP));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const Register crd = ConcreteRegister(rd);
     const Register crn = ConcreteRegister(rn);
     const Register crm = ConcreteRegister(rm);
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(crd) << kRdShift) |
         (static_cast<int32_t>(crn) << kRnShift) |
@@ skipping 83 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_