Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(1886)

Unified Diff: appengine/swarming/swarming_bot/api/platforms/osx.py

Issue 2993523002: swarming: round OSX temperature readings to 2 digits, trim sensor readings (Closed)
Patch Set: Created 3 years, 5 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « no previous file | no next file » | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: appengine/swarming/swarming_bot/api/platforms/osx.py
diff --git a/appengine/swarming/swarming_bot/api/platforms/osx.py b/appengine/swarming/swarming_bot/api/platforms/osx.py
index 1cb2a582fffb17aef7c0244ddbce43b36f9eb6dd..1d89302235b5aa1f39da180941e3af3a785e4611 100644
--- a/appengine/swarming/swarming_bot/api/platforms/osx.py
+++ b/appengine/swarming/swarming_bot/api/platforms/osx.py
@@ -119,93 +119,93 @@ class _SMC_Value(ctypes.Structure):
# TC0E, TC0F, TH0A, TH0B, TH0V, TP0P, TS0D, TS0P
_sensor_names = {
'TA0P': u'ambient', # 'hdd bay 1',
- 'TA0S': u'pci slot 1 pos 1',
- 'TA1S': u'pci slot 1 pos 2',
- 'TA3S': u'pci slot 2 pos 2',
+ #'TA0S': u'pci slot 1 pos 1',
+ #'TA1S': u'pci slot 1 pos 2',
+ #'TA3S': u'pci slot 2 pos 2',
'TB0T': u'enclosure bottom',
- 'TB2T': u'enclosure bottom 3',
- 'TC0D': u'cpu0 die core',
- 'TC0P': u'cpu0 proximity',
- 'TC1D': u'cpu1',
- 'TCAH': u'cpu0',
- 'TCDH': u'cpu3',
+ #'TB2T': u'enclosure bottom 3',
+ #'TC0D': u'cpu0 die core',
+ 'TC0P': u'cpu0', # 'cpu0 proximity'
+ #'TC1D': u'cpu1',
+ #'TCAH': u'cpu0',
+ #'TCDH': u'cpu3',
'TG0D': u'gpu0 diode',
'TG0P': u'gpu0 proximity',
- 'TG1H': u'gpu heatsink 2',
- 'TH0P': u'hdd bay 1',
- 'TH2P': u'hdd bay 3',
- 'TL0P': u'lcd proximity',
- 'TM0P': u'mem bank a1',
- 'TM1P': u'mem bank a2',
- 'TM2P': u'mem bank a3',
- 'TM3P': u'mem bank a4',
- 'TM4P': u'mem bank a5',
- 'TM5P': u'mem bank a6',
- 'TM6P': u'mem bank a7',
- 'TM7P': u'mem bank a8',
- 'TM8P': u'mem bank b1',
- 'TM9P': u'mem bank b2',
- 'TMA1': u'ram a1',
- 'TMA3': u'ram a3',
- 'TMAP': u'mem bank b3',
- 'TMB1': u'ram b1',
- 'TMB3': u'ram b3',
- 'TMBP': u'mem bank b4',
- 'TMCP': u'mem bank b5',
- 'TMDP': u'mem bank b6',
- 'TMEP': u'mem bank b7',
- 'TMFP': u'mem bank b8',
- 'TN0D': u'northbridge die core',
- 'TN0P': u'northbridge proximity',
- 'TO0P': u'optical drive',
- 'TW0P': u'wireless airport card',
- 'Th0H': u'main heatsink a',
- 'Th2H': u'main heatsink c',
- 'Tm0P': u'memory controller',
- 'Tp0C': u'power supply 1',
- 'Tp1C': u'power supply 2',
- 'Tp2P': u'power supply 3',
- 'Tp4P': u'power supply 5',
- 'TA1P': u'ambient 2',
- 'TA2S': u'pci slot 2 pos 1',
- 'TB1T': u'enclosure bottom 2',
- 'TB3T': u'enclosure bottom 4',
- 'TC0H': u'cpu0 heatsink',
- 'TC2D': u'cpu2',
- 'TC3D': u'cpu3',
- 'TCBH': u'cpu1',
- 'TCCH': u'cpu2',
- 'TG0H': u'gpu0 heatsink',
- 'TH1P': u'hdd bay 2',
- 'TH3P': u'hdd bay 4',
- 'TM0S': u'mem module a1',
- 'TM1S': u'mem module a2',
- 'TM2S': u'mem module a3',
- 'TM3S': u'mem module a4',
- 'TM4S': u'mem module a5',
- 'TM5S': u'mem module a6',
- 'TM6S': u'mem module a7',
- 'TM7S': u'mem module a8',
- 'TM8S': u'mem module b1',
- 'TM9S': u'mem module b2',
- 'TMA2': u'ram a2',
- 'TMA4': u'ram a4',
- 'TMAS': u'mem module b3',
- 'TMB2': u'ram b2',
- 'TMB4': u'ram b4',
- 'TMBS': u'mem module b4',
- 'TMCS': u'mem module b5',
- 'TMDS': u'mem module b6',
- 'TMES': u'mem module b7',
- 'TMFS': u'mem module b8',
- 'TN0H': u'northbridge',
- 'TN1P': u'northbridge 2',
- 'TS0C': u'expansion slots',
- 'Th1H': u'main heatsink b',
- 'Tp0P': u'power supply 1',
- 'Tp1P': u'power supply 2',
- 'Tp3P': u'power supply 4',
- 'Tp5P': u'power supply 6',
+ #'TG1H': u'gpu heatsink 2',
+ #'TH0P': u'hdd bay 1',
+ #'TH2P': u'hdd bay 3',
+ #'TL0P': u'lcd proximity',
+ #'TM0P': u'mem bank a1',
+ #'TM1P': u'mem bank a2',
+ #'TM2P': u'mem bank a3',
+ #'TM3P': u'mem bank a4',
+ #'TM4P': u'mem bank a5',
+ #'TM5P': u'mem bank a6',
+ #'TM6P': u'mem bank a7',
+ #'TM7P': u'mem bank a8',
+ #'TM8P': u'mem bank b1',
+ #'TM9P': u'mem bank b2',
+ #'TMA1': u'ram a1',
+ #'TMA3': u'ram a3',
+ #'TMAP': u'mem bank b3',
+ #'TMB1': u'ram b1',
+ #'TMB3': u'ram b3',
+ #'TMBP': u'mem bank b4',
+ #'TMCP': u'mem bank b5',
+ #'TMDP': u'mem bank b6',
+ #'TMEP': u'mem bank b7',
+ #'TMFP': u'mem bank b8',
+ #'TN0D': u'northbridge die core',
+ #'TN0P': u'northbridge proximity',
+ #'TO0P': u'optical drive',
+ #'TW0P': u'wireless airport card',
+ #'Th0H': u'main heatsink a',
+ #'Th2H': u'main heatsink c',
+ #'Tm0P': u'memory controller',
+ 'Tp0C': u'power supply C',
+ #'Tp1C': u'power supply 2',
+ #'Tp2P': u'power supply 3',
+ #'Tp4P': u'power supply 5',
+ #'TA1P': u'ambient 2',
+ #'TA2S': u'pci slot 2 pos 1',
+ #'TB1T': u'enclosure bottom 2',
+ #'TB3T': u'enclosure bottom 4',
+ #'TC0H': u'cpu0 heatsink',
+ #'TC2D': u'cpu2',
+ #'TC3D': u'cpu3',
+ #'TCBH': u'cpu1',
+ #'TCCH': u'cpu2',
+ #'TG0H': u'gpu0 heatsink',
+ #'TH1P': u'hdd bay 2',
+ #'TH3P': u'hdd bay 4',
+ #'TM0S': u'mem module a1',
+ #'TM1S': u'mem module a2',
+ #'TM2S': u'mem module a3',
+ #'TM3S': u'mem module a4',
+ #'TM4S': u'mem module a5',
+ #'TM5S': u'mem module a6',
+ #'TM6S': u'mem module a7',
+ #'TM7S': u'mem module a8',
+ #'TM8S': u'mem module b1',
+ #'TM9S': u'mem module b2',
+ #'TMA2': u'ram a2',
+ #'TMA4': u'ram a4',
+ #'TMAS': u'mem module b3',
+ #'TMB2': u'ram b2',
+ #'TMB4': u'ram b4',
+ #'TMBS': u'mem module b4',
+ #'TMCS': u'mem module b5',
+ #'TMDS': u'mem module b6',
+ #'TMES': u'mem module b7',
+ #'TMFS': u'mem module b8',
+ #'TN0H': u'northbridge',
+ #'TN1P': u'northbridge 2',
+ #'TS0C': u'expansion slots',
+ #'Th1H': u'main heatsink b',
+ 'Tp0P': u'power supply P',
+ #'Tp1P': u'power supply 2',
+ #'Tp3P': u'power supply 4',
+ #'Tp5P': u'power supply 6',
}
# _sensor_found_cache is set on the first call to _SMC_get_values.
@@ -285,12 +285,15 @@ def _SMC_get_value(conn, key):
t = ''.join(map(chr, val.type))
if t == 'sp78\0' and val.size == 2:
# Format is first byte signed int8, second byte uint8 fractional.
- return float(ctypes.c_int8(val.bytes[0]).value) + (val.bytes[1] / 256.)
+ return round(
+ float(ctypes.c_int8(val.bytes[0]).value) + (val.bytes[1] / 256.),
+ 2)
if t == 'fpe2\0' and val.size == 2:
# Format is unsigned 14 bits big endian, 2 bits fractional.
- return (
- float((val.bytes[0] << 6) + (val.bytes[1] >> 2)) +
- (val.bytes[1] & 3) / 4.)
+ return round(
+ (float((val.bytes[0] << 6) + (val.bytes[1] >> 2)) +
+ (val.bytes[1] & 3) / 4.),
+ 2)
# TODO(maruel): Handler other formats like 64 bits long. This is used for fan
# speed.
logging.error(
« no previous file with comments | « no previous file | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698