Revise assertions and fix bug in the implementation of shifts

runtime/vm/intermediate_language_ia32.cc

Index: runtime/vm/intermediate_language_ia32.cc
diff --git a/runtime/vm/intermediate_language_ia32.cc b/runtime/vm/intermediate_language_ia32.cc
index 30a17114424da75b3de780cd5e8b7cad78aaefc4..1ee8f707340a455c8bfe7334c5cb08d0796022e0 100644
--- a/runtime/vm/intermediate_language_ia32.cc
+++ b/runtime/vm/intermediate_language_ia32.cc
@@ -6085,9 +6085,7 @@ void ShiftMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
     ASSERT(locs()->in(1).constant().IsSmi());
     const int32_t shift =
         reinterpret_cast<int32_t>(locs()->in(1).constant().raw()) >> 1;
-    // TODO(alexmarkov): figure out why the following assertion fails on ia32
-    // ASSERT(!has_shift_count_check());
-    // ASSERT(shift >= 0);
+    ASSERT(shift >= 0);
     switch (op_kind()) {
       case Token::kSHR: {
         if (shift > 31) {
@@ -6161,7 +6159,7 @@ void ShiftMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
     // sarl operation masks the count to 5 bits and
     // shrdl is undefined with count > operand size (32)
     __ SmiUntag(ECX);
-    if (has_shift_count_check()) {
+    if (!IsShiftCountInRange()) {
       __ cmpl(ECX, Immediate(kMintShiftCountLimit));
       __ j(ABOVE, deopt);
     }