Revise assertions and fix bug in the implementation of shifts

runtime/vm/intermediate_language_x64.cc

Index: runtime/vm/intermediate_language_x64.cc
diff --git a/runtime/vm/intermediate_language_x64.cc b/runtime/vm/intermediate_language_x64.cc
index b3c574a17f198351d61e03cb5343dbf35fa8d63c..dcb18e61ac1314ef982334ce524c623e49175e38 100644
--- a/runtime/vm/intermediate_language_x64.cc
+++ b/runtime/vm/intermediate_language_x64.cc
@@ -6072,14 +6072,14 @@ void ShiftMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
     ASSERT(locs()->in(1).constant().IsSmi());
     const int64_t shift =
         reinterpret_cast<int64_t>(locs()->in(1).constant().raw()) >> 1;
-    // TODO(alexmarkov): revise and uncomment the following assertions
-    // ASSERT(!has_shift_count_check());
-    // ASSERT((0 <= shift) && (shift < 64));
+    ASSERT(shift >= 0);
     switch (op_kind()) {
       case Token::kSHR:
-        __ sarq(left, Immediate(shift));
+        __ sarq(left,
+                Immediate(Utils::Minimum<int64_t>(shift, kBitsPerWord - 1)));
         break;
       case Token::kSHL: {
+        ASSERT(shift < 64);
         if (can_overflow()) {
           // Check for overflow.
           Register temp = locs()->temp(0).reg();
@@ -6102,7 +6102,7 @@ void ShiftMintOpInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
     // sarl operation masks the count to 5 bits and
     // shrd is undefined with count > operand size (32)

[regis, 2017/07/11 18:45:55]

This last comment does not look correct? shrd with a 64-bit destination
considers 6 bits of the count.

[alexmarkov, 2017/07/11 19:39:23]

Done.

     __ SmiUntag(RCX);
-    if (has_shift_count_check()) {
+    if (!IsShiftCountInRange()) {
       __ cmpq(RCX, Immediate(kMintShiftCountLimit));
       __ j(ABOVE, deopt);
     }