VM: Re-format to use at most one newline between functions

runtime/vm/disassembler_arm.cc

Index: runtime/vm/disassembler_arm.cc
diff --git a/runtime/vm/disassembler_arm.cc b/runtime/vm/disassembler_arm.cc
index 0058f2944d530ea2ea1616739560bac225b32de8..47be39d9da68a691b49606e0f54732e4d31bd5a7 100644
--- a/runtime/vm/disassembler_arm.cc
+++ b/runtime/vm/disassembler_arm.cc
@@ -77,12 +77,10 @@ class ARMDecoder : public ValueObject {
   DISALLOW_COPY_AND_ASSIGN(ARMDecoder);
 };
 
-
 // Support for assertions in the ARMDecoder formatting functions.
 #define STRING_STARTS_WITH(string, compare_string)                             \
   (strncmp(string, compare_string, strlen(compare_string)) == 0)
 
-
 // Append the str to the output buffer.
 void ARMDecoder::Print(const char* str) {
   char cur = *str++;
@@ -93,7 +91,6 @@ void ARMDecoder::Print(const char* str) {
   buffer_[buffer_pos_] = '\0';
 }
 
-
 // These condition names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* cond_names[kNumberOfConditions] = {
@@ -101,13 +98,11 @@ static const char* cond_names[kNumberOfConditions] = {
     "hi", "ls", "ge", "lt", "gt", "le", "",   "invalid",
 };
 
-
 // Print the condition guarding the instruction.
 void ARMDecoder::PrintCondition(Instr* instr) {
   Print(cond_names[instr->ConditionField()]);
 }
 
-
 // These register names are defined in a way to match the native disassembler
 // formatting, except for register alias pp (r5).
 // See for example the command "objdump -d <binary file>".
@@ -121,7 +116,6 @@ static const char* reg_names[kNumberOfCpuRegisters] = {
 #endif
 };
 
-
 // Print the register name according to the active name converter.
 void ARMDecoder::PrintRegister(int reg) {
   ASSERT(0 <= reg);
@@ -129,7 +123,6 @@ void ARMDecoder::PrintRegister(int reg) {
   Print(reg_names[reg]);
 }
 
-
 void ARMDecoder::PrintSRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfSRegisters);
@@ -137,7 +130,6 @@ void ARMDecoder::PrintSRegister(int reg) {
                              remaining_size_in_buffer(), "s%d", reg);
 }
 
-
 void ARMDecoder::PrintDRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfDRegisters);
@@ -145,7 +137,6 @@ void ARMDecoder::PrintDRegister(int reg) {
                              remaining_size_in_buffer(), "d%d", reg);
 }
 
-
 void ARMDecoder::PrintQRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfQRegisters);
@@ -153,12 +144,10 @@ void ARMDecoder::PrintQRegister(int reg) {
                              remaining_size_in_buffer(), "q%d", reg);
 }
 
-
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* shift_names[kMaxShift] = {"lsl", "lsr", "asr", "ror"};
 
-
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
 void ARMDecoder::PrintShiftRm(Instr* instr) {
@@ -193,7 +182,6 @@ void ARMDecoder::PrintShiftRm(Instr* instr) {
   }
 }
 
-
 // Print the immediate operand for the instruction. Generally used for data
 // processing instructions.
 void ARMDecoder::PrintShiftImm(Instr* instr) {
@@ -204,7 +192,6 @@ void ARMDecoder::PrintShiftImm(Instr* instr) {
                              remaining_size_in_buffer(), "#%d", imm);
 }
 
-
 // Print PU formatting to reduce complexity of FormatOption.
 void ARMDecoder::PrintPU(Instr* instr) {
   switch (instr->PUField()) {
@@ -231,7 +218,6 @@ void ARMDecoder::PrintPU(Instr* instr) {
   }
 }
 
-
 // Handle all register based formatting in these functions to reduce the
 // complexity of FormatOption.
 int ARMDecoder::FormatRegister(Instr* instr, const char* format) {
@@ -287,7 +273,6 @@ int ARMDecoder::FormatRegister(Instr* instr, const char* format) {
   return -1;
 }
 
-
 int ARMDecoder::FormatSRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 's');
   if (format[1] == 'n') {  // 'sn: Sn register
@@ -327,7 +312,6 @@ int ARMDecoder::FormatSRegister(Instr* instr, const char* format) {
   return -1;
 }
 
-
 void ARMDecoder::PrintDRegisterList(int start, int reg_count) {
   Print("{");
   for (int i = start; i < start + reg_count; i++) {
@@ -339,7 +323,6 @@ void ARMDecoder::PrintDRegisterList(int start, int reg_count) {
   Print("}");
 }
 
-
 int ARMDecoder::FormatDRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'd');
   if (format[1] == 'n') {  // 'dn: Dn register
@@ -371,7 +354,6 @@ int ARMDecoder::FormatDRegister(Instr* instr, const char* format) {
   return -1;
 }
 
-
 int ARMDecoder::FormatQRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'q');
   if (format[1] == 'n') {  // 'qn: Qn register
@@ -391,7 +373,6 @@ int ARMDecoder::FormatQRegister(Instr* instr, const char* format) {
   return -1;
 }
 
-
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
@@ -623,7 +604,6 @@ int ARMDecoder::FormatOption(Instr* instr, const char* format) {
   return -1;
 }
 
-
 // Format takes a formatting string for a whole instruction and prints it into
 // the output buffer. All escaped options are handed to FormatOption to be
 // parsed further.
@@ -640,14 +620,12 @@ void ARMDecoder::Format(Instr* instr, const char* format) {
   buffer_[buffer_pos_] = '\0';
 }
 
-
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARMDecoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
-
 void ARMDecoder::DecodeType01(Instr* instr) {
   if (!instr->IsDataProcessing()) {
     // miscellaneous, multiply, sync primitives, extra loads and stores.
@@ -932,7 +910,6 @@ void ARMDecoder::DecodeType01(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeType2(Instr* instr) {
   switch (instr->PUField()) {
     case 0: {
@@ -967,7 +944,6 @@ void ARMDecoder::DecodeType2(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeType3(Instr* instr) {
   if (instr->IsDivision()) {
     if (!TargetCPUFeatures::integer_division_supported()) {
@@ -1014,7 +990,6 @@ void ARMDecoder::DecodeType3(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeType4(Instr* instr) {
   if (instr->Bit(22) == 1) {
     Unknown(instr);  // Privileged mode currently not supported.
@@ -1025,12 +1000,10 @@ void ARMDecoder::DecodeType4(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeType5(Instr* instr) {
   Format(instr, "b'l'cond 'target ; 'dest");
 }
 
-
 void ARMDecoder::DecodeType6(Instr* instr) {
   if (instr->IsVFPDoubleTransfer()) {
     if (instr->Bit(8) == 0) {
@@ -1095,7 +1068,6 @@ void ARMDecoder::DecodeType6(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeType7(Instr* instr) {
   if (instr->Bit(24) == 1) {
     Format(instr, "svc'cond #'svc");
@@ -1327,7 +1299,6 @@ void ARMDecoder::DecodeType7(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) {
   ASSERT(instr->ConditionField() == kSpecialCondition);
   if (instr->Bit(6) == 1) {
@@ -1457,7 +1428,6 @@ void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) {
   }
 }
 
-
 void ARMDecoder::InstructionDecode(uword pc) {
   Instr* instr = Instr::At(pc);
 
@@ -1512,7 +1482,6 @@ void ARMDecoder::InstructionDecode(uword pc) {
   }
 }
 
-
 void Disassembler::DecodeInstruction(char* hex_buffer,
                                      intptr_t hex_size,
                                      char* human_buffer,