| Index: runtime/vm/assembler_arm.cc
|
| diff --git a/runtime/vm/assembler_arm.cc b/runtime/vm/assembler_arm.cc
|
| index c51cd60a14b8ff319876a1bf3117b95251a08e31..bacc77d4f064a816f77a4ad600d3c3feaa89ccd3 100644
|
| --- a/runtime/vm/assembler_arm.cc
|
| +++ b/runtime/vm/assembler_arm.cc
|
| @@ -35,7 +35,6 @@ uint32_t Address::encoding3() const {
|
| return encoding_;
|
| }
|
|
|
| -
|
| uint32_t Address::vencoding() const {
|
| ASSERT(kind_ == Immediate);
|
| uint32_t offset = encoding_ & kOffset12Mask;
|
| @@ -50,7 +49,6 @@ uint32_t Address::vencoding() const {
|
| return vencoding;
|
| }
|
|
|
| -
|
| void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
|
| ASSERT(Utils::IsAligned(data, 4));
|
| ASSERT(Utils::IsAligned(length, 4));
|
| @@ -61,13 +59,11 @@ void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::Emit(int32_t value) {
|
| AssemblerBuffer::EnsureCapacity ensured(&buffer_);
|
| buffer_.Emit<int32_t>(value);
|
| }
|
|
|
| -
|
| void Assembler::EmitType01(Condition cond,
|
| int type,
|
| Opcode opcode,
|
| @@ -85,7 +81,6 @@ void Assembler::EmitType01(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
|
| ASSERT(cond != kNoCondition);
|
| int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
|
| @@ -93,7 +88,6 @@ void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
|
| Emit(Assembler::EncodeBranchOffset(offset, encoding));
|
| }
|
|
|
| -
|
| void Assembler::EmitMemOp(Condition cond,
|
| bool load,
|
| bool byte,
|
| @@ -110,7 +104,6 @@ void Assembler::EmitMemOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitMemOpAddressMode3(Condition cond,
|
| int32_t mode,
|
| Register rd,
|
| @@ -122,7 +115,6 @@ void Assembler::EmitMemOpAddressMode3(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitMultiMemOp(Condition cond,
|
| BlockAddressMode am,
|
| bool load,
|
| @@ -136,7 +128,6 @@ void Assembler::EmitMultiMemOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitShiftImmediate(Condition cond,
|
| Shift opcode,
|
| Register rd,
|
| @@ -152,7 +143,6 @@ void Assembler::EmitShiftImmediate(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitShiftRegister(Condition cond,
|
| Shift opcode,
|
| Register rd,
|
| @@ -169,17 +159,14 @@ void Assembler::EmitShiftRegister(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), AND, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
|
| }
|
| @@ -192,107 +179,86 @@ void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), RSB, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::add(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ADD, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ADD, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::subs(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::adc(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ADC, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::adcs(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ADC, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::sbc(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), SBC, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::rsc(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), RSC, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::tst(Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), TST, 1, rn, R0, o);
|
| }
|
|
|
| -
|
| void Assembler::teq(Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), TEQ, 1, rn, R0, o);
|
| }
|
|
|
| -
|
| void Assembler::cmp(Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
|
| }
|
|
|
| -
|
| void Assembler::cmn(Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
|
| }
|
|
|
| -
|
| void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ORR, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::orrs(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), ORR, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::mov(Register rd, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), MOV, 0, R0, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::movs(Register rd, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), BIC, 0, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::bics(Register rd, Register rn, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), BIC, 1, rn, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::mvn(Register rd, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), MVN, 0, R0, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::mvns(Register rd, Operand o, Condition cond) {
|
| EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
|
| }
|
|
|
| -
|
| void Assembler::clz(Register rd, Register rm, Condition cond) {
|
| ASSERT(rd != kNoRegister);
|
| ASSERT(rm != kNoRegister);
|
| @@ -306,7 +272,6 @@ void Assembler::clz(Register rd, Register rm, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
|
| ASSERT(cond != kNoCondition);
|
| int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
|
| @@ -315,7 +280,6 @@ void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
|
| ASSERT(cond != kNoCondition);
|
| int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | B25 | B24 |
|
| @@ -324,7 +288,6 @@ void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitMulOp(Condition cond,
|
| int32_t opcode,
|
| Register rd,
|
| @@ -344,19 +307,16 @@ void Assembler::EmitMulOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
|
| // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
|
| EmitMulOp(cond, 0, R0, rd, rn, rm);
|
| }
|
|
|
| -
|
| // Like mul, but sets condition flags.
|
| void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
|
| EmitMulOp(cond, B20, R0, rd, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::mla(Register rd,
|
| Register rn,
|
| Register rm,
|
| @@ -367,7 +327,6 @@ void Assembler::mla(Register rd,
|
| EmitMulOp(cond, B21, ra, rd, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::mls(Register rd,
|
| Register rn,
|
| Register rm,
|
| @@ -383,7 +342,6 @@ void Assembler::mls(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::smull(Register rd_lo,
|
| Register rd_hi,
|
| Register rn,
|
| @@ -393,7 +351,6 @@ void Assembler::smull(Register rd_lo,
|
| EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::umull(Register rd_lo,
|
| Register rd_hi,
|
| Register rn,
|
| @@ -403,7 +360,6 @@ void Assembler::umull(Register rd_lo,
|
| EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::umlal(Register rd_lo,
|
| Register rd_hi,
|
| Register rn,
|
| @@ -413,7 +369,6 @@ void Assembler::umlal(Register rd_lo,
|
| EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::umaal(Register rd_lo,
|
| Register rd_hi,
|
| Register rn,
|
| @@ -433,7 +388,6 @@ void Assembler::umaal(Register rd_lo,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::EmitDivOp(Condition cond,
|
| int32_t opcode,
|
| Register rd,
|
| @@ -451,57 +405,46 @@ void Assembler::EmitDivOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
|
| EmitDivOp(cond, 0, rd, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
|
| EmitDivOp(cond, B21, rd, rn, rm);
|
| }
|
|
|
| -
|
| void Assembler::ldr(Register rd, Address ad, Condition cond) {
|
| EmitMemOp(cond, true, false, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::str(Register rd, Address ad, Condition cond) {
|
| EmitMemOp(cond, false, false, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::ldrb(Register rd, Address ad, Condition cond) {
|
| EmitMemOp(cond, true, true, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::strb(Register rd, Address ad, Condition cond) {
|
| EmitMemOp(cond, false, true, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::ldrh(Register rd, Address ad, Condition cond) {
|
| EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::strh(Register rd, Address ad, Condition cond) {
|
| EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
|
| EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
|
| EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
|
| }
|
|
|
| -
|
| void Assembler::ldrd(Register rd,
|
| Register rd2,
|
| Register rn,
|
| @@ -517,7 +460,6 @@ void Assembler::ldrd(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::strd(Register rd,
|
| Register rd2,
|
| Register rn,
|
| @@ -533,7 +475,6 @@ void Assembler::strd(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::ldm(BlockAddressMode am,
|
| Register base,
|
| RegList regs,
|
| @@ -542,7 +483,6 @@ void Assembler::ldm(BlockAddressMode am,
|
| EmitMultiMemOp(cond, am, true, base, regs);
|
| }
|
|
|
| -
|
| void Assembler::stm(BlockAddressMode am,
|
| Register base,
|
| RegList regs,
|
| @@ -551,7 +491,6 @@ void Assembler::stm(BlockAddressMode am,
|
| EmitMultiMemOp(cond, am, false, base, regs);
|
| }
|
|
|
| -
|
| void Assembler::ldrex(Register rt, Register rn, Condition cond) {
|
| ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
|
| ASSERT(rn != kNoRegister);
|
| @@ -564,7 +503,6 @@ void Assembler::ldrex(Register rt, Register rn, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
|
| ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
|
| ASSERT(rn != kNoRegister);
|
| @@ -579,7 +517,6 @@ void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::clrex() {
|
| ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
|
| int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
|
| @@ -587,7 +524,6 @@ void Assembler::clrex() {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::nop(Condition cond) {
|
| ASSERT(cond != kNoCondition);
|
| int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B25 |
|
| @@ -595,7 +531,6 @@ void Assembler::nop(Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(sn != kNoSRegister);
|
| @@ -610,7 +545,6 @@ void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(sn != kNoSRegister);
|
| @@ -625,7 +559,6 @@ void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovsrr(SRegister sm,
|
| Register rt,
|
| Register rt2,
|
| @@ -648,7 +581,6 @@ void Assembler::vmovsrr(SRegister sm,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovrrs(Register rt,
|
| Register rt2,
|
| SRegister sm,
|
| @@ -672,7 +604,6 @@ void Assembler::vmovrrs(Register rt,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT((i == 0) || (i == 1));
|
| @@ -688,7 +619,6 @@ void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovdrr(DRegister dm,
|
| Register rt,
|
| Register rt2,
|
| @@ -710,7 +640,6 @@ void Assembler::vmovdrr(DRegister dm,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovrrd(Register rt,
|
| Register rt2,
|
| DRegister dm,
|
| @@ -733,7 +662,6 @@ void Assembler::vmovrrd(Register rt,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(sd != kNoSRegister);
|
| @@ -745,7 +673,6 @@ void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
|
| @@ -758,7 +685,6 @@ void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(dd != kNoDRegister);
|
| @@ -770,7 +696,6 @@ void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vstrd(DRegister dd, Address ad, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
|
| @@ -803,7 +728,6 @@ void Assembler::EmitMultiVSMemOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitMultiVDMemOp(Condition cond,
|
| BlockAddressMode am,
|
| bool load,
|
| @@ -825,7 +749,6 @@ void Assembler::EmitMultiVDMemOp(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vldms(BlockAddressMode am,
|
| Register base,
|
| SRegister first,
|
| @@ -836,7 +759,6 @@ void Assembler::vldms(BlockAddressMode am,
|
| EmitMultiVSMemOp(cond, am, true, base, first, last - first + 1);
|
| }
|
|
|
| -
|
| void Assembler::vstms(BlockAddressMode am,
|
| Register base,
|
| SRegister first,
|
| @@ -847,7 +769,6 @@ void Assembler::vstms(BlockAddressMode am,
|
| EmitMultiVSMemOp(cond, am, false, base, first, last - first + 1);
|
| }
|
|
|
| -
|
| void Assembler::vldmd(BlockAddressMode am,
|
| Register base,
|
| DRegister first,
|
| @@ -859,7 +780,6 @@ void Assembler::vldmd(BlockAddressMode am,
|
| EmitMultiVDMemOp(cond, am, true, base, first, count);
|
| }
|
|
|
| -
|
| void Assembler::vstmd(BlockAddressMode am,
|
| Register base,
|
| DRegister first,
|
| @@ -871,7 +791,6 @@ void Assembler::vstmd(BlockAddressMode am,
|
| EmitMultiVDMemOp(cond, am, false, base, first, count);
|
| }
|
|
|
| -
|
| void Assembler::EmitVFPsss(Condition cond,
|
| int32_t opcode,
|
| SRegister sd,
|
| @@ -892,7 +811,6 @@ void Assembler::EmitVFPsss(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitVFPddd(Condition cond,
|
| int32_t opcode,
|
| DRegister dd,
|
| @@ -913,17 +831,14 @@ void Assembler::EmitVFPddd(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
|
| }
|
|
|
| -
|
| bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
|
| if (TargetCPUFeatures::arm_version() != ARMv7) {
|
| return false;
|
| @@ -941,7 +856,6 @@ bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
|
| return false;
|
| }
|
|
|
| -
|
| bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
|
| if (TargetCPUFeatures::arm_version() != ARMv7) {
|
| return false;
|
| @@ -959,7 +873,6 @@ bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
|
| return false;
|
| }
|
|
|
| -
|
| void Assembler::vadds(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -967,7 +880,6 @@ void Assembler::vadds(SRegister sd,
|
| EmitVFPsss(cond, B21 | B20, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vaddd(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -975,7 +887,6 @@ void Assembler::vaddd(DRegister dd,
|
| EmitVFPddd(cond, B21 | B20, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vsubs(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -983,7 +894,6 @@ void Assembler::vsubs(SRegister sd,
|
| EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vsubd(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -991,7 +901,6 @@ void Assembler::vsubd(DRegister dd,
|
| EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vmuls(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -999,7 +908,6 @@ void Assembler::vmuls(SRegister sd,
|
| EmitVFPsss(cond, B21, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vmuld(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -1007,7 +915,6 @@ void Assembler::vmuld(DRegister dd,
|
| EmitVFPddd(cond, B21, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vmlas(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -1015,7 +922,6 @@ void Assembler::vmlas(SRegister sd,
|
| EmitVFPsss(cond, 0, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vmlad(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -1023,7 +929,6 @@ void Assembler::vmlad(DRegister dd,
|
| EmitVFPddd(cond, 0, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vmlss(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -1031,7 +936,6 @@ void Assembler::vmlss(SRegister sd,
|
| EmitVFPsss(cond, B6, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vmlsd(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -1039,7 +943,6 @@ void Assembler::vmlsd(DRegister dd,
|
| EmitVFPddd(cond, B6, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vdivs(SRegister sd,
|
| SRegister sn,
|
| SRegister sm,
|
| @@ -1047,7 +950,6 @@ void Assembler::vdivs(SRegister sd,
|
| EmitVFPsss(cond, B23, sd, sn, sm);
|
| }
|
|
|
| -
|
| void Assembler::vdivd(DRegister dd,
|
| DRegister dn,
|
| DRegister dm,
|
| @@ -1055,27 +957,22 @@ void Assembler::vdivd(DRegister dd,
|
| EmitVFPddd(cond, B23, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vabss(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
|
| }
|
|
|
| -
|
| void Assembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
|
| }
|
|
|
| -
|
| void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
|
| }
|
| @@ -1084,7 +981,6 @@ void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
|
| }
|
|
|
| -
|
| void Assembler::EmitVFPsd(Condition cond,
|
| int32_t opcode,
|
| SRegister sd,
|
| @@ -1101,7 +997,6 @@ void Assembler::EmitVFPsd(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitVFPds(Condition cond,
|
| int32_t opcode,
|
| DRegister dd,
|
| @@ -1118,77 +1013,62 @@ void Assembler::EmitVFPds(Condition cond,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
|
| EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
|
| EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
|
| EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
|
| EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
|
| EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
|
| EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
|
| }
|
|
|
| -
|
| void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
|
| }
|
|
|
| -
|
| void Assembler::vcmpsz(SRegister sd, Condition cond) {
|
| EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
|
| }
|
|
|
| -
|
| void Assembler::vcmpdz(DRegister dd, Condition cond) {
|
| EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
|
| }
|
|
|
| -
|
| void Assembler::vmrs(Register rd, Condition cond) {
|
| ASSERT(TargetCPUFeatures::vfp_supported());
|
| ASSERT(cond != kNoCondition);
|
| @@ -1198,12 +1078,10 @@ void Assembler::vmrs(Register rd, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmstat(Condition cond) {
|
| vmrs(APSR, cond);
|
| }
|
|
|
| -
|
| static inline int ShiftOfOperandSize(OperandSize size) {
|
| switch (size) {
|
| case kByte:
|
| @@ -1229,7 +1107,6 @@ static inline int ShiftOfOperandSize(OperandSize size) {
|
| return -1;
|
| }
|
|
|
| -
|
| void Assembler::EmitSIMDqqq(int32_t opcode,
|
| OperandSize size,
|
| QRegister qd,
|
| @@ -1249,7 +1126,6 @@ void Assembler::EmitSIMDqqq(int32_t opcode,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::EmitSIMDddd(int32_t opcode,
|
| OperandSize size,
|
| DRegister dd,
|
| @@ -1267,12 +1143,10 @@ void Assembler::EmitSIMDddd(int32_t opcode,
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::vmovq(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
|
| }
|
|
|
| -
|
| void Assembler::vaddqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1280,12 +1154,10 @@ void Assembler::vaddqi(OperandSize sz,
|
| EmitSIMDqqq(B11, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vsubqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1293,12 +1165,10 @@ void Assembler::vsubqi(OperandSize sz,
|
| EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vmulqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1306,12 +1176,10 @@ void Assembler::vmulqi(OperandSize sz,
|
| EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vshlqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qm,
|
| @@ -1319,7 +1187,6 @@ void Assembler::vshlqi(OperandSize sz,
|
| EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vshlqu(OperandSize sz,
|
| QRegister qd,
|
| QRegister qm,
|
| @@ -1327,76 +1194,62 @@ void Assembler::vshlqu(OperandSize sz,
|
| EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vornq(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B21 | B20 | B8 | B4, kByte, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vandq(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B8 | B4, kByte, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vmvnq(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
|
| }
|
|
|
| -
|
| void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vabsqs(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord, qd, Q0,
|
| qm);
|
| }
|
|
|
| -
|
| void Assembler::vnegqs(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8 | B7, kSWord,
|
| qd, Q0, qm);
|
| }
|
|
|
| -
|
| void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord, qd,
|
| Q0, qm);
|
| }
|
|
|
| -
|
| void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vrsqrteqs(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7, kSWord,
|
| qd, Q0, qm);
|
| }
|
|
|
| -
|
| void Assembler::vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B21 | B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
|
| ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
|
| int code = 0;
|
| @@ -1428,18 +1281,15 @@ void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
|
| static_cast<DRegister>(code & 0xf), dm);
|
| }
|
|
|
| -
|
| void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
|
| ASSERT((len >= 1) && (len <= 4));
|
| EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
|
| }
|
|
|
| -
|
| void Assembler::vzipqw(QRegister qd, QRegister qm) {
|
| EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
|
| }
|
|
|
| -
|
| void Assembler::vceqqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1447,12 +1297,10 @@ void Assembler::vceqqi(OperandSize sz,
|
| EmitSIMDqqq(B24 | B11 | B4, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vceqqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B11 | B10 | B9, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcgeqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1460,7 +1308,6 @@ void Assembler::vcgeqi(OperandSize sz,
|
| EmitSIMDqqq(B9 | B8 | B4, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcugeqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1468,12 +1315,10 @@ void Assembler::vcugeqi(OperandSize sz,
|
| EmitSIMDqqq(B24 | B9 | B8 | B4, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcgeqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B24 | B11 | B10 | B9, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcgtqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1481,7 +1326,6 @@ void Assembler::vcgtqi(OperandSize sz,
|
| EmitSIMDqqq(B9 | B8, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcugtqi(OperandSize sz,
|
| QRegister qd,
|
| QRegister qn,
|
| @@ -1489,27 +1333,22 @@ void Assembler::vcugtqi(OperandSize sz,
|
| EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) {
|
| EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm);
|
| }
|
|
|
| -
|
| void Assembler::bkpt(uint16_t imm16) {
|
| Emit(BkptEncoding(imm16));
|
| }
|
|
|
| -
|
| void Assembler::b(Label* label, Condition cond) {
|
| EmitBranch(cond, label, false);
|
| }
|
|
|
| -
|
| void Assembler::bl(Label* label, Condition cond) {
|
| EmitBranch(cond, label, true);
|
| }
|
|
|
| -
|
| void Assembler::bx(Register rm, Condition cond) {
|
| ASSERT(rm != kNoRegister);
|
| ASSERT(cond != kNoCondition);
|
| @@ -1519,7 +1358,6 @@ void Assembler::bx(Register rm, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::blx(Register rm, Condition cond) {
|
| ASSERT(rm != kNoRegister);
|
| ASSERT(cond != kNoCondition);
|
| @@ -1529,7 +1367,6 @@ void Assembler::blx(Register rm, Condition cond) {
|
| Emit(encoding);
|
| }
|
|
|
| -
|
| void Assembler::MarkExceptionHandler(Label* label) {
|
| EmitType01(AL, 1, TST, 1, PC, R0, Operand(0));
|
| Label l;
|
| @@ -1538,7 +1375,6 @@ void Assembler::MarkExceptionHandler(Label* label) {
|
| Bind(&l);
|
| }
|
|
|
| -
|
| void Assembler::Drop(intptr_t stack_elements) {
|
| ASSERT(stack_elements >= 0);
|
| if (stack_elements > 0) {
|
| @@ -1546,12 +1382,10 @@ void Assembler::Drop(intptr_t stack_elements) {
|
| }
|
| }
|
|
|
| -
|
| intptr_t Assembler::FindImmediate(int32_t imm) {
|
| return object_pool_wrapper_.FindImmediate(imm);
|
| }
|
|
|
| -
|
| // Uses a code sequence that can easily be decoded.
|
| void Assembler::LoadWordFromPoolOffset(Register rd,
|
| int32_t offset,
|
| @@ -1605,13 +1439,11 @@ void Assembler::CheckCodePointer() {
|
| #endif
|
| }
|
|
|
| -
|
| void Assembler::RestoreCodePointer() {
|
| ldr(CODE_REG, Address(FP, kPcMarkerSlotFromFp * kWordSize));
|
| CheckCodePointer();
|
| }
|
|
|
| -
|
| void Assembler::LoadPoolPointer(Register reg) {
|
| // Load new pool pointer.
|
| CheckCodePointer();
|
| @@ -1619,12 +1451,10 @@ void Assembler::LoadPoolPointer(Register reg) {
|
| set_constant_pool_allowed(reg == PP);
|
| }
|
|
|
| -
|
| void Assembler::LoadIsolate(Register rd) {
|
| ldr(rd, Address(THR, Thread::isolate_offset()));
|
| }
|
|
|
| -
|
| bool Assembler::CanLoadFromObjectPool(const Object& object) const {
|
| ASSERT(!object.IsICData() || ICData::Cast(object).IsOriginal());
|
| ASSERT(!object.IsField() || Field::Cast(object).IsOriginal());
|
| @@ -1638,7 +1468,6 @@ bool Assembler::CanLoadFromObjectPool(const Object& object) const {
|
| return true;
|
| }
|
|
|
| -
|
| void Assembler::LoadObjectHelper(Register rd,
|
| const Object& object,
|
| Condition cond,
|
| @@ -1665,19 +1494,16 @@ void Assembler::LoadObjectHelper(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
|
| LoadObjectHelper(rd, object, cond, /* is_unique = */ false, PP);
|
| }
|
|
|
| -
|
| void Assembler::LoadUniqueObject(Register rd,
|
| const Object& object,
|
| Condition cond) {
|
| LoadObjectHelper(rd, object, cond, /* is_unique = */ true, PP);
|
| }
|
|
|
| -
|
| void Assembler::LoadFunctionFromCalleePool(Register dst,
|
| const Function& function,
|
| Register new_pp) {
|
| @@ -1686,7 +1512,6 @@ void Assembler::LoadFunctionFromCalleePool(Register dst,
|
| LoadWordFromPoolOffset(dst, offset - kHeapObjectTag, new_pp, AL);
|
| }
|
|
|
| -
|
| void Assembler::LoadNativeEntry(Register rd,
|
| const ExternalLabel* label,
|
| Patchability patchable,
|
| @@ -1696,7 +1521,6 @@ void Assembler::LoadNativeEntry(Register rd,
|
| LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
|
| }
|
|
|
| -
|
| void Assembler::PushObject(const Object& object) {
|
| ASSERT(!object.IsICData() || ICData::Cast(object).IsOriginal());
|
| ASSERT(!object.IsField() || Field::Cast(object).IsOriginal());
|
| @@ -1704,7 +1528,6 @@ void Assembler::PushObject(const Object& object) {
|
| Push(IP);
|
| }
|
|
|
| -
|
| void Assembler::CompareObject(Register rn, const Object& object) {
|
| ASSERT(!object.IsICData() || ICData::Cast(object).IsOriginal());
|
| ASSERT(!object.IsField() || Field::Cast(object).IsOriginal());
|
| @@ -1717,7 +1540,6 @@ void Assembler::CompareObject(Register rn, const Object& object) {
|
| }
|
| }
|
|
|
| -
|
| // Preserves object and value registers.
|
| void Assembler::StoreIntoObjectFilterNoSmi(Register object,
|
| Register value,
|
| @@ -1734,7 +1556,6 @@ void Assembler::StoreIntoObjectFilterNoSmi(Register object,
|
| b(no_update, EQ);
|
| }
|
|
|
| -
|
| // Preserves object and value registers.
|
| void Assembler::StoreIntoObjectFilter(Register object,
|
| Register value,
|
| @@ -1748,7 +1569,6 @@ void Assembler::StoreIntoObjectFilter(Register object,
|
| b(no_update, EQ);
|
| }
|
|
|
| -
|
| Register UseRegister(Register reg, RegList* used) {
|
| ASSERT(reg != THR);
|
| ASSERT(reg != SP);
|
| @@ -1759,7 +1579,6 @@ Register UseRegister(Register reg, RegList* used) {
|
| return reg;
|
| }
|
|
|
| -
|
| Register AllocateRegister(RegList* used) {
|
| const RegList free = ~*used;
|
| return (free == 0)
|
| @@ -1769,7 +1588,6 @@ Register AllocateRegister(RegList* used) {
|
| used);
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObject(Register object,
|
| const Address& dest,
|
| Register value,
|
| @@ -1798,7 +1616,6 @@ void Assembler::StoreIntoObject(Register object,
|
| Bind(&done);
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObjectOffset(Register object,
|
| int32_t offset,
|
| Register value,
|
| @@ -1813,7 +1630,6 @@ void Assembler::StoreIntoObjectOffset(Register object,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObjectNoBarrier(Register object,
|
| const Address& dest,
|
| Register value) {
|
| @@ -1827,7 +1643,6 @@ void Assembler::StoreIntoObjectNoBarrier(Register object,
|
| // No store buffer update.
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObjectNoBarrier(Register object,
|
| const Address& dest,
|
| const Object& value) {
|
| @@ -1840,7 +1655,6 @@ void Assembler::StoreIntoObjectNoBarrier(Register object,
|
| str(IP, dest);
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
|
| int32_t offset,
|
| Register value) {
|
| @@ -1856,7 +1670,6 @@ void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
|
| int32_t offset,
|
| const Object& value) {
|
| @@ -1874,7 +1687,6 @@ void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::InitializeFieldsNoBarrier(Register object,
|
| Register begin,
|
| Register end,
|
| @@ -1898,7 +1710,6 @@ void Assembler::InitializeFieldsNoBarrier(Register object,
|
| // No store buffer update.
|
| }
|
|
|
| -
|
| void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
|
| Register base,
|
| intptr_t begin_offset,
|
| @@ -1925,7 +1736,6 @@ void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
|
| // No store buffer update.
|
| }
|
|
|
| -
|
| void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
|
| #if defined(DEBUG)
|
| Label done;
|
| @@ -1937,7 +1747,6 @@ void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
|
| str(value, dest);
|
| }
|
|
|
| -
|
| void Assembler::LoadClassId(Register result, Register object, Condition cond) {
|
| ASSERT(RawObject::kClassIdTagPos == 16);
|
| ASSERT(RawObject::kClassIdTagSize == 16);
|
| @@ -1946,7 +1755,6 @@ void Assembler::LoadClassId(Register result, Register object, Condition cond) {
|
| ldrh(result, FieldAddress(object, class_id_offset), cond);
|
| }
|
|
|
| -
|
| void Assembler::LoadClassById(Register result, Register class_id) {
|
| ASSERT(result != class_id);
|
| LoadIsolate(result);
|
| @@ -1956,14 +1764,12 @@ void Assembler::LoadClassById(Register result, Register class_id) {
|
| ldr(result, Address(result, class_id, LSL, 2));
|
| }
|
|
|
| -
|
| void Assembler::LoadClass(Register result, Register object, Register scratch) {
|
| ASSERT(scratch != result);
|
| LoadClassId(scratch, object);
|
| LoadClassById(result, scratch);
|
| }
|
|
|
| -
|
| void Assembler::CompareClassId(Register object,
|
| intptr_t class_id,
|
| Register scratch) {
|
| @@ -1971,26 +1777,22 @@ void Assembler::CompareClassId(Register object,
|
| CompareImmediate(scratch, class_id);
|
| }
|
|
|
| -
|
| void Assembler::LoadClassIdMayBeSmi(Register result, Register object) {
|
| tst(object, Operand(kSmiTagMask));
|
| LoadClassId(result, object, NE);
|
| LoadImmediate(result, kSmiCid, EQ);
|
| }
|
|
|
| -
|
| void Assembler::LoadTaggedClassIdMayBeSmi(Register result, Register object) {
|
| LoadClassIdMayBeSmi(result, object);
|
| SmiTag(result);
|
| }
|
|
|
| -
|
| static bool CanEncodeBranchOffset(int32_t offset) {
|
| ASSERT(Utils::IsAligned(offset, 4));
|
| return Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset);
|
| }
|
|
|
| -
|
| int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
|
| // The offset is off by 8 due to the way the ARM CPUs read PC.
|
| offset -= Instr::kPCReadOffset;
|
| @@ -2006,13 +1808,11 @@ int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
|
| return (inst & ~kBranchOffsetMask) | offset;
|
| }
|
|
|
| -
|
| int Assembler::DecodeBranchOffset(int32_t inst) {
|
| // Sign-extend, left-shift by 2, then add 8.
|
| return ((((inst & kBranchOffsetMask) << 8) >> 6) + Instr::kPCReadOffset);
|
| }
|
|
|
| -
|
| static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
|
| int32_t offset = 0;
|
| offset |= (movt & 0xf0000) << 12;
|
| @@ -2022,7 +1822,6 @@ static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
|
| return offset;
|
| }
|
|
|
| -
|
| static int32_t DecodeARMv6LoadImmediate(int32_t mov,
|
| int32_t or1,
|
| int32_t or2,
|
| @@ -2035,7 +1834,6 @@ static int32_t DecodeARMv6LoadImmediate(int32_t mov,
|
| return offset;
|
| }
|
|
|
| -
|
| class PatchFarBranch : public AssemblerFixup {
|
| public:
|
| PatchFarBranch() {}
|
| @@ -2087,7 +1885,6 @@ class PatchFarBranch : public AssemblerFixup {
|
| (or3 == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
|
| }
|
|
|
| -
|
| void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
|
| const int32_t movw = region.Load<int32_t>(position);
|
| const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
|
| @@ -2118,7 +1915,6 @@ class PatchFarBranch : public AssemblerFixup {
|
| virtual bool IsPointerOffset() const { return false; }
|
| };
|
|
|
| -
|
| void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
|
| buffer_.EmitFixup(new PatchFarBranch());
|
| LoadPatchableImmediate(IP, offset);
|
| @@ -2129,7 +1925,6 @@ void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
|
| if (label->IsBound()) {
|
| const int32_t dest = label->Position() - buffer_.Size();
|
| @@ -2151,7 +1946,6 @@ void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::BindARMv6(Label* label) {
|
| ASSERT(!label->IsBound());
|
| intptr_t bound_pc = buffer_.Size();
|
| @@ -2230,7 +2024,6 @@ void Assembler::BindARMv6(Label* label) {
|
| label->BindTo(bound_pc);
|
| }
|
|
|
| -
|
| void Assembler::BindARMv7(Label* label) {
|
| ASSERT(!label->IsBound());
|
| intptr_t bound_pc = buffer_.Size();
|
| @@ -2297,7 +2090,6 @@ void Assembler::BindARMv7(Label* label) {
|
| label->BindTo(bound_pc);
|
| }
|
|
|
| -
|
| void Assembler::Bind(Label* label) {
|
| const ARMVersion version = TargetCPUFeatures::arm_version();
|
| if ((version == ARMv5TE) || (version == ARMv6)) {
|
| @@ -2308,7 +2100,6 @@ void Assembler::Bind(Label* label) {
|
| }
|
| }
|
|
|
| -
|
| OperandSize Address::OperandSizeFor(intptr_t cid) {
|
| switch (cid) {
|
| case kArrayCid:
|
| @@ -2356,7 +2147,6 @@ OperandSize Address::OperandSizeFor(intptr_t cid) {
|
| }
|
| }
|
|
|
| -
|
| bool Address::CanHoldLoadOffset(OperandSize size,
|
| int32_t offset,
|
| int32_t* offset_mask) {
|
| @@ -2391,7 +2181,6 @@ bool Address::CanHoldLoadOffset(OperandSize size,
|
| }
|
| }
|
|
|
| -
|
| bool Address::CanHoldStoreOffset(OperandSize size,
|
| int32_t offset,
|
| int32_t* offset_mask) {
|
| @@ -2426,7 +2215,6 @@ bool Address::CanHoldStoreOffset(OperandSize size,
|
| }
|
| }
|
|
|
| -
|
| bool Address::CanHoldImmediateOffset(bool is_load,
|
| intptr_t cid,
|
| int64_t offset) {
|
| @@ -2438,34 +2226,28 @@ bool Address::CanHoldImmediateOffset(bool is_load,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::Push(Register rd, Condition cond) {
|
| str(rd, Address(SP, -kWordSize, Address::PreIndex), cond);
|
| }
|
|
|
| -
|
| void Assembler::Pop(Register rd, Condition cond) {
|
| ldr(rd, Address(SP, kWordSize, Address::PostIndex), cond);
|
| }
|
|
|
| -
|
| void Assembler::PushList(RegList regs, Condition cond) {
|
| stm(DB_W, SP, regs, cond);
|
| }
|
|
|
| -
|
| void Assembler::PopList(RegList regs, Condition cond) {
|
| ldm(IA_W, SP, regs, cond);
|
| }
|
|
|
| -
|
| void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
|
| if (rd != rm) {
|
| mov(rd, Operand(rm), cond);
|
| }
|
| }
|
|
|
| -
|
| void Assembler::Lsl(Register rd,
|
| Register rm,
|
| const Operand& shift_imm,
|
| @@ -2475,12 +2257,10 @@ void Assembler::Lsl(Register rd,
|
| mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
|
| }
|
|
|
| -
|
| void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
|
| mov(rd, Operand(rm, LSL, rs), cond);
|
| }
|
|
|
| -
|
| void Assembler::Lsr(Register rd,
|
| Register rm,
|
| const Operand& shift_imm,
|
| @@ -2494,12 +2274,10 @@ void Assembler::Lsr(Register rd,
|
| mov(rd, Operand(rm, LSR, shift), cond);
|
| }
|
|
|
| -
|
| void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
|
| mov(rd, Operand(rm, LSR, rs), cond);
|
| }
|
|
|
| -
|
| void Assembler::Asr(Register rd,
|
| Register rm,
|
| const Operand& shift_imm,
|
| @@ -2513,7 +2291,6 @@ void Assembler::Asr(Register rd,
|
| mov(rd, Operand(rm, ASR, shift), cond);
|
| }
|
|
|
| -
|
| void Assembler::Asrs(Register rd,
|
| Register rm,
|
| const Operand& shift_imm,
|
| @@ -2527,12 +2304,10 @@ void Assembler::Asrs(Register rd,
|
| movs(rd, Operand(rm, ASR, shift), cond);
|
| }
|
|
|
| -
|
| void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
|
| mov(rd, Operand(rm, ASR, rs), cond);
|
| }
|
|
|
| -
|
| void Assembler::Ror(Register rd,
|
| Register rm,
|
| const Operand& shift_imm,
|
| @@ -2542,22 +2317,18 @@ void Assembler::Ror(Register rd,
|
| mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond);
|
| }
|
|
|
| -
|
| void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
|
| mov(rd, Operand(rm, ROR, rs), cond);
|
| }
|
|
|
| -
|
| void Assembler::Rrx(Register rd, Register rm, Condition cond) {
|
| mov(rd, Operand(rm, ROR, 0), cond);
|
| }
|
|
|
| -
|
| void Assembler::SignFill(Register rd, Register rm, Condition cond) {
|
| Asr(rd, rm, Operand(31), cond);
|
| }
|
|
|
| -
|
| void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
|
| ASSERT(qm != QTMP);
|
| ASSERT(qd != QTMP);
|
| @@ -2571,7 +2342,6 @@ void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
|
| vmulqs(qd, qd, QTMP);
|
| }
|
|
|
| -
|
| void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
|
| ASSERT(qm != QTMP);
|
| ASSERT(qd != QTMP);
|
| @@ -2589,7 +2359,6 @@ void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
|
| vmulqs(qd, qd, QTMP);
|
| }
|
|
|
| -
|
| void Assembler::Vsqrtqs(QRegister qd, QRegister qm, QRegister temp) {
|
| ASSERT(temp != QTMP);
|
| ASSERT(qm != QTMP);
|
| @@ -2605,7 +2374,6 @@ void Assembler::Vsqrtqs(QRegister qd, QRegister qm, QRegister temp) {
|
| Vreciprocalqs(qd, qm);
|
| }
|
|
|
| -
|
| void Assembler::Vdivqs(QRegister qd, QRegister qn, QRegister qm) {
|
| ASSERT(qd != QTMP);
|
| ASSERT(qn != QTMP);
|
| @@ -2615,7 +2383,6 @@ void Assembler::Vdivqs(QRegister qd, QRegister qn, QRegister qm) {
|
| vmulqs(qd, qn, qd);
|
| }
|
|
|
| -
|
| void Assembler::Branch(const StubEntry& stub_entry,
|
| Patchability patchable,
|
| Register pp,
|
| @@ -2628,7 +2395,6 @@ void Assembler::Branch(const StubEntry& stub_entry,
|
| bx(IP, cond);
|
| }
|
|
|
| -
|
| void Assembler::BranchLink(const Code& target, Patchability patchable) {
|
| // Make sure that class CallPattern is able to patch the label referred
|
| // to by this code sequence.
|
| @@ -2641,26 +2407,22 @@ void Assembler::BranchLink(const Code& target, Patchability patchable) {
|
| blx(LR); // Use blx instruction so that the return branch prediction works.
|
| }
|
|
|
| -
|
| void Assembler::BranchLink(const StubEntry& stub_entry,
|
| Patchability patchable) {
|
| const Code& code = Code::ZoneHandle(stub_entry.code());
|
| BranchLink(code, patchable);
|
| }
|
|
|
| -
|
| void Assembler::BranchLinkPatchable(const Code& target) {
|
| BranchLink(target, kPatchable);
|
| }
|
|
|
| -
|
| void Assembler::BranchLinkToRuntime() {
|
| ldr(IP, Address(THR, Thread::call_to_runtime_entry_point_offset()));
|
| ldr(CODE_REG, Address(THR, Thread::call_to_runtime_stub_offset()));
|
| blx(IP);
|
| }
|
|
|
| -
|
| void Assembler::BranchLinkWithEquivalence(const StubEntry& stub_entry,
|
| const Object& equivalence) {
|
| const Code& target = Code::ZoneHandle(stub_entry.code());
|
| @@ -2675,18 +2437,15 @@ void Assembler::BranchLinkWithEquivalence(const StubEntry& stub_entry,
|
| blx(LR); // Use blx instruction so that the return branch prediction works.
|
| }
|
|
|
| -
|
| void Assembler::BranchLink(const ExternalLabel* label) {
|
| LoadImmediate(LR, label->address()); // Target address is never patched.
|
| blx(LR); // Use blx instruction so that the return branch prediction works.
|
| }
|
|
|
| -
|
| void Assembler::BranchLinkPatchable(const StubEntry& stub_entry) {
|
| BranchLinkPatchable(Code::ZoneHandle(stub_entry.code()));
|
| }
|
|
|
| -
|
| void Assembler::BranchLinkOffset(Register base, int32_t offset) {
|
| ASSERT(base != PC);
|
| ASSERT(base != IP);
|
| @@ -2694,7 +2453,6 @@ void Assembler::BranchLinkOffset(Register base, int32_t offset) {
|
| blx(IP); // Use blx instruction so that the return branch prediction works.
|
| }
|
|
|
| -
|
| void Assembler::LoadPatchableImmediate(Register rd,
|
| int32_t value,
|
| Condition cond) {
|
| @@ -2718,7 +2476,6 @@ void Assembler::LoadPatchableImmediate(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadDecodableImmediate(Register rd,
|
| int32_t value,
|
| Condition cond) {
|
| @@ -2740,7 +2497,6 @@ void Assembler::LoadDecodableImmediate(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
|
| Operand o;
|
| if (Operand::CanHold(value, &o)) {
|
| @@ -2752,7 +2508,6 @@ void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
|
| if (!vmovs(sd, value, cond)) {
|
| const DRegister dd = static_cast<DRegister>(sd >> 1);
|
| @@ -2762,7 +2517,6 @@ void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadDImmediate(DRegister dd,
|
| double value,
|
| Register scratch,
|
| @@ -2779,7 +2533,6 @@ void Assembler::LoadDImmediate(DRegister dd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadFromOffset(OperandSize size,
|
| Register reg,
|
| Register base,
|
| @@ -2814,7 +2567,6 @@ void Assembler::LoadFromOffset(OperandSize size,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::StoreToOffset(OperandSize size,
|
| Register reg,
|
| Register base,
|
| @@ -2844,7 +2596,6 @@ void Assembler::StoreToOffset(OperandSize size,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadSFromOffset(SRegister reg,
|
| Register base,
|
| int32_t offset,
|
| @@ -2859,7 +2610,6 @@ void Assembler::LoadSFromOffset(SRegister reg,
|
| vldrs(reg, Address(base, offset), cond);
|
| }
|
|
|
| -
|
| void Assembler::StoreSToOffset(SRegister reg,
|
| Register base,
|
| int32_t offset,
|
| @@ -2874,7 +2624,6 @@ void Assembler::StoreSToOffset(SRegister reg,
|
| vstrs(reg, Address(base, offset), cond);
|
| }
|
|
|
| -
|
| void Assembler::LoadDFromOffset(DRegister reg,
|
| Register base,
|
| int32_t offset,
|
| @@ -2889,7 +2638,6 @@ void Assembler::LoadDFromOffset(DRegister reg,
|
| vldrd(reg, Address(base, offset), cond);
|
| }
|
|
|
| -
|
| void Assembler::StoreDToOffset(DRegister reg,
|
| Register base,
|
| int32_t offset,
|
| @@ -2904,7 +2652,6 @@ void Assembler::StoreDToOffset(DRegister reg,
|
| vstrd(reg, Address(base, offset), cond);
|
| }
|
|
|
| -
|
| void Assembler::LoadMultipleDFromOffset(DRegister first,
|
| intptr_t count,
|
| Register base,
|
| @@ -2914,7 +2661,6 @@ void Assembler::LoadMultipleDFromOffset(DRegister first,
|
| vldmd(IA, IP, first, count);
|
| }
|
|
|
| -
|
| void Assembler::StoreMultipleDToOffset(DRegister first,
|
| intptr_t count,
|
| Register base,
|
| @@ -2924,7 +2670,6 @@ void Assembler::StoreMultipleDToOffset(DRegister first,
|
| vstmd(IA, IP, first, count);
|
| }
|
|
|
| -
|
| void Assembler::CopyDoubleField(Register dst,
|
| Register src,
|
| Register tmp1,
|
| @@ -2943,7 +2688,6 @@ void Assembler::CopyDoubleField(Register dst,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::CopyFloat32x4Field(Register dst,
|
| Register src,
|
| Register tmp1,
|
| @@ -2979,7 +2723,6 @@ void Assembler::CopyFloat32x4Field(Register dst,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::CopyFloat64x2Field(Register dst,
|
| Register src,
|
| Register tmp1,
|
| @@ -3015,7 +2758,6 @@ void Assembler::CopyFloat64x2Field(Register dst,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::AddImmediate(Register rd,
|
| Register rn,
|
| int32_t value,
|
| @@ -3052,7 +2794,6 @@ void Assembler::AddImmediate(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::AddImmediateSetFlags(Register rd,
|
| Register rn,
|
| int32_t value,
|
| @@ -3080,7 +2821,6 @@ void Assembler::AddImmediateSetFlags(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::SubImmediateSetFlags(Register rd,
|
| Register rn,
|
| int32_t value,
|
| @@ -3108,7 +2848,6 @@ void Assembler::SubImmediateSetFlags(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::AndImmediate(Register rd,
|
| Register rs,
|
| int32_t imm,
|
| @@ -3122,7 +2861,6 @@ void Assembler::AndImmediate(Register rd,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
|
| Operand o;
|
| if (Operand::CanHold(value, &o)) {
|
| @@ -3134,7 +2872,6 @@ void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
|
| Operand o;
|
| if (Operand::CanHold(imm, &o)) {
|
| @@ -3167,7 +2904,6 @@ void Assembler::IntegerDivide(Register result,
|
| }
|
| }
|
|
|
| -
|
| static int NumRegsBelowFP(RegList regs) {
|
| int count = 0;
|
| for (int i = 0; i < FP; i++) {
|
| @@ -3178,7 +2914,6 @@ static int NumRegsBelowFP(RegList regs) {
|
| return count;
|
| }
|
|
|
| -
|
| void Assembler::EnterFrame(RegList regs, intptr_t frame_size) {
|
| if (prologue_offset_ == -1) {
|
| prologue_offset_ = CodeSize();
|
| @@ -3193,7 +2928,6 @@ void Assembler::EnterFrame(RegList regs, intptr_t frame_size) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LeaveFrame(RegList regs) {
|
| ASSERT((regs & (1 << PC)) == 0); // Must not pop PC.
|
| if ((regs & (1 << FP)) != 0) {
|
| @@ -3203,12 +2937,10 @@ void Assembler::LeaveFrame(RegList regs) {
|
| PopList(regs);
|
| }
|
|
|
| -
|
| void Assembler::Ret() {
|
| bx(LR);
|
| }
|
|
|
| -
|
| void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
|
| // Reserve space for arguments and align frame before entering
|
| // the C++ world.
|
| @@ -3218,7 +2950,6 @@ void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
|
| }
|
| }
|
|
|
| -
|
| void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
|
| Comment("EnterCallRuntimeFrame");
|
| // Preserve volatile CPU registers and PP.
|
| @@ -3243,7 +2974,6 @@ void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
|
| ReserveAlignedFrameSpace(frame_space);
|
| }
|
|
|
| -
|
| void Assembler::LeaveCallRuntimeFrame() {
|
| // SP might have been modified to reserve space for arguments
|
| // and ensure proper alignment of the stack frame.
|
| @@ -3278,13 +3008,11 @@ void Assembler::LeaveCallRuntimeFrame() {
|
| LeaveFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP));
|
| }
|
|
|
| -
|
| void Assembler::CallRuntime(const RuntimeEntry& entry,
|
| intptr_t argument_count) {
|
| entry.Call(this, argument_count);
|
| }
|
|
|
| -
|
| void Assembler::EnterDartFrame(intptr_t frame_size) {
|
| ASSERT(!constant_pool_allowed());
|
|
|
| @@ -3301,7 +3029,6 @@ void Assembler::EnterDartFrame(intptr_t frame_size) {
|
| AddImmediate(SP, -frame_size);
|
| }
|
|
|
| -
|
| // On entry to a function compiled for OSR, the caller's frame pointer, the
|
| // stack locals, and any copied parameters are already in place. The frame
|
| // pointer is already set up. The PC marker is not correct for the
|
| @@ -3316,7 +3043,6 @@ void Assembler::EnterOsrFrame(intptr_t extra_size) {
|
| AddImmediate(SP, -extra_size);
|
| }
|
|
|
| -
|
| void Assembler::LeaveDartFrame(RestorePP restore_pp) {
|
| if (restore_pp == kRestoreCallerPP) {
|
| ldr(PP, Address(FP, kSavedCallerPpSlotFromFp * kWordSize));
|
| @@ -3328,17 +3054,14 @@ void Assembler::LeaveDartFrame(RestorePP restore_pp) {
|
| LeaveFrame((1 << FP) | (1 << LR));
|
| }
|
|
|
| -
|
| void Assembler::EnterStubFrame() {
|
| EnterDartFrame(0);
|
| }
|
|
|
| -
|
| void Assembler::LeaveStubFrame() {
|
| LeaveDartFrame();
|
| }
|
|
|
| -
|
| // R0 receiver, R9 guarded cid as Smi
|
| void Assembler::MonomorphicCheckedEntry() {
|
| ASSERT(has_single_entry_point_);
|
| @@ -3368,7 +3091,6 @@ void Assembler::MonomorphicCheckedEntry() {
|
| #endif
|
| }
|
|
|
| -
|
| #ifndef PRODUCT
|
| void Assembler::MaybeTraceAllocation(intptr_t cid,
|
| Register temp_reg,
|
| @@ -3380,7 +3102,6 @@ void Assembler::MaybeTraceAllocation(intptr_t cid,
|
| b(trace, NE);
|
| }
|
|
|
| -
|
| void Assembler::LoadAllocationStatsAddress(Register dest, intptr_t cid) {
|
| ASSERT(dest != kNoRegister);
|
| ASSERT(dest != TMP);
|
| @@ -3393,7 +3114,6 @@ void Assembler::LoadAllocationStatsAddress(Register dest, intptr_t cid) {
|
| AddImmediate(dest, class_offset);
|
| }
|
|
|
| -
|
| void Assembler::IncrementAllocationStats(Register stats_addr_reg,
|
| intptr_t cid,
|
| Heap::Space space) {
|
| @@ -3410,7 +3130,6 @@ void Assembler::IncrementAllocationStats(Register stats_addr_reg,
|
| str(TMP, count_address);
|
| }
|
|
|
| -
|
| void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
|
| Register size_reg,
|
| Heap::Space space) {
|
| @@ -3435,7 +3154,6 @@ void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
|
| }
|
| #endif // !PRODUCT
|
|
|
| -
|
| void Assembler::TryAllocate(const Class& cls,
|
| Label* failure,
|
| Register instance_reg,
|
| @@ -3484,7 +3202,6 @@ void Assembler::TryAllocate(const Class& cls,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::TryAllocateArray(intptr_t cid,
|
| intptr_t instance_size,
|
| Label* failure,
|
| @@ -3533,7 +3250,6 @@ void Assembler::TryAllocateArray(intptr_t cid,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::Stop(const char* message) {
|
| if (FLAG_print_stop_message) {
|
| PushList((1 << R0) | (1 << IP) | (1 << LR)); // Preserve R0, IP, LR.
|
| @@ -3552,7 +3268,6 @@ void Assembler::Stop(const char* message) {
|
| bkpt(Instr::kStopMessageCode);
|
| }
|
|
|
| -
|
| Address Assembler::ElementAddressForIntIndex(bool is_load,
|
| bool is_external,
|
| intptr_t cid,
|
| @@ -3575,7 +3290,6 @@ Address Assembler::ElementAddressForIntIndex(bool is_load,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadElementAddressForIntIndex(Register address,
|
| bool is_load,
|
| bool is_external,
|
| @@ -3591,7 +3305,6 @@ void Assembler::LoadElementAddressForIntIndex(Register address,
|
| AddImmediate(address, array, offset);
|
| }
|
|
|
| -
|
| Address Assembler::ElementAddressForRegIndex(bool is_load,
|
| bool is_external,
|
| intptr_t cid,
|
| @@ -3631,7 +3344,6 @@ Address Assembler::ElementAddressForRegIndex(bool is_load,
|
| return Address(base, offset);
|
| }
|
|
|
| -
|
| void Assembler::LoadElementAddressForRegIndex(Register address,
|
| bool is_load,
|
| bool is_external,
|
| @@ -3654,7 +3366,6 @@ void Assembler::LoadElementAddressForRegIndex(Register address,
|
| }
|
| }
|
|
|
| -
|
| void Assembler::LoadHalfWordUnaligned(Register dst,
|
| Register addr,
|
| Register tmp) {
|
| @@ -3664,7 +3375,6 @@ void Assembler::LoadHalfWordUnaligned(Register dst,
|
| orr(dst, dst, Operand(tmp, LSL, 8));
|
| }
|
|
|
| -
|
| void Assembler::LoadHalfWordUnsignedUnaligned(Register dst,
|
| Register addr,
|
| Register tmp) {
|
| @@ -3674,7 +3384,6 @@ void Assembler::LoadHalfWordUnsignedUnaligned(Register dst,
|
| orr(dst, dst, Operand(tmp, LSL, 8));
|
| }
|
|
|
| -
|
| void Assembler::StoreHalfWordUnaligned(Register src,
|
| Register addr,
|
| Register tmp) {
|
| @@ -3683,7 +3392,6 @@ void Assembler::StoreHalfWordUnaligned(Register src,
|
| strb(tmp, Address(addr, 1));
|
| }
|
|
|
| -
|
| void Assembler::LoadWordUnaligned(Register dst, Register addr, Register tmp) {
|
| ASSERT(dst != addr);
|
| ldrb(dst, Address(addr, 0));
|
| @@ -3695,7 +3403,6 @@ void Assembler::LoadWordUnaligned(Register dst, Register addr, Register tmp) {
|
| orr(dst, dst, Operand(tmp, LSL, 24));
|
| }
|
|
|
| -
|
| void Assembler::StoreWordUnaligned(Register src, Register addr, Register tmp) {
|
| strb(src, Address(addr, 0));
|
| Lsr(tmp, src, Operand(8));
|
| @@ -3706,19 +3413,16 @@ void Assembler::StoreWordUnaligned(Register src, Register addr, Register tmp) {
|
| strb(tmp, Address(addr, 3));
|
| }
|
|
|
| -
|
| static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
|
| "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
| "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
|
| };
|
|
|
| -
|
| const char* Assembler::RegisterName(Register reg) {
|
| ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
|
| return cpu_reg_names[reg];
|
| }
|
|
|
| -
|
| static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
|
| "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
|
| #if defined(VFPv3_D32)
|
| @@ -3726,7 +3430,6 @@ static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
|
| #endif
|
| };
|
|
|
| -
|
| const char* Assembler::FpuRegisterName(FpuRegister reg) {
|
| ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
|
| return fpu_reg_names[reg];
|
|
|
Chromium Code Reviews
Issue 2974233002:
VM: Re-format to use at most one newline between functions (Closed)
