VM: Re-format to use at most one newline between functions

runtime/vm/simulator_arm64.cc

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include <setjmp.h>  // NOLINT
 #include <stdlib.h>
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM64)
 
 // Only build the simulator if not compiling for real ARM hardware.
 #if defined(USING_SIMULATOR)
 
 #include "vm/simulator.h"
 
 #include "vm/assembler.h"
 #include "vm/constants_arm64.h"
 #include "vm/disassembler.h"
 #include "vm/lockers.h"
 #include "vm/native_arguments.h"
+#include "vm/os_thread.h"
 #include "vm/stack_frame.h"
-#include "vm/os_thread.h"
 
 namespace dart {
 
 DEFINE_FLAG(uint64_t,
             trace_sim_after,
             ULLONG_MAX,
             "Trace simulator execution after instruction count reached.");
 DEFINE_FLAG(uint64_t,
             stop_sim_at,
             ULLONG_MAX,
             "Instruction address or instruction count to stop simulator at.");
 
-
 // This macro provides a platform independent use of sscanf. The reason for
 // SScanF not being implemented in a platform independent way through
 // OS in the same way as SNPrint is that the Windows C Run-Time
 // Library does not provide vsscanf.
 #define SScanF sscanf  // NOLINT
 
-
 // SimulatorSetjmpBuffer are linked together, and the last created one
 // is referenced by the Simulator. When an exception is thrown, the exception
 // runtime looks at where to jump and finds the corresponding
 // SimulatorSetjmpBuffer based on the stack pointer of the exception handler.
 // The runtime then does a Longjmp on that buffer to return to the simulator.
 class SimulatorSetjmpBuffer {
  public:
   void Longjmp() {
     // "This" is now the last setjmp buffer.
     simulator_->set_last_setjmp_buffer(this);
@@ skipping 18 matching lines @@
 
  private:
   uword sp_;
   Simulator* simulator_;
   SimulatorSetjmpBuffer* link_;
   jmp_buf buffer_;
 
   friend class Simulator;
 };
 
-
 // The SimulatorDebugger class is used by the simulator while debugging
 // simulated ARM64 code.
 class SimulatorDebugger {
  public:
   explicit SimulatorDebugger(Simulator* sim);
   ~SimulatorDebugger();
 
   void Stop(Instr* instr, const char* message);
   void Debug();
   char* ReadLine(const char* prompt);
@@ skipping 20 matching lines @@
   // Set or delete a breakpoint. Returns true if successful.
   bool SetBreakpoint(Instr* breakpc);
   bool DeleteBreakpoint(Instr* breakpc);
 
   // Undo and redo all breakpoints. This is needed to bracket disassembly and
   // execution to skip past breakpoints when run from the debugger.
   void UndoBreakpoints();
   void RedoBreakpoints();
 };
 
-
 SimulatorDebugger::SimulatorDebugger(Simulator* sim) {
   sim_ = sim;
 }
 
-
 SimulatorDebugger::~SimulatorDebugger() {}
 
-
 void SimulatorDebugger::Stop(Instr* instr, const char* message) {
   OS::Print("Simulator hit %s\n", message);
   Debug();
 }
 
-
 static Register LookupCpuRegisterByName(const char* name) {
   static const char* kNames[] = {
       "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
       "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
       "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
       "r24", "r25", "r26", "r27", "r28", "r29", "r30",
 
       "ip0", "ip1", "pp",  "ctx", "fp",  "lr",  "sp",  "zr",
   };
   static const Register kRegisters[] = {
       R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7,  R8,  R9,  R10,
       R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
       R22, R23, R24, R25, R26, R27, R28, R29, R30,
 
       IP0, IP1, PP,  CTX, FP,  LR,  R31, ZR,
   };
   ASSERT(ARRAY_SIZE(kNames) == ARRAY_SIZE(kRegisters));
   for (unsigned i = 0; i < ARRAY_SIZE(kNames); i++) {
     if (strcmp(kNames[i], name) == 0) {
       return kRegisters[i];
     }
   }
   return kNoRegister;
 }
 
-
 static VRegister LookupVRegisterByName(const char* name) {
   int reg_nr = -1;
   bool ok = SScanF(name, "v%d", &reg_nr);
   if (ok && (0 <= reg_nr) && (reg_nr < kNumberOfVRegisters)) {
     return static_cast<VRegister>(reg_nr);
   }
   return kNoVRegister;
 }
 
-
 bool SimulatorDebugger::GetValue(char* desc, uint64_t* value) {
   Register reg = LookupCpuRegisterByName(desc);
   if (reg != kNoRegister) {
     if (reg == ZR) {
       *value = 0;
       return true;
     }
     *value = sim_->get_register(reg);
     return true;
   }
@@ skipping 11 matching lines @@
     *value = sim_->get_pc();
     return true;
   }
   bool retval = SScanF(desc, "0x%" Px64, value) == 1;
   if (!retval) {
     retval = SScanF(desc, "%" Px64, value) == 1;
   }
   return retval;
 }
 
-
 bool SimulatorDebugger::GetSValue(char* desc, uint32_t* value) {
   VRegister vreg = LookupVRegisterByName(desc);
   if (vreg != kNoVRegister) {
     *value = sim_->get_vregisters(vreg, 0);
     return true;
   }
   if (desc[0] == '*') {
     uint64_t addr;
     if (GetValue(desc + 1, &addr)) {
       if (Simulator::IsIllegalAddress(addr)) {
         return false;
       }
       *value = *(reinterpret_cast<uint32_t*>(addr));
       return true;
     }
   }
   return false;
 }
 
-
 bool SimulatorDebugger::GetDValue(char* desc, uint64_t* value) {
   VRegister vreg = LookupVRegisterByName(desc);
   if (vreg != kNoVRegister) {
     *value = sim_->get_vregisterd(vreg, 0);
     return true;
   }
   if (desc[0] == '*') {
     uint64_t addr;
     if (GetValue(desc + 1, &addr)) {
       if (Simulator::IsIllegalAddress(addr)) {
         return false;
       }
       *value = *(reinterpret_cast<uint64_t*>(addr));
       return true;
     }
   }
   return false;
 }
 
-
 bool SimulatorDebugger::GetQValue(char* desc, simd_value_t* value) {
   VRegister vreg = LookupVRegisterByName(desc);
   if (vreg != kNoVRegister) {
     sim_->get_vregister(vreg, value);
     return true;
   }
   if (desc[0] == '*') {
     uint64_t addr;
     if (GetValue(desc + 1, &addr)) {
       if (Simulator::IsIllegalAddress(addr)) {
         return false;
       }
       *value = *(reinterpret_cast<simd_value_t*>(addr));
       return true;
     }
   }
   return false;
 }
 
-
 TokenPosition SimulatorDebugger::GetApproximateTokenIndex(const Code& code,
                                                           uword pc) {
   TokenPosition token_pos = TokenPosition::kNoSource;
   uword pc_offset = pc - code.PayloadStart();
   const PcDescriptors& descriptors =
       PcDescriptors::Handle(code.pc_descriptors());
   PcDescriptors::Iterator iter(descriptors, RawPcDescriptors::kAnyKind);
   while (iter.MoveNext()) {
     if (iter.PcOffset() == pc_offset) {
       return iter.TokenPos();
     } else if (!token_pos.IsReal() && (iter.PcOffset() > pc_offset)) {
       token_pos = iter.TokenPos();
     }
   }
   return token_pos;
 }
 
-
 void SimulatorDebugger::PrintDartFrame(uword pc,
                                        uword fp,
                                        uword sp,
                                        const Function& function,
                                        TokenPosition token_pos,
                                        bool is_optimized,
                                        bool is_inlined) {
   const Script& script = Script::Handle(function.script());
   const String& func_name = String::Handle(function.QualifiedScrubbedName());
   const String& url = String::Handle(script.url());
   intptr_t line = -1;
   intptr_t column = -1;
   if (token_pos.IsReal()) {
     script.GetTokenLocation(token_pos, &line, &column);
   }
   OS::Print(
       "pc=0x%" Px " fp=0x%" Px " sp=0x%" Px " %s%s (%s:%" Pd ":%" Pd ")\n", pc,
       fp, sp, is_optimized ? (is_inlined ? "inlined " : "optimized ") : "",
       func_name.ToCString(), url.ToCString(), line, column);
 }
 
-
 void SimulatorDebugger::PrintBacktrace() {
   StackFrameIterator frames(
       sim_->get_register(FP), sim_->get_register(SP), sim_->get_pc(),
       StackFrameIterator::kDontValidateFrames, Thread::Current(),
       StackFrameIterator::kNoCrossThreadIteration);
   StackFrame* frame = frames.NextFrame();
   ASSERT(frame != NULL);
   Function& function = Function::Handle();
   Function& inlined_function = Function::Handle();
   Code& code = Code::Handle();
@@ skipping 31 matching lines @@
                 frame->IsEntryFrame()
                     ? "entry"
                     : frame->IsExitFrame()
                           ? "exit"
                           : frame->IsStubFrame() ? "stub" : "invalid");
     }
     frame = frames.NextFrame();
   }
 }
 
-
 bool SimulatorDebugger::SetBreakpoint(Instr* breakpc) {
   // Check if a breakpoint can be set. If not return without any side-effects.
   if (sim_->break_pc_ != NULL) {
     return false;
   }
 
   // Set the breakpoint.
   sim_->break_pc_ = breakpc;
   sim_->break_instr_ = breakpc->InstructionBits();
   // Not setting the breakpoint instruction in the code itself. It will be set
   // when the debugger shell continues.
   return true;
 }
 
-
 bool SimulatorDebugger::DeleteBreakpoint(Instr* breakpc) {
   if (sim_->break_pc_ != NULL) {
     sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
   }
 
   sim_->break_pc_ = NULL;
   sim_->break_instr_ = 0;
   return true;
 }
 
-
 void SimulatorDebugger::UndoBreakpoints() {
   if (sim_->break_pc_ != NULL) {
     sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
   }
 }
 
-
 void SimulatorDebugger::RedoBreakpoints() {
   if (sim_->break_pc_ != NULL) {
     sim_->break_pc_->SetInstructionBits(Instr::kSimulatorBreakpointInstruction);
   }
 }
 
-
 void SimulatorDebugger::Debug() {
   intptr_t last_pc = -1;
   bool done = false;
 
 #define COMMAND_SIZE 63
 #define ARG_SIZE 255
 
 #define STR(a) #a
 #define XSTR(a) STR(a)
 
@@ skipping 254 matching lines @@
   // shell when hit.
   RedoBreakpoints();
 
 #undef COMMAND_SIZE
 #undef ARG_SIZE
 
 #undef STR
 #undef XSTR
 }
 
-
 char* SimulatorDebugger::ReadLine(const char* prompt) {
   char* result = NULL;
   char line_buf[256];
   intptr_t offset = 0;
   bool keep_going = true;
   OS::Print("%s", prompt);
   while (keep_going) {
     if (fgets(line_buf, sizeof(line_buf), stdin) == NULL) {
       // fgets got an error. Just give up.
       if (result != NULL) {
@@ skipping 38 matching lines @@
     }
     // Copy the newly read line into the result.
     memmove(result + offset, line_buf, len);
     offset += len;
   }
   ASSERT(result != NULL);
   result[offset] = '\0';
   return result;
 }
 
-
 // Synchronization primitives support.
 Mutex* Simulator::exclusive_access_lock_ = NULL;
 Simulator::AddressTag Simulator::exclusive_access_state_[kNumAddressTags] = {
     {NULL, 0}};
 int Simulator::next_address_tag_ = 0;
 
-
 void Simulator::InitOnce() {
   // Setup exclusive access state lock.
   exclusive_access_lock_ = new Mutex();
 }
 
-
 Simulator::Simulator() {
   // Setup simulator support first. Some of this information is needed to
   // setup the architecture state.
   // We allocate the stack here, the size is computed as the sum of
   // the size specified by the user and the buffer space needed for
   // handling stack overflow exceptions. To be safe in potential
   // stack underflows we also add some underflow buffer space.
   stack_ =
       new char[(OSThread::GetSpecifiedStackSize() + OSThread::kStackSizeBuffer +
                 kSimulatorStackUnderflowSize)];
@@ skipping 21 matching lines @@
 
   // The sp is initialized to point to the bottom (high address) of the
   // allocated stack area.
   registers_[R31] = StackTop();
   // The lr and pc are initialized to a known bad value that will cause an
   // access violation if the simulator ever tries to execute it.
   registers_[LR] = kBadLR;
   pc_ = kBadLR;
 }
 
-
 Simulator::~Simulator() {
   delete[] stack_;
   Isolate* isolate = Isolate::Current();
   if (isolate != NULL) {
     isolate->set_simulator(NULL);
   }
 }
 
-
 // When the generated code calls an external reference we need to catch that in
 // the simulator.  The external reference will be a function compiled for the
 // host architecture.  We need to call that function instead of trying to
 // execute it with the simulator.  We do that by redirecting the external
 // reference to a svc (supervisor call) instruction that is handled by
 // the simulator.  We write the original destination of the jump just at a known
 // offset from the svc instruction so the simulator knows what to call.
 class Redirection {
  public:
   uword address_of_hlt_instruction() {
@@ skipping 55 matching lines @@
   }
 
   uword external_function_;
   Simulator::CallKind call_kind_;
   int argument_count_;
   uint32_t hlt_instruction_;
   Redirection* next_;
   static Redirection* list_;
 };
 
-
 Redirection* Redirection::list_ = NULL;
 
-
 uword Simulator::RedirectExternalReference(uword function,
                                            CallKind call_kind,
                                            int argument_count) {
   Redirection* redirection =
       Redirection::Get(function, call_kind, argument_count);
   return redirection->address_of_hlt_instruction();
 }
 
-
 uword Simulator::FunctionForRedirect(uword redirect) {
   return Redirection::FunctionForRedirect(redirect);
 }
 
-
 // Get the active Simulator for the current isolate.
 Simulator* Simulator::Current() {
   Simulator* simulator = Isolate::Current()->simulator();
   if (simulator == NULL) {
     simulator = new Simulator();
     Isolate::Current()->set_simulator(simulator);
   }
   return simulator;
 }
 
-
 // Sets the register in the architecture state.
 void Simulator::set_register(Instr* instr,
                              Register reg,
                              int64_t value,
                              R31Type r31t) {
   // Register is in range.
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   ASSERT(instr == NULL || reg != R18);  // R18 is globally reserved on iOS.
   if ((reg != R31) || (r31t != R31IsZR)) {
     registers_[reg] = value;
     // If we're setting CSP, make sure it is 16-byte aligned. In truth, CSP
     // can store addresses that are not 16-byte aligned, but loads and stores
     // are not allowed through CSP when it is not aligned. Thus, this check is
     // more conservative that necessary. However, it will likely be more
     // useful to find the program locations where CSP is set to a bad value,
     // than to find only the resulting loads/stores that would cause a fault on
     // hardware.
     if ((instr != NULL) && (reg == R31) && !Utils::IsAligned(value, 16)) {
       UnalignedAccess("CSP set", value, instr);
     }
   }
 }
 
-
 // Get the register from the architecture state.
 int64_t Simulator::get_register(Register reg, R31Type r31t) const {
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   if ((reg == R31) && (r31t == R31IsZR)) {
     return 0;
   } else {
     return registers_[reg];
   }
 }
 
-
 void Simulator::set_wregister(Register reg, int32_t value, R31Type r31t) {
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   // When setting in W mode, clear the high bits.
   if ((reg != R31) || (r31t != R31IsZR)) {
     registers_[reg] = Utils::LowHighTo64Bits(static_cast<uint32_t>(value), 0);
   }
 }
 
-
 // Get the register from the architecture state.
 int32_t Simulator::get_wregister(Register reg, R31Type r31t) const {
   ASSERT((reg >= 0) && (reg < kNumberOfCpuRegisters));
   if ((reg == R31) && (r31t == R31IsZR)) {
     return 0;
   } else {
     return static_cast<int32_t>(registers_[reg]);
   }
 }
 
-
 int32_t Simulator::get_vregisters(VRegister reg, int idx) const {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   ASSERT((idx >= 0) && (idx <= 3));
   return vregisters_[reg].bits.i32[idx];
 }
 
-
 void Simulator::set_vregisters(VRegister reg, int idx, int32_t value) {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   ASSERT((idx >= 0) && (idx <= 3));
   vregisters_[reg].bits.i32[idx] = value;
 }
 
-
 int64_t Simulator::get_vregisterd(VRegister reg, int idx) const {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   ASSERT((idx == 0) || (idx == 1));
   return vregisters_[reg].bits.i64[idx];
 }
 
-
 void Simulator::set_vregisterd(VRegister reg, int idx, int64_t value) {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   ASSERT((idx == 0) || (idx == 1));
   vregisters_[reg].bits.i64[idx] = value;
 }
 
-
 void Simulator::get_vregister(VRegister reg, simd_value_t* value) const {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   value->bits.i64[0] = vregisters_[reg].bits.i64[0];
   value->bits.i64[1] = vregisters_[reg].bits.i64[1];
 }
 
-
 void Simulator::set_vregister(VRegister reg, const simd_value_t& value) {
   ASSERT((reg >= 0) && (reg < kNumberOfVRegisters));
   vregisters_[reg].bits.i64[0] = value.bits.i64[0];
   vregisters_[reg].bits.i64[1] = value.bits.i64[1];
 }
 
-
 // Raw access to the PC register.
 void Simulator::set_pc(int64_t value) {
   pc_modified_ = true;
   last_pc_ = pc_;
   pc_ = value;
 }
 
-
 // Raw access to the pc.
 int64_t Simulator::get_pc() const {
   return pc_;
 }
 
-
 int64_t Simulator::get_last_pc() const {
   return last_pc_;
 }
 
-
 void Simulator::HandleIllegalAccess(uword addr, Instr* instr) {
   uword fault_pc = get_pc();
   uword last_pc = get_last_pc();
   char buffer[128];
-  snprintf(buffer, sizeof(buffer), "illegal memory access at 0x%" Px
-                                   ", pc=0x%" Px ", last_pc=0x%" Px "\n",
+  snprintf(buffer, sizeof(buffer),
+           "illegal memory access at 0x%" Px ", pc=0x%" Px ", last_pc=0x%" Px
+           "\n",
            addr, fault_pc, last_pc);
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   // The debugger will return control in non-interactive mode.
   FATAL("Cannot continue execution after illegal memory access.");
 }
 
-
 // The ARMv8 manual advises that an unaligned access may generate a fault,
 // and if not, will likely take a number of additional cycles to execute,
 // so let's just not generate any.
 void Simulator::UnalignedAccess(const char* msg, uword addr, Instr* instr) {
   char buffer[128];
   snprintf(buffer, sizeof(buffer), "unaligned %s at 0x%" Px ", pc=%p\n", msg,
            addr, instr);
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   // The debugger will not be able to single step past this instruction, but
   // it will be possible to disassemble the code and inspect registers.
   FATAL("Cannot continue execution after unaligned access.");
 }
 
-
 void Simulator::UnimplementedInstruction(Instr* instr) {
   char buffer[128];
   snprintf(buffer, sizeof(buffer),
            "Unimplemented instruction: at %p, last_pc=0x%" Px64 "\n", instr,
            get_last_pc());
   SimulatorDebugger dbg(this);
   dbg.Stop(instr, buffer);
   FATAL("Cannot continue execution after unimplemented instruction.");
 }
 
-
 // Returns the top of the stack area to enable checking for stack pointer
 // validity.
 uword Simulator::StackTop() const {
   // To be safe in potential stack underflows we leave some buffer above and
   // set the stack top.
   return StackBase() +
          (OSThread::GetSpecifiedStackSize() + OSThread::kStackSizeBuffer);
 }
 
-
 bool Simulator::IsTracingExecution() const {
   return icount_ > FLAG_trace_sim_after;
 }
 
-
 intptr_t Simulator::ReadX(uword addr, Instr* instr) {
   if ((addr & 7) == 0) {
     intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("read", addr, instr);
   return 0;
 }
 
-
 void Simulator::WriteX(uword addr, intptr_t value, Instr* instr) {
   if ((addr & 7) == 0) {
     intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
     *ptr = value;
     return;
   }
   UnalignedAccess("write", addr, instr);
 }
 
-
 uint32_t Simulator::ReadWU(uword addr, Instr* instr) {
   if ((addr & 3) == 0) {
     uint32_t* ptr = reinterpret_cast<uint32_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("read unsigned single word", addr, instr);
   return 0;
 }
 
-
 int32_t Simulator::ReadW(uword addr, Instr* instr) {
   if ((addr & 3) == 0) {
     int32_t* ptr = reinterpret_cast<int32_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("read single word", addr, instr);
   return 0;
 }
 
-
 void Simulator::WriteW(uword addr, uint32_t value, Instr* instr) {
   if ((addr & 3) == 0) {
     uint32_t* ptr = reinterpret_cast<uint32_t*>(addr);
     *ptr = value;
     return;
   }
   UnalignedAccess("write single word", addr, instr);
 }
 
-
 uint16_t Simulator::ReadHU(uword addr, Instr* instr) {
   if ((addr & 1) == 0) {
     uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("unsigned halfword read", addr, instr);
   return 0;
 }
 
-
 int16_t Simulator::ReadH(uword addr, Instr* instr) {
   if ((addr & 1) == 0) {
     int16_t* ptr = reinterpret_cast<int16_t*>(addr);
     return *ptr;
   }
   UnalignedAccess("signed halfword read", addr, instr);
   return 0;
 }
 
-
 void Simulator::WriteH(uword addr, uint16_t value, Instr* instr) {
   if ((addr & 1) == 0) {
     uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
     *ptr = value;
     return;
   }
   UnalignedAccess("halfword write", addr, instr);
 }
 
-
 uint8_t Simulator::ReadBU(uword addr) {
   uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
   return *ptr;
 }
 
-
 int8_t Simulator::ReadB(uword addr) {
   int8_t* ptr = reinterpret_cast<int8_t*>(addr);
   return *ptr;
 }
 
-
 void Simulator::WriteB(uword addr, uint8_t value) {
   uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
   *ptr = value;
 }
 
-
 // Synchronization primitives support.
 void Simulator::SetExclusiveAccess(uword addr) {
   Thread* thread = Thread::Current();
   ASSERT(thread != NULL);
   DEBUG_ASSERT(exclusive_access_lock_->IsOwnedByCurrentThread());
   int i = 0;
   // Find an entry for this thread in the exclusive access state.
   while ((i < kNumAddressTags) &&
          (exclusive_access_state_[i].thread != thread)) {
     i++;
   }
   // Round-robin replacement of previously used entries.
   if (i == kNumAddressTags) {
     i = next_address_tag_;
     if (++next_address_tag_ == kNumAddressTags) {
       next_address_tag_ = 0;
     }
     exclusive_access_state_[i].thread = thread;
   }
   // Remember the address being reserved.
   exclusive_access_state_[i].addr = addr;
 }
 
-
 bool Simulator::HasExclusiveAccessAndOpen(uword addr) {
   Thread* thread = Thread::Current();
   ASSERT(thread != NULL);
   ASSERT(addr != 0);
   DEBUG_ASSERT(exclusive_access_lock_->IsOwnedByCurrentThread());
   bool result = false;
   for (int i = 0; i < kNumAddressTags; i++) {
     if (exclusive_access_state_[i].thread == thread) {
       // Check whether the current threads address reservation matches.
       if (exclusive_access_state_[i].addr == addr) {
         result = true;
       }
       exclusive_access_state_[i].addr = 0;
     } else if (exclusive_access_state_[i].addr == addr) {
       // Other threads with matching address lose their reservations.
       exclusive_access_state_[i].addr = 0;
     }
   }
   return result;
 }
 
-
 void Simulator::ClearExclusive() {
   MutexLocker ml(exclusive_access_lock_);
   // Remove the reservation for this thread.
   SetExclusiveAccess(0);
 }
 
-
 intptr_t Simulator::ReadExclusiveX(uword addr, Instr* instr) {
   MutexLocker ml(exclusive_access_lock_);
   SetExclusiveAccess(addr);
   return ReadX(addr, instr);
 }
 
-
 intptr_t Simulator::ReadExclusiveW(uword addr, Instr* instr) {
   MutexLocker ml(exclusive_access_lock_);
   SetExclusiveAccess(addr);
   return ReadWU(addr, instr);
 }
 
-
 intptr_t Simulator::WriteExclusiveX(uword addr, intptr_t value, Instr* instr) {
   MutexLocker ml(exclusive_access_lock_);
   bool write_allowed = HasExclusiveAccessAndOpen(addr);
   if (write_allowed) {
     WriteX(addr, value, instr);
     return 0;  // Success.
   }
   return 1;  // Failure.
 }
 
-
 intptr_t Simulator::WriteExclusiveW(uword addr, intptr_t value, Instr* instr) {
   MutexLocker ml(exclusive_access_lock_);
   bool write_allowed = HasExclusiveAccessAndOpen(addr);
   if (write_allowed) {
     WriteW(addr, value, instr);
     return 0;  // Success.
   }
   return 1;  // Failure.
 }
 
-
 uword Simulator::CompareExchange(uword* address,
                                  uword compare_value,
                                  uword new_value) {
   MutexLocker ml(exclusive_access_lock_);
   // We do not get a reservation as it would be guaranteed to be found when
   // writing below. No other thread is able to make a reservation while we
   // hold the lock.
   uword value = *address;
   if (value == compare_value) {
     *address = new_value;
     // Same effect on exclusive access state as a successful STREX.
     HasExclusiveAccessAndOpen(reinterpret_cast<uword>(address));
   } else {
     // Same effect on exclusive access state as an LDREX.
     SetExclusiveAccess(reinterpret_cast<uword>(address));
   }
   return value;
 }
 
-
 uint32_t Simulator::CompareExchangeUint32(uint32_t* address,
                                           uint32_t compare_value,
                                           uint32_t new_value) {
   MutexLocker ml(exclusive_access_lock_);
   // We do not get a reservation as it would be guaranteed to be found when
   // writing below. No other thread is able to make a reservation while we
   // hold the lock.
   uint32_t value = *address;
   if (value == compare_value) {
     *address = new_value;
     // Same effect on exclusive access state as a successful STREX.
     HasExclusiveAccessAndOpen(reinterpret_cast<uword>(address));
   } else {
     // Same effect on exclusive access state as an LDREX.
     SetExclusiveAccess(reinterpret_cast<uword>(address));
   }
   return value;
 }
 
-
 // Unsupported instructions use Format to print an error and stop execution.
 void Simulator::Format(Instr* instr, const char* format) {
   OS::Print("Simulator found unsupported instruction:\n 0x%p: %s\n", instr,
             format);
   UNIMPLEMENTED();
 }
 
-
 // Calculate and set the Negative and Zero flags.
 void Simulator::SetNZFlagsW(int32_t val) {
   n_flag_ = (val < 0);
   z_flag_ = (val == 0);
 }
 
-
 // Calculate C flag value for additions (and subtractions with adjusted args).
 bool Simulator::CarryFromW(int32_t left, int32_t right, int32_t carry) {
   uint64_t uleft = static_cast<uint32_t>(left);
   uint64_t uright = static_cast<uint32_t>(right);
   uint64_t ucarry = static_cast<uint32_t>(carry);
   return ((uleft + uright + ucarry) >> 32) != 0;
 }
 
-
 // Calculate V flag value for additions (and subtractions with adjusted args).
 bool Simulator::OverflowFromW(int32_t left, int32_t right, int32_t carry) {
   int64_t result = static_cast<int64_t>(left) + right + carry;
   return (result >> 31) != (result >> 32);
 }
 
-
 // Calculate and set the Negative and Zero flags.
 void Simulator::SetNZFlagsX(int64_t val) {
   n_flag_ = (val < 0);
   z_flag_ = (val == 0);
 }
 
-
 // Calculate C flag value for additions and subtractions.
 bool Simulator::CarryFromX(int64_t alu_out,
                            int64_t left,
                            int64_t right,
                            bool addition) {
   if (addition) {
     return (((left & right) | ((left | right) & ~alu_out)) >> 63) != 0;
   } else {
     return (((~left & right) | ((~left | right) & alu_out)) >> 63) == 0;
   }
 }
 
-
 // Calculate V flag value for additions and subtractions.
 bool Simulator::OverflowFromX(int64_t alu_out,
                               int64_t left,
                               int64_t right,
                               bool addition) {
   if (addition) {
     return (((alu_out ^ left) & (alu_out ^ right)) >> 63) != 0;
   } else {
     return (((left ^ right) & (alu_out ^ left)) >> 63) != 0;
   }
 }
 
-
 // Set the Carry flag.
 void Simulator::SetCFlag(bool val) {
   c_flag_ = val;
 }
 
-
 // Set the oVerflow flag.
 void Simulator::SetVFlag(bool val) {
   v_flag_ = val;
 }
 
-
 void Simulator::DecodeMoveWide(Instr* instr) {
   const Register rd = instr->RdField();
   const int hw = instr->HWField();
   const int64_t shift = hw << 4;
   const int64_t shifted_imm = static_cast<int64_t>(instr->Imm16Field())
                               << shift;
 
   if (instr->SFField()) {
     if (instr->Bits(29, 2) == 0) {
       // Format(instr, "movn'sf 'rd, 'imm16 'hw");
@@ skipping 23 matching lines @@
       set_wregister(rd, result, instr->RdMode());
     } else {
       UnimplementedInstruction(instr);
     }
   } else {
     // Dest is 32 bits, but shift is more than 32.
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeAddSubImm(Instr* instr) {
   const bool addition = (instr->Bit(30) == 0);
   // Format(instr, "addi'sf's 'rd, 'rn, 'imm12s");
   // Format(instr, "subi'sf's 'rd, 'rn, 'imm12s");
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   uint32_t imm = (instr->Bit(22) == 1) ? (instr->Imm12Field() << 12)
                                        : (instr->Imm12Field());
   if (instr->SFField()) {
     // 64-bit add.
@@ skipping 16 matching lines @@
     const int32_t alu_out = rn_val + imm + carry_in;
     set_wregister(rd, alu_out, instr->RdMode());
     if (instr->HasS()) {
       SetNZFlagsW(alu_out);
       SetCFlag(CarryFromW(rn_val, imm, carry_in));
       SetVFlag(OverflowFromW(rn_val, imm, carry_in));
     }
   }
 }
 
-
 void Simulator::DecodeLogicalImm(Instr* instr) {
   const int op = instr->Bits(29, 2);
   const bool set_flags = op == 3;
   const int out_size = ((instr->SFField() == 0) && (instr->NField() == 0))
                            ? kWRegSizeInBits
                            : kXRegSizeInBits;
   const Register rn = instr->RnField();
   const Register rd = instr->RdField();
   const int64_t rn_val = get_register(rn, instr->RnMode());
   const uint64_t imm = instr->ImmLogical();
@@ skipping 30 matching lines @@
     SetVFlag(false);
   }
 
   if (out_size == kXRegSizeInBits) {
     set_register(instr, rd, alu_out, instr->RdMode());
   } else {
     set_wregister(rd, alu_out, instr->RdMode());
   }
 }
 
-
 void Simulator::DecodePCRel(Instr* instr) {
   const int op = instr->Bit(31);
   if (op == 0) {
     // Format(instr, "adr 'rd, 'pcrel")
     const Register rd = instr->RdField();
     const int64_t immhi = instr->SImm19Field();
     const int64_t immlo = instr->Bits(29, 2);
     const int64_t off = (immhi << 2) | immlo;
     const int64_t dest = get_pc() + off;
     set_register(instr, rd, dest, instr->RdMode());
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeDPImmediate(Instr* instr) {
   if (instr->IsMoveWideOp()) {
     DecodeMoveWide(instr);
   } else if (instr->IsAddSubImmOp()) {
     DecodeAddSubImm(instr);
   } else if (instr->IsLogicalImmOp()) {
     DecodeLogicalImm(instr);
   } else if (instr->IsPCRelOp()) {
     DecodePCRel(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeCompareAndBranch(Instr* instr) {
   const int op = instr->Bit(24);
   const Register rt = instr->RtField();
   const int64_t imm19 = instr->SImm19Field();
   const int64_t dest = get_pc() + (imm19 << 2);
   const int64_t mask = instr->SFField() == 1 ? kXRegMask : kWRegMask;
   const int64_t rt_val = get_register(rt, R31IsZR) & mask;
   if (op == 0) {
     // Format(instr, "cbz'sf 'rt, 'dest19");
     if (rt_val == 0) {
       set_pc(dest);
     }
   } else {
     // Format(instr, "cbnz'sf 'rt, 'dest19");
     if (rt_val != 0) {
       set_pc(dest);
     }
   }
 }
 
-
 bool Simulator::ConditionallyExecute(Instr* instr) {
   Condition cond;
   if (instr->IsConditionalSelectOp()) {
     cond = instr->SelectConditionField();
   } else {
     cond = instr->ConditionField();
   }
   switch (cond) {
     case EQ:
       return z_flag_;
@@ skipping 24 matching lines @@
     case LE:
       return z_flag_ || (n_flag_ != v_flag_);
     case AL:
       return true;
     default:
       UNREACHABLE();
   }
   return false;
 }
 
-
 void Simulator::DecodeConditionalBranch(Instr* instr) {
   // Format(instr, "b'cond 'dest19");
   if ((instr->Bit(24) != 0) || (instr->Bit(4) != 0)) {
     UnimplementedInstruction(instr);
   }
   const int64_t imm19 = instr->SImm19Field();
   const int64_t dest = get_pc() + (imm19 << 2);
   if (ConditionallyExecute(instr)) {
     set_pc(dest);
   }
 }
 
-
 // Calls into the Dart runtime are based on this interface.
 typedef void (*SimulatorRuntimeCall)(NativeArguments arguments);
 
 // Calls to leaf Dart runtime functions are based on this interface.
 typedef int64_t (*SimulatorLeafRuntimeCall)(int64_t r0,
                                             int64_t r1,
                                             int64_t r2,
                                             int64_t r3,
                                             int64_t r4,
                                             int64_t r5,
                                             int64_t r6,
                                             int64_t r7);
 
 // Calls to leaf float Dart runtime functions are based on this interface.
 typedef double (*SimulatorLeafFloatRuntimeCall)(double d0,
                                                 double d1,
                                                 double d2,
                                                 double d3,
                                                 double d4,
                                                 double d5,
                                                 double d6,
                                                 double d7);
 
 // Calls to native Dart functions are based on this interface.
 typedef void (*SimulatorBootstrapNativeCall)(NativeArguments* arguments);
 typedef void (*SimulatorNativeCall)(NativeArguments* arguments, uword target);
 
-
 void Simulator::DoRedirectedCall(Instr* instr) {
   SimulatorSetjmpBuffer buffer(this);
   if (!setjmp(buffer.buffer_)) {
     int64_t saved_lr = get_register(LR);
     Redirection* redirection = Redirection::FromHltInstruction(instr);
     uword external = redirection->external_function();
     if (IsTracingExecution()) {
       THR_Print("Call to host function at 0x%" Pd "\n", external);
     }
 
@@ skipping 91 matching lines @@
     // TODO(zra): Zap caller-saved fpu registers.
 
     // Return.
     set_pc(saved_lr);
   } else {
     // Coming via long jump from a throw. Continue to exception handler.
     set_top_exit_frame_info(0);
   }
 }
 
-
 void Simulator::DecodeExceptionGen(Instr* instr) {
   if ((instr->Bits(0, 2) == 1) && (instr->Bits(2, 3) == 0) &&
       (instr->Bits(21, 3) == 0)) {
     // Format(instr, "svc 'imm16");
     UnimplementedInstruction(instr);
   } else if ((instr->Bits(0, 2) == 0) && (instr->Bits(2, 3) == 0) &&
              (instr->Bits(21, 3) == 1)) {
     // Format(instr, "brk 'imm16");
     SimulatorDebugger dbg(this);
     int32_t imm = instr->Imm16Field();
@@ skipping 18 matching lines @@
     } else if (imm == Instr::kSimulatorRedirectCode) {
       DoRedirectedCall(instr);
     } else {
       UnimplementedInstruction(instr);
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeSystem(Instr* instr) {
   if (instr->InstructionBits() == CLREX) {
     // Format(instr, "clrex");
     ClearExclusive();
     return;
   }
 
   if ((instr->Bits(0, 8) == 0x1f) && (instr->Bits(12, 4) == 2) &&
       (instr->Bits(16, 3) == 3) && (instr->Bits(19, 2) == 0) &&
       (instr->Bit(21) == 0)) {
     if (instr->Bits(8, 4) == 0) {
       // Format(instr, "nop");
     } else {
       UnimplementedInstruction(instr);
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeTestAndBranch(Instr* instr) {
   const int op = instr->Bit(24);
   const int bitpos = instr->Bits(19, 4) | (instr->Bit(31) << 5);
   const int64_t imm14 = instr->SImm14Field();
   const int64_t dest = get_pc() + (imm14 << 2);
   const Register rt = instr->RtField();
   const int64_t rt_val = get_register(rt, R31IsZR);
   if (op == 0) {
     // Format(instr, "tbz'sf 'rt, 'bitpos, 'dest14");
     if ((rt_val & (1 << bitpos)) == 0) {
       set_pc(dest);
     }
   } else {
     // Format(instr, "tbnz'sf 'rt, 'bitpos, 'dest14");
     if ((rt_val & (1 << bitpos)) != 0) {
       set_pc(dest);
     }
   }
 }
 
-
 void Simulator::DecodeUnconditionalBranch(Instr* instr) {
   const bool link = instr->Bit(31) == 1;
   const int64_t imm26 = instr->SImm26Field();
   const int64_t dest = get_pc() + (imm26 << 2);
   const int64_t ret = get_pc() + Instr::kInstrSize;
   set_pc(dest);
   if (link) {
     set_register(instr, LR, ret);
   }
 }
 
-
 void Simulator::DecodeUnconditionalBranchReg(Instr* instr) {
   if ((instr->Bits(0, 5) == 0) && (instr->Bits(10, 6) == 0) &&
       (instr->Bits(16, 5) == 0x1f)) {
     switch (instr->Bits(21, 4)) {
       case 0: {
         // Format(instr, "br 'rn");
         const Register rn = instr->RnField();
         const int64_t dest = get_register(rn, instr->RnMode());
         set_pc(dest);
         break;
@@ skipping 16 matching lines @@
       }
       default:
         UnimplementedInstruction(instr);
         break;
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeCompareBranch(Instr* instr) {
   if (instr->IsCompareAndBranchOp()) {
     DecodeCompareAndBranch(instr);
   } else if (instr->IsConditionalBranchOp()) {
     DecodeConditionalBranch(instr);
   } else if (instr->IsExceptionGenOp()) {
     DecodeExceptionGen(instr);
   } else if (instr->IsSystemOp()) {
     DecodeSystem(instr);
   } else if (instr->IsTestAndBranchOp()) {
     DecodeTestAndBranch(instr);
   } else if (instr->IsUnconditionalBranchOp()) {
     DecodeUnconditionalBranch(instr);
   } else if (instr->IsUnconditionalBranchRegOp()) {
     DecodeUnconditionalBranchReg(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeLoadStoreReg(Instr* instr) {
   // Calculate the address.
   const Register rn = instr->RnField();
   const Register rt = instr->RtField();
   const VRegister vt = instr->VtField();
   const int64_t rn_val = get_register(rn, R31IsSP);
   const uint32_t size = (instr->Bit(26) == 1)
                             ? ((instr->Bit(23) << 2) | instr->SzField())
                             : instr->SzField();
   uword address = 0;
@@ skipping 173 matching lines @@
       }
     }
   }
 
   // Do writeback.
   if (wb) {
     set_register(instr, rn, wb_address, R31IsSP);
   }
 }
 
-
 void Simulator::DecodeLoadStoreRegPair(Instr* instr) {
   const int32_t opc = instr->Bits(23, 3);
   const Register rn = instr->RnField();
   const Register rt = instr->RtField();
   const Register rt2 = instr->Rt2Field();
   const int64_t rn_val = get_register(rn, R31IsSP);
   const intptr_t shift = 2 + instr->SFField();
   const intptr_t size = 1 << shift;
   const int32_t offset = (instr->SImm7Field() << shift);
   uword address = 0;
@@ skipping 73 matching lines @@
       WriteW(address + size, val2, instr);
     }
   }
 
   // Do writeback.
   if (wb) {
     set_register(instr, rn, wb_address, R31IsSP);
   }
 }
 
-
 void Simulator::DecodeLoadRegLiteral(Instr* instr) {
   if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) ||
       (instr->Bits(24, 3) != 0)) {
     UnimplementedInstruction(instr);
   }
 
   const Register rt = instr->RtField();
   const int64_t off = instr->SImm19Field() << 2;
   const int64_t pc = reinterpret_cast<int64_t>(instr);
   const int64_t address = pc + off;
   const int64_t val = ReadX(address, instr);
   if (instr->Bit(30)) {
     // Format(instr, "ldrx 'rt, 'pcldr");
     set_register(instr, rt, val, R31IsZR);
   } else {
     // Format(instr, "ldrw 'rt, 'pcldr");
     set_wregister(rt, static_cast<int32_t>(val), R31IsZR);
   }
 }
 
-
 void Simulator::DecodeLoadStoreExclusive(Instr* instr) {
   if ((instr->Bit(23) != 0) || (instr->Bit(21) != 0) || (instr->Bit(15) != 0)) {
     UNIMPLEMENTED();
   }
   const int32_t size = instr->Bits(30, 2);
   if (size != 3 && size != 2) {
     UNIMPLEMENTED();
   }
   const Register rs = instr->RsField();
   const Register rn = instr->RnField();
@@ skipping 19 matching lines @@
       set_register(instr, rs, status, R31IsSP);
     } else {
       uint32_t value = get_register(rt, R31IsSP);
       uword addr = get_register(rn, R31IsSP);
       intptr_t status = WriteExclusiveW(addr, value, instr);
       set_register(instr, rs, status, R31IsSP);
     }
   }
 }
 
-
 void Simulator::DecodeLoadStore(Instr* instr) {
   if (instr->IsLoadStoreRegOp()) {
     DecodeLoadStoreReg(instr);
   } else if (instr->IsLoadStoreRegPairOp()) {
     DecodeLoadStoreRegPair(instr);
   } else if (instr->IsLoadRegLiteralOp()) {
     DecodeLoadRegLiteral(instr);
   } else if (instr->IsLoadStoreExclusiveOp()) {
     DecodeLoadStoreExclusive(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 int64_t Simulator::ShiftOperand(uint8_t reg_size,
                                 int64_t value,
                                 Shift shift_type,
                                 uint8_t amount) {
   if (amount == 0) {
     return value;
   }
   int64_t mask = reg_size == kXRegSizeInBits ? kXRegMask : kWRegMask;
   switch (shift_type) {
     case LSL:
@@ skipping 14 matching lines @@
       return (static_cast<uint64_t>(value) >> amount) |
              ((static_cast<uint64_t>(value) & ((1ULL << amount) - 1ULL))
               << (reg_size - amount));
     }
     default:
       UNIMPLEMENTED();
       return 0;
   }
 }
 
-
 int64_t Simulator::ExtendOperand(uint8_t reg_size,
                                  int64_t value,
                                  Extend extend_type,
                                  uint8_t amount) {
   switch (extend_type) {
     case UXTB:
       value &= 0xff;
       break;
     case UXTH:
       value &= 0xffff;
@@ skipping 14 matching lines @@
     case SXTX:
       break;
     default:
       UNREACHABLE();
       break;
   }
   int64_t mask = (reg_size == kXRegSizeInBits) ? kXRegMask : kWRegMask;
   return (value << amount) & mask;
 }
 
-
 int64_t Simulator::DecodeShiftExtendOperand(Instr* instr) {
   const Register rm = instr->RmField();
   const int64_t rm_val = get_register(rm, R31IsZR);
   const uint8_t size = instr->SFField() ? kXRegSizeInBits : kWRegSizeInBits;
   if (instr->IsShift()) {
     const Shift shift_type = instr->ShiftTypeField();
     const uint8_t shift_amount = instr->Imm6Field();
     return ShiftOperand(size, rm_val, shift_type, shift_amount);
   } else {
     ASSERT(instr->IsExtend());
     const Extend extend_type = instr->ExtendTypeField();
     const uint8_t shift_amount = instr->Imm3Field();
     return ExtendOperand(size, rm_val, extend_type, shift_amount);
   }
   UNREACHABLE();
   return -1;
 }
 
-
 void Simulator::DecodeAddSubShiftExt(Instr* instr) {
   // Format(instr, "add'sf's 'rd, 'rn, 'shift_op");
   // also, sub, cmp, etc.
   const bool addition = (instr->Bit(30) == 0);
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const int64_t rm_val = DecodeShiftExtendOperand(instr);
   if (instr->SFField()) {
     // 64-bit add.
     const int64_t rn_val = get_register(rn, instr->RnMode());
@@ skipping 16 matching lines @@
     const int32_t alu_out = rn_val + rm_val32 + carry_in;
     set_wregister(rd, alu_out, instr->RdMode());
     if (instr->HasS()) {
       SetNZFlagsW(alu_out);
       SetCFlag(CarryFromW(rn_val, rm_val32, carry_in));
       SetVFlag(OverflowFromW(rn_val, rm_val32, carry_in));
     }
   }
 }
 
-
 void Simulator::DecodeAddSubWithCarry(Instr* instr) {
   // Format(instr, "adc'sf's 'rd, 'rn, 'rm");
   // Format(instr, "sbc'sf's 'rd, 'rn, 'rm");
   const bool addition = (instr->Bit(30) == 0);
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
   const int64_t rn_val64 = get_register(rn, R31IsZR);
   const int32_t rn_val32 = get_wregister(rn, R31IsZR);
   const int64_t rm_val64 = get_register(rm, R31IsZR);
@@ skipping 17 matching lines @@
     const int32_t alu_out = rn_val32 + rm_val32 + carry_in;
     set_wregister(rd, alu_out, R31IsZR);
     if (instr->HasS()) {
       SetNZFlagsW(alu_out);
       SetCFlag(CarryFromW(rn_val32, rm_val32, carry_in));
       SetVFlag(OverflowFromW(rn_val32, rm_val32, carry_in));
     }
   }
 }
 
-
 void Simulator::DecodeLogicalShift(Instr* instr) {
   const int op = (instr->Bits(29, 2) << 1) | instr->Bit(21);
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const int64_t rn_val = get_register(rn, instr->RnMode());
   const int64_t rm_val = DecodeShiftExtendOperand(instr);
   int64_t alu_out = 0;
   switch (op) {
     case 0:
       // Format(instr, "and'sf 'rd, 'rn, 'shift_op");
@@ skipping 43 matching lines @@
     SetVFlag(false);
   }
 
   if (instr->SFField() == 1) {
     set_register(instr, rd, alu_out, instr->RdMode());
   } else {
     set_wregister(rd, alu_out & kWRegMask, instr->RdMode());
   }
 }
 
-
 static int64_t divide64(int64_t top, int64_t bottom, bool signd) {
   // ARM64 does not trap on integer division by zero. The destination register
   // is instead set to 0.
   if (bottom == 0) {
     return 0;
   }
 
   if (signd) {
     // INT_MIN / -1 = INT_MIN.
     if ((top == static_cast<int64_t>(0x8000000000000000LL)) &&
         (bottom == static_cast<int64_t>(0xffffffffffffffffLL))) {
       return static_cast<int64_t>(0x8000000000000000LL);
     } else {
       return top / bottom;
     }
   } else {
     const uint64_t utop = static_cast<uint64_t>(top);
     const uint64_t ubottom = static_cast<uint64_t>(bottom);
     return static_cast<int64_t>(utop / ubottom);
   }
 }
 
-
 static int32_t divide32(int32_t top, int32_t bottom, bool signd) {
   // ARM64 does not trap on integer division by zero. The destination register
   // is instead set to 0.
   if (bottom == 0) {
     return 0;
   }
 
   if (signd) {
     // INT_MIN / -1 = INT_MIN.
     if ((top == static_cast<int32_t>(0x80000000)) &&
         (bottom == static_cast<int32_t>(0xffffffff))) {
       return static_cast<int32_t>(0x80000000);
     } else {
       return top / bottom;
     }
   } else {
     const uint32_t utop = static_cast<uint32_t>(top);
     const uint32_t ubottom = static_cast<uint32_t>(bottom);
     return static_cast<int32_t>(utop / ubottom);
   }
 }
 
-
 void Simulator::DecodeMiscDP1Source(Instr* instr) {
   if (instr->Bit(29) != 0) {
     UnimplementedInstruction(instr);
   }
 
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const int op = instr->Bits(10, 10);
   const int64_t rn_val64 = get_register(rn, R31IsZR);
   const int32_t rn_val32 = get_wregister(rn, R31IsZR);
@@ skipping 16 matching lines @@
         set_wregister(rd, rd_val, R31IsZR);
       }
       break;
     }
     default:
       UnimplementedInstruction(instr);
       break;
   }
 }
 
-
 void Simulator::DecodeMiscDP2Source(Instr* instr) {
   if (instr->Bit(29) != 0) {
     UnimplementedInstruction(instr);
   }
 
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
   const int op = instr->Bits(10, 5);
   const int64_t rn_val64 = get_register(rn, R31IsZR);
@@ skipping 47 matching lines @@
         set_wregister(rd, alu_out, R31IsZR);
       }
       break;
     }
     default:
       UnimplementedInstruction(instr);
       break;
   }
 }
 
-
 void Simulator::DecodeMiscDP3Source(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
   const Register ra = instr->RaField();
   if ((instr->Bits(29, 2) == 0) && (instr->Bits(21, 3) == 0) &&
       (instr->Bit(15) == 0)) {
     // Format(instr, "madd'sf 'rd, 'rn, 'rm, 'ra");
     if (instr->SFField() == 1) {
       const int64_t rn_val = get_register(rn, R31IsZR);
@@ skipping 60 matching lines @@
     const uint64_t rn_val = static_cast<uint32_t>(get_wregister(rn, R31IsZR));
     const uint64_t rm_val = static_cast<uint32_t>(get_wregister(rm, R31IsZR));
     const uint64_t ra_val = get_register(ra, R31IsZR);
     const uint64_t alu_out = ra_val + (rn_val * rm_val);
     set_register(instr, rd, alu_out, R31IsZR);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeConditionalSelect(Instr* instr) {
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
   const Register rm = instr->RmField();
   const int64_t rm_val64 = get_register(rm, R31IsZR);
   const int32_t rm_val32 = get_wregister(rm, R31IsZR);
   const int64_t rn_val64 = get_register(rn, instr->RnMode());
   const int32_t rn_val32 = get_wregister(rn, instr->RnMode());
   int64_t result64 = 0;
   int32_t result32 = 0;
@@ skipping 27 matching lines @@
     return;
   }
 
   if (instr->SFField() == 1) {
     set_register(instr, rd, result64, instr->RdMode());
   } else {
     set_wregister(rd, result32, instr->RdMode());
   }
 }
 
-
 void Simulator::DecodeDPRegister(Instr* instr) {
   if (instr->IsAddSubShiftExtOp()) {
     DecodeAddSubShiftExt(instr);
   } else if (instr->IsAddSubWithCarryOp()) {
     DecodeAddSubWithCarry(instr);
   } else if (instr->IsLogicalShiftOp()) {
     DecodeLogicalShift(instr);
   } else if (instr->IsMiscDP1SourceOp()) {
     DecodeMiscDP1Source(instr);
   } else if (instr->IsMiscDP2SourceOp()) {
     DecodeMiscDP2Source(instr);
   } else if (instr->IsMiscDP3SourceOp()) {
     DecodeMiscDP3Source(instr);
   } else if (instr->IsConditionalSelectOp()) {
     DecodeConditionalSelect(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeSIMDCopy(Instr* instr) {
   const int32_t Q = instr->Bit(30);
   const int32_t op = instr->Bit(29);
   const int32_t imm4 = instr->Bits(11, 4);
   const int32_t imm5 = instr->Bits(16, 5);
 
   int32_t idx4 = -1;
   int32_t idx5 = -1;
   int32_t element_bytes;
   if (imm5 & 0x1) {
@@ skipping 74 matching lines @@
     } else if (element_bytes == 8) {
       set_vregisterd(vd, idx5, get_vregisterd(vn, idx4));
     } else {
       UnimplementedInstruction(instr);
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeSIMDThreeSame(Instr* instr) {
   const int Q = instr->Bit(30);
   const int U = instr->Bit(29);
   const int opcode = instr->Bits(11, 5);
 
   if (Q == 0) {
     UnimplementedInstruction(instr);
     return;
   }
 
@@ skipping 136 matching lines @@
         }
       } else {
         UnimplementedInstruction(instr);
         return;
       }
       set_vregisterd(vd, idx, res);
     }
   }
 }
 
-
 static float arm_reciprocal_sqrt_estimate(float a) {
   // From the ARM Architecture Reference Manual A2-87.
   if (isinf(a) || (fabs(a) >= exp2f(126)))
     return 0.0;
   else if (a == 0.0)
     return kPosInfinity;
   else if (isnan(a))
     return a;
 
   uint32_t a_bits = bit_cast<uint32_t, float>(a);
@@ skipping 34 matching lines @@
   double estimate = static_cast<double>(s) / 256.0;
   ASSERT((estimate >= 1.0) && (estimate <= (511.0 / 256.0)));
 
   // result = 0 : result_exp<7:0> : estimate<51:29>
   int32_t result_bits =
       ((result_exp & 0xff) << 23) |
       ((bit_cast<uint64_t, double>(estimate) >> 29) & 0x7fffff);
   return bit_cast<float, int32_t>(result_bits);
 }
 
-
 static float arm_recip_estimate(float a) {
   // From the ARM Architecture Reference Manual A2-85.
   if (isinf(a) || (fabs(a) >= exp2f(126)))
     return 0.0;
   else if (a == 0.0)
     return kPosInfinity;
   else if (isnan(a))
     return a;
 
   uint32_t a_bits = bit_cast<uint32_t, float>(a);
@@ skipping 16 matching lines @@
   double estimate = static_cast<double>(s) / 256.0;
   ASSERT((estimate >= 1.0) && (estimate <= (511.0 / 256.0)));
 
   // result = sign : result_exp<7:0> : estimate<51:29>
   int32_t result_bits =
       (a_bits & 0x80000000) | ((result_exp & 0xff) << 23) |
       ((bit_cast<uint64_t, double>(estimate) >> 29) & 0x7fffff);
   return bit_cast<float, int32_t>(result_bits);
 }
 
-
 void Simulator::DecodeSIMDTwoReg(Instr* instr) {
   const int32_t Q = instr->Bit(30);
   const int32_t U = instr->Bit(29);
   const int32_t op = instr->Bits(12, 5);
   const int32_t sz = instr->Bits(22, 2);
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
 
   if (Q != 1) {
     UnimplementedInstruction(instr);
@@ skipping 81 matching lines @@
       const int32_t vn_val = get_vregisters(vn, i);
       const float vn_flt = bit_cast<float, int32_t>(vn_val);
       const float re = arm_reciprocal_sqrt_estimate(vn_flt);
       set_vregisters(vd, i, bit_cast<int32_t, float>(re));
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeDPSimd1(Instr* instr) {
   if (instr->IsSIMDCopyOp()) {
     DecodeSIMDCopy(instr);
   } else if (instr->IsSIMDThreeSameOp()) {
     DecodeSIMDThreeSame(instr);
   } else if (instr->IsSIMDTwoRegOp()) {
     DecodeSIMDTwoReg(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeFPImm(Instr* instr) {
   if ((instr->Bit(31) != 0) || (instr->Bit(29) != 0) || (instr->Bit(23) != 0) ||
       (instr->Bits(5, 5) != 0)) {
     UnimplementedInstruction(instr);
     return;
   }
   if (instr->Bit(22) == 1) {
     // Double.
     // Format(instr, "fmovd 'vd, #'immd");
     const VRegister vd = instr->VdField();
     const int64_t immd = Instr::VFPExpandImm(instr->Imm8Field());
     set_vregisterd(vd, 0, immd);
     set_vregisterd(vd, 1, 0);
   } else {
     // Single.
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeFPIntCvt(Instr* instr) {
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
   const Register rd = instr->RdField();
   const Register rn = instr->RnField();
 
   if (instr->Bit(29) != 0) {
     UnimplementedInstruction(instr);
     return;
   }
@@ skipping 37 matching lines @@
       const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
       set_register(instr, rd, static_cast<int64_t>(vn_val), instr->RdMode());
     } else {
       UnimplementedInstruction(instr);
     }
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeFPOneSource(Instr* instr) {
   const int opc = instr->Bits(15, 6);
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
   const int64_t vn_val = get_vregisterd(vn, 0);
   const int32_t vn_val32 = vn_val & kWRegMask;
   const double vn_dbl = bit_cast<double, int64_t>(vn_val);
   const float vn_flt = bit_cast<float, int32_t>(vn_val32);
 
   if ((opc != 5) && (instr->Bit(22) != 1)) {
@@ skipping 34 matching lines @@
       break;
     default:
       UnimplementedInstruction(instr);
       break;
   }
 
   set_vregisterd(vd, 0, res_val);
   set_vregisterd(vd, 1, 0);
 }
 
-
 void Simulator::DecodeFPTwoSource(Instr* instr) {
   if (instr->Bits(22, 2) != 1) {
     UnimplementedInstruction(instr);
     return;
   }
   const VRegister vd = instr->VdField();
   const VRegister vn = instr->VnField();
   const VRegister vm = instr->VmField();
   const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
   const double vm_val = bit_cast<double, int64_t>(get_vregisterd(vm, 0));
@@ skipping 19 matching lines @@
       break;
     default:
       UnimplementedInstruction(instr);
       return;
   }
 
   set_vregisterd(vd, 0, bit_cast<int64_t, double>(result));
   set_vregisterd(vd, 1, 0);
 }
 
-
 void Simulator::DecodeFPCompare(Instr* instr) {
   const VRegister vn = instr->VnField();
   const VRegister vm = instr->VmField();
   const double vn_val = bit_cast<double, int64_t>(get_vregisterd(vn, 0));
   double vm_val;
 
   if ((instr->Bit(22) == 1) && (instr->Bits(3, 2) == 0)) {
     // Format(instr, "fcmpd 'vn, 'vm");
     vm_val = bit_cast<double, int64_t>(get_vregisterd(vm, 0));
   } else if ((instr->Bit(22) == 1) && (instr->Bits(3, 2) == 1)) {
@@ skipping 20 matching lines @@
   } else if (vn_val == vm_val) {
     z_flag_ = true;
     c_flag_ = true;
   } else if (vn_val < vm_val) {
     n_flag_ = true;
   } else {
     c_flag_ = true;
   }
 }
 
-
 void Simulator::DecodeFP(Instr* instr) {
   if (instr->IsFPImmOp()) {
     DecodeFPImm(instr);
   } else if (instr->IsFPIntCvtOp()) {
     DecodeFPIntCvt(instr);
   } else if (instr->IsFPOneSourceOp()) {
     DecodeFPOneSource(instr);
   } else if (instr->IsFPTwoSourceOp()) {
     DecodeFPTwoSource(instr);
   } else if (instr->IsFPCompareOp()) {
     DecodeFPCompare(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 void Simulator::DecodeDPSimd2(Instr* instr) {
   if (instr->IsFPOp()) {
     DecodeFP(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 }
 
-
 // Executes the current instruction.
 void Simulator::InstructionDecode(Instr* instr) {
   pc_modified_ = false;
   if (IsTracingExecution()) {
     THR_Print("%" Pu64 " ", icount_);
     const uword start = reinterpret_cast<uword>(instr);
     const uword end = start + Instr::kInstrSize;
     if (FLAG_support_disassembler) {
       Disassembler::Disassemble(start, end);
     } else {
@@ skipping 15 matching lines @@
     DecodeDPSimd2(instr);
   } else {
     UnimplementedInstruction(instr);
   }
 
   if (!pc_modified_) {
     set_pc(reinterpret_cast<int64_t>(instr) + Instr::kInstrSize);
   }
 }
 
-
 void Simulator::Execute() {
   // Get the PC to simulate. Cannot use the accessor here as we need the
   // raw PC value and not the one used as input to arithmetic instructions.
   uword program_counter = get_pc();
 
   if (FLAG_stop_sim_at == ULLONG_MAX) {
     // Fast version of the dispatch loop without checking whether the simulator
     // should be stopping at a particular executed instruction.
     while (program_counter != kEndSimulatingPC) {
       Instr* instr = reinterpret_cast<Instr*>(program_counter);
@@ skipping 20 matching lines @@
       } else if (IsIllegalAddress(program_counter)) {
         HandleIllegalAccess(program_counter, instr);
       } else {
         InstructionDecode(instr);
       }
       program_counter = get_pc();
     }
   }
 }
 
-
 int64_t Simulator::Call(int64_t entry,
                         int64_t parameter0,
                         int64_t parameter1,
                         int64_t parameter2,
                         int64_t parameter3,
                         bool fp_return,
                         bool fp_args) {
   // Save the SP register before the call so we can restore it.
   const intptr_t sp_before_call = get_register(R31, R31IsSP);
 
@@ skipping 72 matching lines @@
   set_register(NULL, R31, sp_before_call, R31IsSP);
   int64_t return_value;
   if (fp_return) {
     return_value = get_vregisterd(V0, 0);
   } else {
     return_value = get_register(R0);
   }
   return return_value;
 }
 
-
 void Simulator::JumpToFrame(uword pc, uword sp, uword fp, Thread* thread) {
   // Walk over all setjmp buffers (simulated --> C++ transitions)
   // and try to find the setjmp associated with the simulated stack pointer.
   SimulatorSetjmpBuffer* buf = last_setjmp_buffer();
   while (buf->link() != NULL && buf->link()->sp() <= sp) {
     buf = buf->link();
   }
   ASSERT(buf != NULL);
 
   // The C++ caller has not cleaned up the stack memory of C++ frames.
@@ skipping 19 matching lines @@
   set_register(NULL, CODE_REG, code);
   set_register(NULL, PP, pp);
   buf->Longjmp();
 }
 
 }  // namespace dart
 
 #endif  // !defined(USING_SIMULATOR)
 
 #endif  // defined TARGET_ARCH_ARM64