VM: Re-format to use at most one newline between functions

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
-#include "vm/intermediate_language.h"
-#include "vm/il_printer.h"
 #include "vm/flow_graph.h"
 #include "vm/flow_graph_compiler.h"
+#include "vm/il_printer.h"
+#include "vm/intermediate_language.h"
 #include "vm/log.h"
 #include "vm/parser.h"
 #include "vm/stack_frame.h"
 
 namespace dart {
 
 #if defined(DEBUG)
 #define TRACE_ALLOC(statement)                                                 \
   do {                                                                         \
     if (FLAG_trace_ssa_allocator) statement;                                   \
   } while (0)
 #else
 #define TRACE_ALLOC(statement)
 #endif
 
-
 static const intptr_t kNoVirtualRegister = -1;
 static const intptr_t kTempVirtualRegister = -2;
 static const intptr_t kIllegalPosition = -1;
 static const intptr_t kMaxPosition = 0x7FFFFFFF;
 static const intptr_t kPairVirtualRegisterOffset = 1;
 
 // Definitions which have pair representations
 // (kPairOfTagged) use two virtual register names.
 // At SSA index allocation time each definition reserves two SSA indexes,
 // the second index is only used for pairs. This function maps from the first
 // SSA index to the second.
 static intptr_t ToSecondPairVreg(intptr_t vreg) {
   // Map vreg to its pair vreg.
   return vreg + kPairVirtualRegisterOffset;
 }
 
-
 static intptr_t MinPosition(intptr_t a, intptr_t b) {
   return (a < b) ? a : b;
 }
 
-
 static bool IsInstructionStartPosition(intptr_t pos) {
   return (pos & 1) == 0;
 }
 
-
 static bool IsInstructionEndPosition(intptr_t pos) {
   return (pos & 1) == 1;
 }
 
-
 static intptr_t ToInstructionStart(intptr_t pos) {
   return (pos & ~1);
 }
 
-
 static intptr_t ToInstructionEnd(intptr_t pos) {
   return (pos | 1);
 }
 
-
 FlowGraphAllocator::FlowGraphAllocator(const FlowGraph& flow_graph,
                                        bool intrinsic_mode)
     : flow_graph_(flow_graph),
       reaching_defs_(flow_graph),
       value_representations_(flow_graph.max_virtual_register_number()),
       block_order_(flow_graph.reverse_postorder()),
       postorder_(flow_graph.postorder()),
       liveness_(flow_graph),
       vreg_count_(flow_graph.max_virtual_register_number()),
       live_ranges_(flow_graph.max_virtual_register_number()),
@@ skipping 30 matching lines @@
   if (intrinsic_mode) {
     blocked_cpu_registers_[ARGS_DESC_REG] = true;
 #if !defined(TARGET_ARCH_IA32)
     // Need to preserve CODE_REG to be able to store the PC marker
     // and load the pool pointer.
     blocked_cpu_registers_[CODE_REG] = true;
 #endif
   }
 }
 
-
 static void DeepLiveness(MaterializeObjectInstr* mat, BitVector* live_in) {
   if (mat->was_visited_for_liveness()) {
     return;
   }
   mat->mark_visited_for_liveness();
 
   for (intptr_t i = 0; i < mat->InputCount(); i++) {
     if (!mat->InputAt(i)->BindsToConstant()) {
       Definition* defn = mat->InputAt(i)->definition();
       MaterializeObjectInstr* inner_mat = defn->AsMaterializeObject();
       if (inner_mat != NULL) {
         DeepLiveness(inner_mat, live_in);
       } else {
         intptr_t idx = defn->ssa_temp_index();
         live_in->Add(idx);
       }
     }
   }
 }
 
-
 void SSALivenessAnalysis::ComputeInitialSets() {
   const intptr_t block_count = postorder_.length();
   for (intptr_t i = 0; i < block_count; i++) {
     BlockEntryInstr* block = postorder_[i];
 
     BitVector* kill = kill_[i];
     BitVector* live_in = live_in_[i];
 
     // Iterate backwards starting at the last instruction.
     for (BackwardInstructionIterator it(block); !it.Done(); it.Advance()) {
@@ skipping 108 matching lines @@
 
   // Process initial definitions, ie, constants and incoming parameters.
   for (intptr_t i = 0; i < graph_entry_->initial_definitions()->length(); i++) {
     Definition* def = (*graph_entry_->initial_definitions())[i];
     const intptr_t vreg = def->ssa_temp_index();
     kill_[graph_entry_->postorder_number()]->Add(vreg);
     live_in_[graph_entry_->postorder_number()]->Remove(vreg);
   }
 }
 
-
 UsePosition* LiveRange::AddUse(intptr_t pos, Location* location_slot) {
   ASSERT(location_slot != NULL);
   ASSERT((first_use_interval_->start_ <= pos) &&
          (pos <= first_use_interval_->end_));
   if (uses_ != NULL) {
     if ((uses_->pos() == pos) && (uses_->location_slot() == location_slot)) {
       return uses_;
     } else if (uses_->pos() < pos) {
       // If an instruction at position P is using the same value both as
       // a fixed register input and a non-fixed input (in this order) we will
@@ skipping 15 matching lines @@
 
       insert_after->set_next(
           new UsePosition(pos, insert_after->next(), location_slot));
       return insert_after->next();
     }
   }
   uses_ = new UsePosition(pos, uses_, location_slot);
   return uses_;
 }
 
-
 void LiveRange::AddSafepoint(intptr_t pos, LocationSummary* locs) {
   ASSERT(IsInstructionStartPosition(pos));
   SafepointPosition* safepoint =
       new SafepointPosition(ToInstructionEnd(pos), locs);
 
   if (first_safepoint_ == NULL) {
     ASSERT(last_safepoint_ == NULL);
     first_safepoint_ = last_safepoint_ = safepoint;
   } else {
     ASSERT(last_safepoint_ != NULL);
     // We assume that safepoints list is sorted by position and that
     // safepoints are added in this order.
     ASSERT(last_safepoint_->pos() < pos);
     last_safepoint_->set_next(safepoint);
     last_safepoint_ = safepoint;
   }
 }
 
-
 void LiveRange::AddHintedUse(intptr_t pos,
                              Location* location_slot,
                              Location* hint) {
   ASSERT(hint != NULL);
   AddUse(pos, location_slot)->set_hint(hint);
 }
 
-
 void LiveRange::AddUseInterval(intptr_t start, intptr_t end) {
   ASSERT(start < end);
 
   // Live ranges are being build by visiting instructions in post-order.
   // This implies that use intervals will be prepended in a monotonically
   // decreasing order.
   if (first_use_interval() != NULL) {
     // If the first use interval and the use interval we are adding
     // touch then we can just extend the first interval to cover their
     // union.
@@ skipping 16 matching lines @@
     ASSERT(end < first_use_interval()->start());
   }
 
   first_use_interval_ = new UseInterval(start, end, first_use_interval_);
   if (last_use_interval_ == NULL) {
     ASSERT(first_use_interval_->next() == NULL);
     last_use_interval_ = first_use_interval_;
   }
 }
 
-
 void LiveRange::DefineAt(intptr_t pos) {
   // Live ranges are being build by visiting instructions in post-order.
   // This implies that use intervals will be prepended in a monotonically
   // decreasing order.
   // When we encounter a use of a value inside a block we optimistically
   // expand the first use interval to cover the block from the start
   // to the last use in the block and then we shrink it if we encounter
   // definition of the value inside the same block.
   if (first_use_interval_ == NULL) {
     // Definition without a use.
     first_use_interval_ = new UseInterval(pos, pos + 1, NULL);
     last_use_interval_ = first_use_interval_;
   } else {
     // Shrink the first use interval. It was optimistically expanded to
     // cover the block from the start to the last use in the block.
     ASSERT(first_use_interval_->start_ <= pos);
     first_use_interval_->start_ = pos;
   }
 }
 
-
 LiveRange* FlowGraphAllocator::GetLiveRange(intptr_t vreg) {
   if (live_ranges_[vreg] == NULL) {
     Representation rep = value_representations_[vreg];
     ASSERT(rep != kNoRepresentation);
     live_ranges_[vreg] = new LiveRange(vreg, rep);
   }
   return live_ranges_[vreg];
 }
 
-
 LiveRange* FlowGraphAllocator::MakeLiveRangeForTemporary() {
   // Representation does not matter for temps.
   Representation ignored = kNoRepresentation;
   LiveRange* range = new LiveRange(kTempVirtualRegister, ignored);
 #if defined(DEBUG)
   temporaries_.Add(range);
 #endif
   return range;
 }
 
-
 void FlowGraphAllocator::BlockRegisterLocation(Location loc,
                                                intptr_t from,
                                                intptr_t to,
                                                bool* blocked_registers,
                                                LiveRange** blocking_ranges) {
   if (blocked_registers[loc.register_code()]) {
     return;
   }
 
   if (blocking_ranges[loc.register_code()] == NULL) {
     Representation ignored = kNoRepresentation;
     LiveRange* range = new LiveRange(kNoVirtualRegister, ignored);
     blocking_ranges[loc.register_code()] = range;
     range->set_assigned_location(loc);
 #if defined(DEBUG)
     temporaries_.Add(range);
 #endif
   }
 
   blocking_ranges[loc.register_code()]->AddUseInterval(from, to);
 }
 
-
 // Block location from the start of the instruction to its end.
 void FlowGraphAllocator::BlockLocation(Location loc,
                                        intptr_t from,
                                        intptr_t to) {
   if (loc.IsRegister()) {
     BlockRegisterLocation(loc, from, to, blocked_cpu_registers_, cpu_regs_);
 #if defined(TARGET_ARCH_DBC)
     last_used_register_ =
         Utils::Maximum(last_used_register_, loc.register_code());
 #endif
   } else if (loc.IsFpuRegister()) {
     BlockRegisterLocation(loc, from, to, blocked_fpu_registers_, fpu_regs_);
   } else {
     UNREACHABLE();
   }
 }
 
-
 void LiveRange::Print() {
   if (first_use_interval() == NULL) {
     return;
   }
 
   THR_Print("  live range v%" Pd " [%" Pd ", %" Pd ") in ", vreg(), Start(),
             End());
   assigned_location().Print();
   if (spill_slot_.HasStackIndex()) {
     intptr_t stack_slot = spill_slot_.stack_index();
@@ skipping 23 matching lines @@
       THR_Print("\n");
       use_pos = use_pos->next();
     }
   }
 
   if (next_sibling() != NULL) {
     next_sibling()->Print();
   }
 }
 
-
 void FlowGraphAllocator::PrintLiveRanges() {
 #if defined(DEBUG)
   for (intptr_t i = 0; i < temporaries_.length(); i++) {
     temporaries_[i]->Print();
   }
 #endif
 
   for (intptr_t i = 0; i < live_ranges_.length(); i++) {
     if (live_ranges_[i] != NULL) {
       live_ranges_[i]->Print();
     }
   }
 }
 
-
 // Returns true if all uses of the given range inside the given loop
 // have Any allocation policy.
 static bool HasOnlyUnconstrainedUsesInLoop(LiveRange* range,
                                            BlockInfo* loop_header) {
   const intptr_t boundary = loop_header->last_block()->end_pos();
 
   UsePosition* use = range->first_use();
   while ((use != NULL) && (use->pos() < boundary)) {
     if (!use->location_slot()->Equals(Location::Any())) {
       return false;
     }
     use = use->next();
   }
 
   return true;
 }
 
-
 // Returns true if all uses of the given range have Any allocation policy.
 static bool HasOnlyUnconstrainedUses(LiveRange* range) {
   UsePosition* use = range->first_use();
   while (use != NULL) {
     if (!use->location_slot()->Equals(Location::Any())) {
       return false;
     }
     use = use->next();
   }
   return true;
 }
 
-
 void FlowGraphAllocator::BuildLiveRanges() {
   const intptr_t block_count = postorder_.length();
   ASSERT(postorder_.Last()->IsGraphEntry());
   BitVector* current_interference_set = NULL;
   Zone* zone = flow_graph_.zone();
   for (intptr_t i = 0; i < (block_count - 1); i++) {
     BlockEntryInstr* block = postorder_[i];
 
     BlockInfo* block_info = BlockInfoAt(block->start_pos());
 
@@ skipping 25 matching lines @@
 
     // Now process all instructions in reverse order.
     while (current != block) {
       // Skip parallel moves that we insert while processing instructions.
       if (!current->IsParallelMove()) {
         ProcessOneInstruction(block, current, current_interference_set);
       }
       current = current->previous();
     }
 
-
     // Check if any values live into the loop can be spilled for free.
     if (block_info->is_loop_header()) {
       current_interference_set = NULL;
       for (BitVector::Iterator it(liveness_.GetLiveInSetAt(i)); !it.Done();
            it.Advance()) {
         LiveRange* range = GetLiveRange(it.Current());
         if (HasOnlyUnconstrainedUsesInLoop(range, block_info)) {
           range->MarkHasOnlyUnconstrainedUsesInLoop(block_info->loop_id());
         }
       }
@@ skipping 40 matching lines @@
   for (intptr_t i = 0; i < graph_entry->initial_definitions()->length(); i++) {
     Definition* defn = (*graph_entry->initial_definitions())[i];
     ASSERT(!defn->HasPairRepresentation());
     LiveRange* range = GetLiveRange(defn->ssa_temp_index());
     range->AddUseInterval(graph_entry->start_pos(), graph_entry->end_pos());
     range->DefineAt(graph_entry->start_pos());
     ProcessInitialDefinition(defn, range, graph_entry);
   }
 }
 
-
 void FlowGraphAllocator::SplitInitialDefinitionAt(LiveRange* range,
                                                   intptr_t pos) {
   if (range->End() > pos) {
     LiveRange* tail = range->SplitAt(pos);
     CompleteRange(tail, Location::kRegister);
   }
 }
 
-
 void FlowGraphAllocator::ProcessInitialDefinition(Definition* defn,
                                                   LiveRange* range,
                                                   BlockEntryInstr* block) {
 #if defined(TARGET_ARCH_DBC)
   if (block->IsCatchBlockEntry()) {
     if (defn->IsParameter()) {
       // This must be in sync with FlowGraphCompiler::CatchEntryRegForVariable.
       ParameterInstr* param = defn->AsParameter();
       intptr_t slot_index = param->index();
       AssignSafepoints(defn, range);
@@ skipping 110 matching lines @@
     // Note, all incoming parameters are assumed to be tagged.
     MarkAsObjectAtSafepoints(range);
   } else if (defn->IsConstant() && block->IsCatchBlockEntry()) {
     // Constants at catch block entries consume spill slots.
     spill_slots_.Add(range_end);
     quad_spill_slots_.Add(false);
     untagged_spill_slots_.Add(false);
   }
 }
 
-
 static Location::Kind RegisterKindFromPolicy(Location loc) {
   if (loc.policy() == Location::kRequiresFpuRegister) {
     return Location::kFpuRegister;
   } else {
     return Location::kRegister;
   }
 }
 
-
 static Location::Kind RegisterKindForResult(Instruction* instr) {
   const Representation rep = instr->representation();
 #if !defined(TARGET_ARCH_DBC)
   if ((rep == kUnboxedDouble) || (rep == kUnboxedFloat32x4) ||
       (rep == kUnboxedInt32x4) || (rep == kUnboxedFloat64x2)) {
     return Location::kFpuRegister;
   } else {
     return Location::kRegister;
   }
 #else
   // DBC supports only unboxed doubles and does not have distinguished FPU
   // registers.
   ASSERT((rep != kUnboxedFloat32x4) && (rep != kUnboxedInt32x4) &&
          (rep != kUnboxedFloat64x2));
   return Location::kRegister;
 #endif
 }
 
-
 //
 // When describing shape of live ranges in comments below we are going to use
 // the following notation:
 //
 //    B    block entry
 //    g g' start and end of goto instruction
 //    i i' start and end of any other instruction
 //    j j' start and end of any other instruction
 
 //    -  body of a use interval
@@ skipping 77 matching lines @@
                               ->assigned_location_slot());
       move->set_src(Location::PrefersRegister());
     }
   }
 
   // Begin backward iteration with the instruction before the parallel
   // move.
   return goto_instr->previous();
 }
 
-
 void FlowGraphAllocator::ConnectIncomingPhiMoves(JoinEntryInstr* join) {
   // For join blocks we need to add destinations of phi resolution moves
   // to phi's live range so that register allocator will fill them with moves.
 
   // All uses are recorded at the start position in the block.
   const intptr_t pos = join->start_pos();
   const bool is_loop_header = BlockInfoAt(join->start_pos())->is_loop_header();
   intptr_t move_idx = 0;
   for (PhiIterator it(join); !it.Done(); it.Advance()) {
     PhiInstr* phi = it.Current();
@@ skipping 41 matching lines @@
     if (is_pair_phi) {
       LiveRange* second_range = GetLiveRange(ToSecondPairVreg(vreg));
       AssignSafepoints(phi, second_range);
       CompleteRange(second_range, RegisterKindForResult(phi));
     }
 
     move_idx += is_pair_phi ? 2 : 1;
   }
 }
 
-
 void FlowGraphAllocator::ProcessEnvironmentUses(BlockEntryInstr* block,
                                                 Instruction* current) {
   ASSERT(current->env() != NULL);
   Environment* env = current->env();
   while (env != NULL) {
     // Any value mentioned in the deoptimization environment should survive
     // until the end of instruction but it does not need to be in the register.
     // Expected shape of live range:
     //
     //                 i  i'
@@ skipping 61 matching lines @@
         range->AddUseInterval(block_start_pos, use_pos);
         range->AddUse(use_pos, &locations[i]);
       }
     }
 
     env->set_locations(locations);
     env = env->outer();
   }
 }
 
-
 void FlowGraphAllocator::ProcessMaterializationUses(
     BlockEntryInstr* block,
     const intptr_t block_start_pos,
     const intptr_t use_pos,
     MaterializeObjectInstr* mat) {
   // Materialization can occur several times in the same environment.
   // Check if we already processed this one.
   if (mat->locations() != NULL) {
     return;  // Already processed.
   }
@@ skipping 33 matching lines @@
                                  def->AsMaterializeObject());
     } else {
       locations[i] = Location::Any();
       LiveRange* range = GetLiveRange(def->ssa_temp_index());
       range->AddUseInterval(block_start_pos, use_pos);
       range->AddUse(use_pos, &locations[i]);
     }
   }
 }
 
-
 void FlowGraphAllocator::ProcessOneInput(BlockEntryInstr* block,
                                          intptr_t pos,
                                          Location* in_ref,
                                          Value* input,
                                          intptr_t vreg,
                                          RegisterSet* live_registers) {
   ASSERT(in_ref != NULL);
   ASSERT(!in_ref->IsPairLocation());
   ASSERT(input != NULL);
   ASSERT(block != NULL);
@@ skipping 43 matching lines @@
       //      value    -----*
       //
       range->AddUseInterval(block->start_pos(), pos + 1);
       range->AddUse(pos + 1, in_ref);
     }
   } else {
     ASSERT(in_ref->IsConstant());
   }
 }
 
-
 void FlowGraphAllocator::ProcessOneOutput(BlockEntryInstr* block,
                                           intptr_t pos,
                                           Location* out,
                                           Definition* def,
                                           intptr_t vreg,
                                           bool output_same_as_first_input,
                                           Location* in_ref,
                                           Definition* input,
                                           intptr_t input_vreg,
                                           BitVector* interference_set) {
@@ skipping 87 matching lines @@
     // Shorten live range to the point of definition and add use to be filled by
     // allocator.
     range->DefineAt(pos);
     range->AddUse(pos, out);
   }
 
   AssignSafepoints(def, range);
   CompleteRange(range, RegisterKindForResult(def));
 }
 
-
 // Create and update live ranges corresponding to instruction's inputs,
 // temporaries and output.
 void FlowGraphAllocator::ProcessOneInstruction(BlockEntryInstr* block,
                                                Instruction* current,
                                                BitVector* interference_set) {
   LocationSummary* locs = current->locs();
 
   Definition* def = current->AsDefinition();
   if ((def != NULL) && (def->AsConstant() != NULL)) {
     ASSERT(!def->HasPairRepresentation());
@@ skipping 129 matching lines @@
       BlockLocation(Location::RegisterLocation(static_cast<Register>(reg)), pos,
                     pos + 1);
     }
 
     for (intptr_t reg = 0; reg < kNumberOfFpuRegisters; reg++) {
       BlockLocation(
           Location::FpuRegisterLocation(static_cast<FpuRegister>(reg)), pos,
           pos + 1);
     }
 
-
 #if defined(DEBUG)
     // Verify that temps, inputs and output were specified as fixed
     // locations.  Every register is blocked now so attempt to
     // allocate will not succeed.
     for (intptr_t j = 0; j < locs->temp_count(); j++) {
       ASSERT(!locs->temp(j).IsPairLocation());
       ASSERT(!locs->temp(j).IsUnallocated());
     }
 
     for (intptr_t j = 0; j < locs->input_count(); j++) {
@@ skipping 79 matching lines @@
                        interference_set);
     } else {
       ProcessOneOutput(block, pos, out, def, def->ssa_temp_index(),
                        false,           // output is not mapped to first input.
                        NULL, NULL, -1,  // First input not needed.
                        interference_set);
     }
   }
 }
 
-
 static ParallelMoveInstr* CreateParallelMoveBefore(Instruction* instr,
                                                    intptr_t pos) {
   ASSERT(pos > 0);
   Instruction* prev = instr->previous();
   ParallelMoveInstr* move = prev->AsParallelMove();
   if ((move == NULL) || (move->lifetime_position() != pos)) {
     move = new ParallelMoveInstr();
     prev->LinkTo(move);
     move->LinkTo(instr);
     move->set_lifetime_position(pos);
   }
   return move;
 }
 
-
 static ParallelMoveInstr* CreateParallelMoveAfter(Instruction* instr,
                                                   intptr_t pos) {
   Instruction* next = instr->next();
   if (next->IsParallelMove() && (next->lifetime_position() == pos)) {
     return next->AsParallelMove();
   }
   return CreateParallelMoveBefore(next, pos);
 }
 
-
 // Linearize the control flow graph.  The chosen order will be used by the
 // linear-scan register allocator.  Number most instructions with a pair of
 // numbers representing lifetime positions.  Introduce explicit parallel
 // move instructions in the predecessors of join nodes.  The moves are used
 // for phi resolution.
 void FlowGraphAllocator::NumberInstructions() {
   intptr_t pos = 0;
 
   // The basic block order is reverse postorder.
   const intptr_t block_count = postorder_.length();
@@ skipping 44 matching lines @@
 
         // Populate the ParallelMove with empty moves.
         for (intptr_t j = 0; j < move_count; j++) {
           move->AddMove(Location::NoLocation(), Location::NoLocation());
         }
       }
     }
   }
 }
 
-
 // Discover structural (reducible) loops nesting structure.
 void FlowGraphAllocator::DiscoverLoops() {
   // This algorithm relies on the assumption that we emit blocks in reverse
   // postorder, so postorder number can be used to identify loop nesting.
   //
   // TODO(vegorov): consider using a generic algorithm to correctly discover
   // both headers of reducible and irreducible loops.
   BlockInfo* current_loop = NULL;
 
   intptr_t loop_id = 0;  // All loop headers have a unique id.
@@ skipping 29 matching lines @@
       if (current_info == current_loop) {
         ASSERT(current_loop->is_loop_header());
         current_loop = current_info->loop();
       } else {
         current_info->set_loop(current_loop);
       }
     }
   }
 }
 
-
 Instruction* FlowGraphAllocator::InstructionAt(intptr_t pos) const {
   return instructions_[pos / 2];
 }
 
-
 BlockInfo* FlowGraphAllocator::BlockInfoAt(intptr_t pos) const {
   return block_info_[pos / 2];
 }
 
-
 bool FlowGraphAllocator::IsBlockEntry(intptr_t pos) const {
   return IsInstructionStartPosition(pos) && InstructionAt(pos)->IsBlockEntry();
 }
 
-
 void AllocationFinger::Initialize(LiveRange* range) {
   first_pending_use_interval_ = range->first_use_interval();
   first_register_use_ = range->first_use();
   first_register_beneficial_use_ = range->first_use();
   first_hinted_use_ = range->first_use();
 }
 
-
 bool AllocationFinger::Advance(const intptr_t start) {
   UseInterval* a = first_pending_use_interval_;
   while (a != NULL && a->end() <= start)
     a = a->next();
   first_pending_use_interval_ = a;
   return (first_pending_use_interval_ == NULL);
 }
 
-
 Location AllocationFinger::FirstHint() {
   UsePosition* use = first_hinted_use_;
 
   while (use != NULL) {
     if (use->HasHint()) return use->hint();
     use = use->next();
   }
 
   return Location::NoLocation();
 }
 
-
 static UsePosition* FirstUseAfter(UsePosition* use, intptr_t after) {
   while ((use != NULL) && (use->pos() < after)) {
     use = use->next();
   }
   return use;
 }
 
-
 UsePosition* AllocationFinger::FirstRegisterUse(intptr_t after) {
   for (UsePosition* use = FirstUseAfter(first_register_use_, after);
        use != NULL; use = use->next()) {
     Location* loc = use->location_slot();
     if (loc->IsUnallocated() &&
         ((loc->policy() == Location::kRequiresRegister) ||
          (loc->policy() == Location::kRequiresFpuRegister))) {
       first_register_use_ = use;
       return use;
     }
   }
   return NULL;
 }
 
-
 UsePosition* AllocationFinger::FirstRegisterBeneficialUse(intptr_t after) {
   for (UsePosition* use = FirstUseAfter(first_register_beneficial_use_, after);
        use != NULL; use = use->next()) {
     Location* loc = use->location_slot();
     if (loc->IsUnallocated() && loc->IsRegisterBeneficial()) {
       first_register_beneficial_use_ = use;
       return use;
     }
   }
   return NULL;
 }
 
-
 UsePosition* AllocationFinger::FirstInterferingUse(intptr_t after) {
   if (IsInstructionEndPosition(after)) {
     // If after is a position at the end of the instruction disregard
     // any use occurring at it.
     after += 1;
   }
   return FirstRegisterUse(after);
 }
 
-
 void AllocationFinger::UpdateAfterSplit(intptr_t first_use_after_split_pos) {
   if ((first_register_use_ != NULL) &&
       (first_register_use_->pos() >= first_use_after_split_pos)) {
     first_register_use_ = NULL;
   }
 
   if ((first_register_beneficial_use_ != NULL) &&
       (first_register_beneficial_use_->pos() >= first_use_after_split_pos)) {
     first_register_beneficial_use_ = NULL;
   }
 }
 
-
 intptr_t UseInterval::Intersect(UseInterval* other) {
   if (this->start() <= other->start()) {
     if (other->start() < this->end()) return other->start();
   } else if (this->start() < other->end()) {
     return this->start();
   }
   return kIllegalPosition;
 }
 
-
 static intptr_t FirstIntersection(UseInterval* a, UseInterval* u) {
   while (a != NULL && u != NULL) {
     const intptr_t pos = a->Intersect(u);
     if (pos != kIllegalPosition) return pos;
 
     if (a->start() < u->start()) {
       a = a->next();
     } else {
       u = u->next();
     }
   }
 
   return kMaxPosition;
 }
 
-
 template <typename PositionType>
 PositionType* SplitListOfPositions(PositionType** head,
                                    intptr_t split_pos,
                                    bool split_at_start) {
   PositionType* last_before_split = NULL;
   PositionType* pos = *head;
   if (split_at_start) {
     while ((pos != NULL) && (pos->pos() < split_pos)) {
       last_before_split = pos;
       pos = pos->next();
     }
   } else {
     while ((pos != NULL) && (pos->pos() <= split_pos)) {
       last_before_split = pos;
       pos = pos->next();
     }
   }
 
   if (last_before_split == NULL) {
     *head = NULL;
   } else {
     last_before_split->set_next(NULL);
   }
 
   return pos;
 }
 
-
 LiveRange* LiveRange::SplitAt(intptr_t split_pos) {
   if (Start() == split_pos) return this;
 
   UseInterval* interval = finger_.first_pending_use_interval();
   if (interval == NULL) {
     finger_.Initialize(this);
     interval = finger_.first_pending_use_interval();
   }
 
   ASSERT(split_pos < End());
@@ skipping 43 matching lines @@
   last_use_interval_ = last_before_split;
   last_use_interval_->next_ = NULL;
 
   if (first_use_after_split != NULL) {
     finger_.UpdateAfterSplit(first_use_after_split->pos());
   }
 
   return next_sibling_;
 }
 
-
 LiveRange* FlowGraphAllocator::SplitBetween(LiveRange* range,
                                             intptr_t from,
                                             intptr_t to) {
   TRACE_ALLOC(THR_Print("split v%" Pd " [%" Pd ", %" Pd ") between [%" Pd
                         ", %" Pd ")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
 
   intptr_t split_pos = kIllegalPosition;
 
   BlockInfo* split_block = BlockInfoAt(to);
@@ skipping 18 matching lines @@
     // instruction.
     split_pos = ToInstructionStart(to) - 1;
   }
 
   ASSERT(split_pos != kIllegalPosition);
   ASSERT(from < split_pos);
 
   return range->SplitAt(split_pos);
 }
 
-
 void FlowGraphAllocator::SpillBetween(LiveRange* range,
                                       intptr_t from,
                                       intptr_t to) {
   ASSERT(from < to);
   TRACE_ALLOC(THR_Print("spill v%" Pd " [%" Pd ", %" Pd ") "
                         "between [%" Pd ", %" Pd ")\n",
                         range->vreg(), range->Start(), range->End(), from, to));
   LiveRange* tail = range->SplitAt(from);
 
   if (tail->Start() < to) {
     // There is an intersection of tail and [from, to).
     LiveRange* tail_tail = SplitBetween(tail, tail->Start(), to);
     Spill(tail);
     AddToUnallocated(tail_tail);
   } else {
     // No intersection between tail and [from, to).
     AddToUnallocated(tail);
   }
 }
 
-
 void FlowGraphAllocator::SpillAfter(LiveRange* range, intptr_t from) {
   TRACE_ALLOC(THR_Print("spill v%" Pd " [%" Pd ", %" Pd ") after %" Pd "\n",
                         range->vreg(), range->Start(), range->End(), from));
 
   // When spilling the value inside the loop check if this spill can
   // be moved outside.
   BlockInfo* block_info = BlockInfoAt(from);
   if (block_info->is_loop_header() || (block_info->loop() != NULL)) {
     BlockInfo* loop_header =
         block_info->is_loop_header() ? block_info : block_info->loop();
 
     if ((range->Start() <= loop_header->entry()->start_pos()) &&
         RangeHasOnlyUnconstrainedUsesInLoop(range, loop_header->loop_id())) {
       ASSERT(loop_header->entry()->start_pos() <= from);
       from = loop_header->entry()->start_pos();
       TRACE_ALLOC(
           THR_Print("  moved spill position to loop header %" Pd "\n", from));
     }
   }
 
   LiveRange* tail = range->SplitAt(from);
   Spill(tail);
 }
 
-
 void FlowGraphAllocator::AllocateSpillSlotFor(LiveRange* range) {
 #if defined(TARGET_ARCH_DBC)
   // There is no need to support spilling on DBC because we have a lot of
   // registers and registers and spill-slots have the same performance
   // characteristics.
   flow_graph_.parsed_function().Bailout("FlowGraphAllocator", "SPILL");
   UNREACHABLE();
 #endif
 
   ASSERT(range->spill_slot().IsInvalid());
@@ skipping 77 matching lines @@
     } else {
       ASSERT((range->representation() == kUnboxedDouble));
       location = Location::DoubleStackSlot(slot_idx);
     }
     range->set_spill_slot(location);
   }
 
   spilled_.Add(range);
 }
 
-
 void FlowGraphAllocator::MarkAsObjectAtSafepoints(LiveRange* range) {
   intptr_t stack_index = range->spill_slot().stack_index();
   ASSERT(stack_index >= 0);
 
   while (range != NULL) {
     for (SafepointPosition* safepoint = range->first_safepoint();
          safepoint != NULL; safepoint = safepoint->next()) {
       // Mark the stack slot as having an object.
       safepoint->locs()->SetStackBit(stack_index);
     }
     range = range->next_sibling();
   }
 }
 
-
 void FlowGraphAllocator::Spill(LiveRange* range) {
   LiveRange* parent = GetLiveRange(range->vreg());
   if (parent->spill_slot().IsInvalid()) {
     AllocateSpillSlotFor(parent);
     if (range->representation() == kTagged) {
       MarkAsObjectAtSafepoints(parent);
     }
   }
   range->set_assigned_location(parent->spill_slot());
   ConvertAllUses(range);
 }
 
-
 intptr_t FlowGraphAllocator::FirstIntersectionWithAllocated(
     intptr_t reg,
     LiveRange* unallocated) {
   intptr_t intersection = kMaxPosition;
   for (intptr_t i = 0; i < registers_[reg]->length(); i++) {
     LiveRange* allocated = (*registers_[reg])[i];
     if (allocated == NULL) continue;
 
     UseInterval* allocated_head =
         allocated->finger()->first_pending_use_interval();
     if (allocated_head->start() >= intersection) continue;
 
     const intptr_t pos = FirstIntersection(
         unallocated->finger()->first_pending_use_interval(), allocated_head);
     if (pos < intersection) intersection = pos;
   }
   return intersection;
 }
 
-
 void ReachingDefs::AddPhi(PhiInstr* phi) {
   if (phi->reaching_defs() == NULL) {
     Zone* zone = flow_graph_.zone();
     phi->set_reaching_defs(
         new (zone) BitVector(zone, flow_graph_.max_virtual_register_number()));
 
     // Compute initial set reaching defs set.
     bool depends_on_phi = false;
     for (intptr_t i = 0; i < phi->InputCount(); i++) {
       Definition* input = phi->InputAt(i)->definition();
       if (input->IsPhi()) {
         depends_on_phi = true;
       }
       phi->reaching_defs()->Add(input->ssa_temp_index());
       if (phi->HasPairRepresentation()) {
         phi->reaching_defs()->Add(ToSecondPairVreg(input->ssa_temp_index()));
       }
     }
 
     // If this phi depends on another phi then we need fix point iteration.
     if (depends_on_phi) phis_.Add(phi);
   }
 }
 
-
 void ReachingDefs::Compute() {
   // Transitively collect all phis that are used by the given phi.
   for (intptr_t i = 0; i < phis_.length(); i++) {
     PhiInstr* phi = phis_[i];
 
     // Add all phis that affect this phi to the list.
     for (intptr_t i = 0; i < phi->InputCount(); i++) {
       PhiInstr* input_phi = phi->InputAt(i)->definition()->AsPhi();
       if (input_phi != NULL) {
         AddPhi(input_phi);
@@ skipping 14 matching lines @@
             changed = true;
           }
         }
       }
     }
   } while (changed);
 
   phis_.Clear();
 }
 
-
 BitVector* ReachingDefs::Get(PhiInstr* phi) {
   if (phi->reaching_defs() == NULL) {
     ASSERT(phis_.is_empty());
     AddPhi(phi);
     Compute();
   }
   return phi->reaching_defs();
 }
 
-
 bool FlowGraphAllocator::AllocateFreeRegister(LiveRange* unallocated) {
   intptr_t candidate = kNoRegister;
   intptr_t free_until = 0;
 
   // If hint is available try hint first.
   // TODO(vegorov): ensure that phis are hinted on the back edge.
   Location hint = unallocated->finger()->FirstHint();
   if (hint.IsMachineRegister()) {
     if (!blocked_registers_[hint.register_code()]) {
       free_until =
@@ skipping 109 matching lines @@
 
   registers_[candidate]->Add(unallocated);
   unallocated->set_assigned_location(MakeRegisterLocation(candidate));
 #if defined(TARGET_ARCH_DBC)
   last_used_register_ = Utils::Maximum(last_used_register_, candidate);
 #endif
 
   return true;
 }
 
-
 bool FlowGraphAllocator::RangeHasOnlyUnconstrainedUsesInLoop(LiveRange* range,
                                                              intptr_t loop_id) {
   if (range->vreg() >= 0) {
     LiveRange* parent = GetLiveRange(range->vreg());
     return parent->HasOnlyUnconstrainedUsesInLoop(loop_id);
   }
   return false;
 }
 
-
 bool FlowGraphAllocator::IsCheapToEvictRegisterInLoop(BlockInfo* loop,
                                                       intptr_t reg) {
   const intptr_t loop_start = loop->entry()->start_pos();
   const intptr_t loop_end = loop->last_block()->end_pos();
 
   for (intptr_t i = 0; i < registers_[reg]->length(); i++) {
     LiveRange* allocated = (*registers_[reg])[i];
 
     UseInterval* interval = allocated->finger()->first_pending_use_interval();
     if (interval->Contains(loop_start)) {
       if (!RangeHasOnlyUnconstrainedUsesInLoop(allocated, loop->loop_id())) {
         return false;
       }
     } else if (interval->start() < loop_end) {
       return false;
     }
   }
 
   return true;
 }
 
-
 bool FlowGraphAllocator::HasCheapEvictionCandidate(LiveRange* phi_range) {
   ASSERT(phi_range->is_loop_phi());
 
   BlockInfo* loop_header = BlockInfoAt(phi_range->Start());
   ASSERT(loop_header->is_loop_header());
   ASSERT(phi_range->Start() == loop_header->entry()->start_pos());
 
   for (intptr_t reg = 0; reg < NumberOfRegisters(); ++reg) {
     if (blocked_registers_[reg]) continue;
     if (IsCheapToEvictRegisterInLoop(loop_header, reg)) {
       return true;
     }
   }
 
   return false;
 }
 
-
 void FlowGraphAllocator::AllocateAnyRegister(LiveRange* unallocated) {
   // If a loop phi has no register uses we might still want to allocate it
   // to the register to reduce amount of memory moves on the back edge.
   // This is possible if there is a register blocked by a range that can be
   // cheaply evicted i.e. it has no register beneficial uses inside the
   // loop.
   UsePosition* register_use =
       unallocated->finger()->FirstRegisterUse(unallocated->Start());
   if ((register_use == NULL) &&
       !(unallocated->is_loop_phi() && HasCheapEvictionCandidate(unallocated))) {
@@ skipping 32 matching lines @@
     // Register is blocked before the end of the live range.  Split the range
     // at latest at blocked_at position.
     LiveRange* tail =
         SplitBetween(unallocated, unallocated->Start(), blocked_at + 1);
     AddToUnallocated(tail);
   }
 
   AssignNonFreeRegister(unallocated, candidate);
 }
 
-
 bool FlowGraphAllocator::UpdateFreeUntil(intptr_t reg,
                                          LiveRange* unallocated,
                                          intptr_t* cur_free_until,
                                          intptr_t* cur_blocked_at) {
   intptr_t free_until = kMaxPosition;
   intptr_t blocked_at = kMaxPosition;
   const intptr_t start = unallocated->Start();
 
   for (intptr_t i = 0; i < registers_[reg]->length(); i++) {
     LiveRange* allocated = (*registers_[reg])[i];
@@ skipping 33 matching lines @@
       return false;
     }
   }
 
   ASSERT(free_until > *cur_free_until);
   *cur_free_until = free_until;
   *cur_blocked_at = blocked_at;
   return true;
 }
 
-
 void FlowGraphAllocator::RemoveEvicted(intptr_t reg, intptr_t first_evicted) {
   intptr_t to = first_evicted;
   intptr_t from = first_evicted + 1;
   while (from < registers_[reg]->length()) {
     LiveRange* allocated = (*registers_[reg])[from++];
     if (allocated != NULL) (*registers_[reg])[to++] = allocated;
   }
   registers_[reg]->TruncateTo(to);
 }
 
-
 void FlowGraphAllocator::AssignNonFreeRegister(LiveRange* unallocated,
                                                intptr_t reg) {
   intptr_t first_evicted = -1;
   for (intptr_t i = registers_[reg]->length() - 1; i >= 0; i--) {
     LiveRange* allocated = (*registers_[reg])[i];
     if (allocated->vreg() < 0) continue;  // Can't be evicted.
     if (EvictIntersection(allocated, unallocated)) {
       // If allocated was not spilled convert all pending uses.
       if (allocated->assigned_location().IsMachineRegister()) {
         ASSERT(allocated->End() <= unallocated->Start());
         ConvertAllUses(allocated);
       }
       (*registers_[reg])[i] = NULL;
       first_evicted = i;
     }
   }
 
   // Remove evicted ranges from the array.
   if (first_evicted != -1) RemoveEvicted(reg, first_evicted);
 
   registers_[reg]->Add(unallocated);
   unallocated->set_assigned_location(MakeRegisterLocation(reg));
 #if defined(TARGET_ARCH_DBC)
   last_used_register_ = Utils::Maximum(last_used_register_, reg);
 #endif
 }
 
-
 bool FlowGraphAllocator::EvictIntersection(LiveRange* allocated,
                                            LiveRange* unallocated) {
   UseInterval* first_unallocated =
       unallocated->finger()->first_pending_use_interval();
   const intptr_t intersection = FirstIntersection(
       allocated->finger()->first_pending_use_interval(), first_unallocated);
   if (intersection == kMaxPosition) return false;
 
   const intptr_t spill_position = first_unallocated->start();
   UsePosition* use = allocated->finger()->FirstInterferingUse(spill_position);
   if (use == NULL) {
     // No register uses after this point.
     SpillAfter(allocated, spill_position);
   } else {
     const intptr_t restore_position =
         (spill_position < intersection) ? MinPosition(intersection, use->pos())
                                         : use->pos();
 
     SpillBetween(allocated, spill_position, restore_position);
   }
 
   return true;
 }
 
-
 MoveOperands* FlowGraphAllocator::AddMoveAt(intptr_t pos,
                                             Location to,
                                             Location from) {
   ASSERT(!IsBlockEntry(pos));
 
   if (pos < kNormalEntryPos) {
     ASSERT(pos > 0);
     // Parallel moves added to the GraphEntry (B0) will be added at the start
     // of the normal entry (B1)
     BlockEntryInstr* entry = InstructionAt(kNormalEntryPos)->AsBlockEntry();
     return entry->GetParallelMove()->AddMove(to, from);
   }
 
   Instruction* instr = InstructionAt(pos);
 
   ParallelMoveInstr* parallel_move = NULL;
   if (IsInstructionStartPosition(pos)) {
     parallel_move = CreateParallelMoveBefore(instr, pos);
   } else {
     parallel_move = CreateParallelMoveAfter(instr, pos);
   }
 
   return parallel_move->AddMove(to, from);
 }
 
-
 void FlowGraphAllocator::ConvertUseTo(UsePosition* use, Location loc) {
   ASSERT(!loc.IsPairLocation());
   ASSERT(use->location_slot() != NULL);
   Location* slot = use->location_slot();
   ASSERT(slot->IsUnallocated());
   TRACE_ALLOC(THR_Print("  use at %" Pd " converted to ", use->pos()));
   TRACE_ALLOC(loc.Print());
   TRACE_ALLOC(THR_Print("\n"));
   *slot = loc;
 }
 
-
 void FlowGraphAllocator::ConvertAllUses(LiveRange* range) {
   if (range->vreg() == kNoVirtualRegister) return;
 
   const Location loc = range->assigned_location();
   ASSERT(!loc.IsInvalid());
 
   TRACE_ALLOC(THR_Print("range [%" Pd ", %" Pd ") "
                         "for v%" Pd " has been allocated to ",
                         range->Start(), range->End(), range->vreg()));
   TRACE_ALLOC(loc.Print());
@@ skipping 15 matching lines @@
       }
 #else
       if (range->representation() == kTagged) {
         safepoint->locs()->SetStackBit(loc.reg());
       }
 #endif  // !defined(TARGET_ARCH_DBC)
     }
   }
 }
 
-
 void FlowGraphAllocator::AdvanceActiveIntervals(const intptr_t start) {
   for (intptr_t reg = 0; reg < NumberOfRegisters(); reg++) {
     if (registers_[reg]->is_empty()) continue;
 
     intptr_t first_evicted = -1;
     for (intptr_t i = registers_[reg]->length() - 1; i >= 0; i--) {
       LiveRange* range = (*registers_[reg])[i];
       if (range->finger()->Advance(start)) {
         ConvertAllUses(range);
         (*registers_[reg])[i] = NULL;
         first_evicted = i;
       }
     }
 
     if (first_evicted != -1) RemoveEvicted(reg, first_evicted);
   }
 }
 
-
 bool LiveRange::Contains(intptr_t pos) const {
   if (!CanCover(pos)) return false;
 
   for (UseInterval* interval = first_use_interval_; interval != NULL;
        interval = interval->next()) {
     if (interval->Contains(pos)) {
       return true;
     }
   }
 
   return false;
 }
 
-
 void FlowGraphAllocator::AssignSafepoints(Definition* defn, LiveRange* range) {
   for (intptr_t i = safepoints_.length() - 1; i >= 0; i--) {
     Instruction* safepoint_instr = safepoints_[i];
     if (safepoint_instr == defn) {
       // The value is not live until after the definition is fully executed,
       // don't assign the safepoint inside the definition itself to
       // definition's liverange.
       continue;
     }
 
     const intptr_t pos = safepoint_instr->lifetime_position();
     if (range->End() <= pos) break;
 
     if (range->Contains(pos)) {
       range->AddSafepoint(pos, safepoint_instr->locs());
     }
   }
 }
 
-
 static inline bool ShouldBeAllocatedBefore(LiveRange* a, LiveRange* b) {
   // TODO(vegorov): consider first hint position when ordering live ranges.
   return a->Start() <= b->Start();
 }
 
-
 static void AddToSortedListOfRanges(GrowableArray<LiveRange*>* list,
                                     LiveRange* range) {
   range->finger()->Initialize(range);
 
   if (list->is_empty()) {
     list->Add(range);
     return;
   }
 
   for (intptr_t i = list->length() - 1; i >= 0; i--) {
     if (ShouldBeAllocatedBefore(range, (*list)[i])) {
       list->InsertAt(i + 1, range);
       return;
     }
   }
   list->InsertAt(0, range);
 }
 
-
 void FlowGraphAllocator::AddToUnallocated(LiveRange* range) {
   AddToSortedListOfRanges(&unallocated_, range);
 }
 
-
 void FlowGraphAllocator::CompleteRange(LiveRange* range, Location::Kind kind) {
   switch (kind) {
     case Location::kRegister:
       AddToSortedListOfRanges(&unallocated_cpu_, range);
       break;
 
     case Location::kFpuRegister:
       AddToSortedListOfRanges(&unallocated_xmm_, range);
       break;
 
     default:
       UNREACHABLE();
   }
 }
 
-
 #if defined(DEBUG)
 bool FlowGraphAllocator::UnallocatedIsSorted() {
   for (intptr_t i = unallocated_.length() - 1; i >= 1; i--) {
     LiveRange* a = unallocated_[i];
     LiveRange* b = unallocated_[i - 1];
     if (!ShouldBeAllocatedBefore(a, b)) {
       UNREACHABLE();
       return false;
     }
   }
   return true;
 }
 #endif
 
-
 void FlowGraphAllocator::PrepareForAllocation(
     Location::Kind register_kind,
     intptr_t number_of_registers,
     const GrowableArray<LiveRange*>& unallocated,
     LiveRange** blocking_ranges,
     bool* blocked_registers) {
   register_kind_ = register_kind;
   number_of_registers_ = number_of_registers;
 
   blocked_registers_.Clear();
@@ skipping 10 matching lines @@
     ASSERT(registers_[reg]->is_empty());
 
     LiveRange* range = blocking_ranges[reg];
     if (range != NULL) {
       range->finger()->Initialize(range);
       registers_[reg]->Add(range);
     }
   }
 }
 
-
 void FlowGraphAllocator::AllocateUnallocatedRanges() {
 #if defined(DEBUG)
   ASSERT(UnallocatedIsSorted());
 #endif
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.RemoveLast();
     const intptr_t start = range->Start();
     TRACE_ALLOC(THR_Print("Processing live range for v%" Pd " "
                           "starting at %" Pd "\n",
@@ skipping 14 matching lines @@
   }
 
   // All allocation decisions were done.
   ASSERT(unallocated_.is_empty());
 
   // Finish allocation.
   AdvanceActiveIntervals(kMaxPosition);
   TRACE_ALLOC(THR_Print("Allocation completed\n"));
 }
 
-
 bool FlowGraphAllocator::TargetLocationIsSpillSlot(LiveRange* range,
                                                    Location target) {
   if (target.IsStackSlot() || target.IsDoubleStackSlot() ||
       target.IsConstant()) {
     ASSERT(GetLiveRange(range->vreg())->spill_slot().Equals(target));
     return true;
   }
   return false;
 }
 
-
 void FlowGraphAllocator::ConnectSplitSiblings(LiveRange* parent,
                                               BlockEntryInstr* source_block,
                                               BlockEntryInstr* target_block) {
   TRACE_ALLOC(THR_Print("Connect v%" Pd " on the edge B%" Pd " -> B%" Pd "\n",
                         parent->vreg(), source_block->block_id(),
                         target_block->block_id()));
   if (parent->next_sibling() == NULL) {
     // Nothing to connect. The whole range was allocated to the same location.
     TRACE_ALLOC(THR_Print("range v%" Pd " has no siblings\n", parent->vreg()));
     return;
@@ skipping 49 matching lines @@
 
   Instruction* last = source_block->last_instruction();
   if ((last->SuccessorCount() == 1) && !source_block->IsGraphEntry()) {
     ASSERT(last->IsGoto());
     last->AsGoto()->GetParallelMove()->AddMove(target, source);
   } else {
     target_block->GetParallelMove()->AddMove(target, source);
   }
 }
 
-
 void FlowGraphAllocator::ResolveControlFlow() {
   // Resolve linear control flow between touching split siblings
   // inside basic blocks.
   for (intptr_t vreg = 0; vreg < live_ranges_.length(); vreg++) {
     LiveRange* range = live_ranges_[vreg];
     if (range == NULL) continue;
 
     while (range->next_sibling() != NULL) {
       LiveRange* sibling = range->next_sibling();
       TRACE_ALLOC(THR_Print("connecting [%" Pd ", %" Pd ") [", range->Start(),
@@ skipping 35 matching lines @@
         range->assigned_location().IsDoubleStackSlot() ||
         range->assigned_location().IsConstant()) {
       ASSERT(range->assigned_location().Equals(range->spill_slot()));
     } else {
       AddMoveAt(range->Start() + 1, range->spill_slot(),
                 range->assigned_location());
     }
   }
 }
 
-
 static Representation RepresentationForRange(Representation definition_rep) {
   if (definition_rep == kUnboxedMint) {
     // kUnboxedMint is split into two ranges, each of which are kUntagged.
     return kUntagged;
   } else if (definition_rep == kUnboxedUint32) {
     // kUnboxedUint32 is untagged.
     return kUntagged;
   }
   return definition_rep;
 }
 
-
 void FlowGraphAllocator::CollectRepresentations() {
   // Parameters.
   GraphEntryInstr* graph_entry = flow_graph_.graph_entry();
   for (intptr_t i = 0; i < graph_entry->initial_definitions()->length(); ++i) {
     Definition* def = (*graph_entry->initial_definitions())[i];
     value_representations_[def->ssa_temp_index()] =
         RepresentationForRange(def->representation());
     ASSERT(!def->HasPairRepresentation());
   }
 
@@ skipping 36 matching lines @@
             RepresentationForRange(def->representation());
         if (def->HasPairRepresentation()) {
           value_representations_[ToSecondPairVreg(vreg)] =
               RepresentationForRange(def->representation());
         }
       }
     }
   }
 }
 
-
 void FlowGraphAllocator::AllocateRegisters() {
   CollectRepresentations();
 
   liveness_.Analyze();
 
   NumberInstructions();
 
   DiscoverLoops();
 
 #if defined(TARGET_ARCH_DBC)
@@ skipping 81 matching lines @@
     if (FLAG_support_il_printer) {
 #ifndef PRODUCT
       FlowGraphPrinter printer(flow_graph_, true);
       printer.PrintBlocks();
 #endif
     }
     THR_Print("----------------------------------------------\n");
   }
 }
 
-
 }  // namespace dart