VM: Re-format to use at most one newline between functions

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 #include "platform/assert.h"
 #include "vm/cpu.h"
@@ skipping 59 matching lines @@
   size_t remaining_size_in_buffer() { return buffer_size_ - buffer_pos_; }
 
   char* buffer_;        // Decode instructions into this buffer.
   size_t buffer_size_;  // The size of the character buffer.
   size_t buffer_pos_;   // Current character position in buffer.
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(ARMDecoder);
 };
 
-
 // Support for assertions in the ARMDecoder formatting functions.
 #define STRING_STARTS_WITH(string, compare_string)                             \
   (strncmp(string, compare_string, strlen(compare_string)) == 0)
 
-
 // Append the str to the output buffer.
 void ARMDecoder::Print(const char* str) {
   char cur = *str++;
   while (cur != '\0' && (buffer_pos_ < (buffer_size_ - 1))) {
     buffer_[buffer_pos_++] = cur;
     cur = *str++;
   }
   buffer_[buffer_pos_] = '\0';
 }
 
-
 // These condition names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* cond_names[kNumberOfConditions] = {
     "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
     "hi", "ls", "ge", "lt", "gt", "le", "",   "invalid",
 };
 
-
 // Print the condition guarding the instruction.
 void ARMDecoder::PrintCondition(Instr* instr) {
   Print(cond_names[instr->ConditionField()]);
 }
 
-
 // These register names are defined in a way to match the native disassembler
 // formatting, except for register alias pp (r5).
 // See for example the command "objdump -d <binary file>".
 static const char* reg_names[kNumberOfCpuRegisters] = {
 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
     "r0", "r1", "r2",  "r3",  "r4", "pp", "r6", "fp",
     "r8", "r9", "thr", "r11", "ip", "sp", "lr", "pc",
 #else
     "r0", "r1", "r2",  "r3", "r4", "pp", "r6", "r7",
     "r8", "r9", "thr", "fp", "ip", "sp", "lr", "pc",
 #endif
 };
 
-
 // Print the register name according to the active name converter.
 void ARMDecoder::PrintRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfCpuRegisters);
   Print(reg_names[reg]);
 }
 
-
 void ARMDecoder::PrintSRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfSRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                              remaining_size_in_buffer(), "s%d", reg);
 }
 
-
 void ARMDecoder::PrintDRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfDRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                              remaining_size_in_buffer(), "d%d", reg);
 }
 
-
 void ARMDecoder::PrintQRegister(int reg) {
   ASSERT(0 <= reg);
   ASSERT(reg < kNumberOfQRegisters);
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                              remaining_size_in_buffer(), "q%d", reg);
 }
 
-
 // These shift names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 static const char* shift_names[kMaxShift] = {"lsl", "lsr", "asr", "ror"};
 
-
 // Print the register shift operands for the instruction. Generally used for
 // data processing instructions.
 void ARMDecoder::PrintShiftRm(Instr* instr) {
   Shift shift = instr->ShiftField();
   int shift_amount = instr->ShiftAmountField();
   int rm = instr->RmField();
 
   PrintRegister(rm);
 
   if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) {
@@ skipping 14 matching lines @@
   } else {
     // by register
     int rs = instr->RsField();
     buffer_pos_ +=
         OS::SNPrint(current_position_in_buffer(), remaining_size_in_buffer(),
                     ", %s ", shift_names[shift]);
     PrintRegister(rs);
   }
 }
 
-
 // Print the immediate operand for the instruction. Generally used for data
 // processing instructions.
 void ARMDecoder::PrintShiftImm(Instr* instr) {
   int rotate = instr->RotateField() * 2;
   int immed8 = instr->Immed8Field();
   int imm = (immed8 >> rotate) | (immed8 << (32 - rotate));
   buffer_pos_ += OS::SNPrint(current_position_in_buffer(),
                              remaining_size_in_buffer(), "#%d", imm);
 }
 
-
 // Print PU formatting to reduce complexity of FormatOption.
 void ARMDecoder::PrintPU(Instr* instr) {
   switch (instr->PUField()) {
     case 0: {
       Print("da");
       break;
     }
     case 1: {
       Print("ia");
       break;
     }
     case 2: {
       Print("db");
       break;
     }
     case 3: {
       Print("ib");
       break;
     }
     default: {
       UNREACHABLE();
       break;
     }
   }
 }
 
-
 // Handle all register based formatting in these functions to reduce the
 // complexity of FormatOption.
 int ARMDecoder::FormatRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'r');
   if (format[1] == 'n') {  // 'rn: Rn register
     int reg = instr->RnField();
     PrintRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'rd: Rd register
     int reg = instr->RdField();
@@ skipping 35 matching lines @@
       reg++;
       rlist >>= 1;
     }
     Print("}");
     return 5;
   }
   UNREACHABLE();
   return -1;
 }
 
-
 int ARMDecoder::FormatSRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 's');
   if (format[1] == 'n') {  // 'sn: Sn register
     int reg = instr->SnField();
     PrintSRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'sd: Sd register
     int reg = instr->SdField();
     PrintSRegister(reg);
     return 2;
@@ skipping 19 matching lines @@
         Print(", ");
       }
     }
     Print("}");
     return 5;
   }
   UNREACHABLE();
   return -1;
 }
 
-
 void ARMDecoder::PrintDRegisterList(int start, int reg_count) {
   Print("{");
   for (int i = start; i < start + reg_count; i++) {
     PrintDRegister(i);
     if (i != start + reg_count - 1) {
       Print(", ");
     }
   }
   Print("}");
 }
 
-
 int ARMDecoder::FormatDRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'd');
   if (format[1] == 'n') {  // 'dn: Dn register
     int reg = instr->DnField();
     PrintDRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'dd: Dd register
     int reg = instr->DdField();
     PrintDRegister(reg);
     return 2;
@@ skipping 11 matching lines @@
     ASSERT(STRING_STARTS_WITH(format, "dtbllist"));
     int reg_count = instr->Bits(8, 2) + 1;
     int start = (instr->Bit(7) << 4) | instr->Bits(16, 4);
     PrintDRegisterList(start, reg_count);
     return 8;
   }
   UNREACHABLE();
   return -1;
 }
 
-
 int ARMDecoder::FormatQRegister(Instr* instr, const char* format) {
   ASSERT(format[0] == 'q');
   if (format[1] == 'n') {  // 'qn: Qn register
     int reg = instr->QnField();
     PrintQRegister(reg);
     return 2;
   } else if (format[1] == 'd') {  // 'qd: Qd register
     int reg = instr->QdField();
     PrintQRegister(reg);
     return 2;
   } else if (format[1] == 'm') {  // 'qm: Qm register
     int reg = instr->QmField();
     PrintQRegister(reg);
     return 2;
   }
   UNREACHABLE();
   return -1;
 }
 
-
 // FormatOption takes a formatting string and interprets it based on
 // the current instructions. The format string points to the first
 // character of the option string (the option escape has already been
 // consumed by the caller.)  FormatOption returns the number of
 // characters that were consumed from the formatting string.
 int ARMDecoder::FormatOption(Instr* instr, const char* format) {
   switch (format[0]) {
     case 'a': {  // 'a: accumulate multiplies
       if (instr->Bit(21) == 0) {
         Print("ul");
@@ skipping 211 matching lines @@
     }
     default: {
       UNREACHABLE();
       break;
     }
   }
   UNREACHABLE();
   return -1;
 }
 
-
 // Format takes a formatting string for a whole instruction and prints it into
 // the output buffer. All escaped options are handed to FormatOption to be
 // parsed further.
 void ARMDecoder::Format(Instr* instr, const char* format) {
   char cur = *format++;
   while ((cur != 0) && (buffer_pos_ < (buffer_size_ - 1))) {
     if (cur == '\'') {  // Single quote is used as the formatting escape.
       format += FormatOption(instr, format);
     } else {
       buffer_[buffer_pos_++] = cur;
     }
     cur = *format++;
   }
   buffer_[buffer_pos_] = '\0';
 }
 
-
 // For currently unimplemented decodings the disassembler calls Unknown(instr)
 // which will just print "unknown" of the instruction bits.
 void ARMDecoder::Unknown(Instr* instr) {
   Format(instr, "unknown");
 }
 
-
 void ARMDecoder::DecodeType01(Instr* instr) {
   if (!instr->IsDataProcessing()) {
     // miscellaneous, multiply, sync primitives, extra loads and stores.
     if (instr->IsMiscellaneous()) {
       switch (instr->Bits(4, 3)) {
         case 1: {
           if (instr->Bits(21, 2) == 0x3) {
             Format(instr, "clz'cond 'rd, 'rm");
           } else if (instr->Bits(21, 2) == 0x1) {
             Format(instr, "bx'cond 'rm");
@@ skipping 264 matching lines @@
       }
       default: {
         // The Opcode field is a 4-bit field.
         UNREACHABLE();
         break;
       }
     }
   }
 }
 
-
 void ARMDecoder::DecodeType2(Instr* instr) {
   switch (instr->PUField()) {
     case 0: {
       if (instr->HasW()) {
         Unknown(instr);  // Not used.
       } else {
         Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
       }
       break;
     }
@@ skipping 14 matching lines @@
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
 }
 
-
 void ARMDecoder::DecodeType3(Instr* instr) {
   if (instr->IsDivision()) {
     if (!TargetCPUFeatures::integer_division_supported()) {
       Unknown(instr);
       return;
     }
     if (instr->Bit(21)) {
       Format(instr, "udiv'cond 'rn, 'rs, 'rm");
     } else {
       Format(instr, "sdiv'cond 'rn, 'rs, 'rm");
@@ skipping 26 matching lines @@
       break;
     }
     default: {
       // The PU field is a 2-bit field.
       UNREACHABLE();
       break;
     }
   }
 }
 
-
 void ARMDecoder::DecodeType4(Instr* instr) {
   if (instr->Bit(22) == 1) {
     Unknown(instr);  // Privileged mode currently not supported.
   } else if (instr->HasL()) {
     Format(instr, "ldm'cond'pu 'rn'w, 'rlist");
   } else {
     Format(instr, "stm'cond'pu 'rn'w, 'rlist");
   }
 }
 
-
 void ARMDecoder::DecodeType5(Instr* instr) {
   Format(instr, "b'l'cond 'target ; 'dest");
 }
 
-
 void ARMDecoder::DecodeType6(Instr* instr) {
   if (instr->IsVFPDoubleTransfer()) {
     if (instr->Bit(8) == 0) {
       if (instr->Bit(20) == 1) {
         Format(instr, "vmovrrs'cond 'rd, 'rn, {'sm, 'sm1}");
       } else {
         Format(instr, "vmovsrr'cond {'sm, 'sm1}, 'rd, 'rn");
       }
     } else {
       if (instr->Bit(20) == 1) {
@@ skipping 44 matching lines @@
         Format(instr, "vstmd'cond'pu 'rn'w, 'dlist");
       } else {  // vstms
         Format(instr, "vstms'cond'pu 'rn'w, 'slist");
       }
     }
   } else {
     Unknown(instr);
   }
 }
 
-
 void ARMDecoder::DecodeType7(Instr* instr) {
   if (instr->Bit(24) == 1) {
     Format(instr, "svc'cond #'svc");
   } else if (instr->IsVFPDataProcessingOrSingleTransfer()) {
     if (instr->Bit(4) == 0) {
       // VFP Data Processing
       switch (instr->Bits(20, 4) & 0xb) {
         case 0: {  // vmla, vmls floating-point
           if (instr->Bit(8) == 0) {
             if (instr->Bit(6) == 0) {
@@ skipping 211 matching lines @@
         }
       } else {
         Unknown(instr);
       }
     }
   } else {
     Unknown(instr);
   }
 }
 
-
 void ARMDecoder::DecodeSIMDDataProcessing(Instr* instr) {
   ASSERT(instr->ConditionField() == kSpecialCondition);
   if (instr->Bit(6) == 1) {
     if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) &&
         (instr->Bits(23, 2) == 0)) {
       Format(instr, "vaddq'sz 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 0) &&
                (instr->Bits(23, 2) == 0) && (instr->Bit(21) == 0)) {
       Format(instr, "vaddqs 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 0) &&
@@ skipping 109 matching lines @@
   } else {
     if ((instr->Bits(23, 2) == 3) && (instr->Bits(20, 2) == 3) &&
         (instr->Bits(10, 2) == 2) && (instr->Bit(4) == 0)) {
       Format(instr, "vtbl 'dd, 'dtbllist, 'dm");
     } else {
       Unknown(instr);
     }
   }
 }
 
-
 void ARMDecoder::InstructionDecode(uword pc) {
   Instr* instr = Instr::At(pc);
 
   if (instr->ConditionField() == kSpecialCondition) {
     if ((instr->InstructionBits() == static_cast<int32_t>(0xf57ff01f)) &&
         (TargetCPUFeatures::arm_version() != ARMv5TE)) {
       Format(instr, "clrex");
     } else {
       if (instr->IsSIMDDataProcessing()) {
         DecodeSIMDDataProcessing(instr);
@@ skipping 34 matching lines @@
       }
       default: {
         // The type field is 3-bits in the ARM encoding.
         UNREACHABLE();
         break;
       }
     }
   }
 }
 
-
 void Disassembler::DecodeInstruction(char* hex_buffer,
                                      intptr_t hex_size,
                                      char* human_buffer,
                                      intptr_t human_size,
                                      int* out_instr_size,
                                      const Code& code,
                                      Object** object,
                                      uword pc) {
   ARMDecoder decoder(human_buffer, human_size);
   decoder.InstructionDecode(pc);
@@ skipping 10 matching lines @@
       *object = NULL;
     }
   }
 }
 
 #endif  // !PRODUCT
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM