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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #ifndef RUNTIME_VM_CONSTANTS_ARM_H_ | 5 #ifndef RUNTIME_VM_CONSTANTS_ARM_H_ |
6 #define RUNTIME_VM_CONSTANTS_ARM_H_ | 6 #define RUNTIME_VM_CONSTANTS_ARM_H_ |
7 | 7 |
| 8 #include "platform/assert.h" |
8 #include "platform/globals.h" | 9 #include "platform/globals.h" |
9 #include "platform/assert.h" | |
10 | 10 |
11 namespace dart { | 11 namespace dart { |
12 | 12 |
13 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at | 13 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at |
14 // a time. | 14 // a time. |
15 #if defined(__ARM_ARCH_7A__) | 15 #if defined(__ARM_ARCH_7A__) |
16 #define VFPv3_D32 | 16 #define VFPv3_D32 |
17 #elif defined(TARGET_ARCH_ARM) && !defined(HOST_ARCH_ARM) | 17 #elif defined(TARGET_ARCH_ARM) && !defined(HOST_ARCH_ARM) |
18 // If we're running in the simulator, use all 32. | 18 // If we're running in the simulator, use all 32. |
19 #define VFPv3_D32 | 19 #define VFPv3_D32 |
20 #else | 20 #else |
21 #define VFPv3_D16 | 21 #define VFPv3_D16 |
22 #endif | 22 #endif |
23 #if defined(VFPv3_D16) == defined(VFPv3_D32) | 23 #if defined(VFPv3_D16) == defined(VFPv3_D32) |
24 #error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time." | 24 #error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time." |
25 #endif | 25 #endif |
26 | 26 |
27 | |
28 // The Linux/Android ABI and the iOS ABI differ in their choice of frame | 27 // The Linux/Android ABI and the iOS ABI differ in their choice of frame |
29 // pointer, their treatment of R9, and the interprocedural stack alignment. | 28 // pointer, their treatment of R9, and the interprocedural stack alignment. |
30 | 29 |
31 // EABI (Linux, Android) | 30 // EABI (Linux, Android) |
32 // See "Procedure Call Standard for the ARM Architecture". | 31 // See "Procedure Call Standard for the ARM Architecture". |
33 // R0-R1: Argument / result / volatile | 32 // R0-R1: Argument / result / volatile |
34 // R2-R3: Argument / volatile | 33 // R2-R3: Argument / volatile |
35 // R4-R10: Preserved | 34 // R4-R10: Preserved |
36 // R11: Frame pointer | 35 // R11: Frame pointer |
37 // R12: Volatile | 36 // R12: Volatile |
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52 // R7: Frame pointer | 51 // R7: Frame pointer |
53 // R8-R9: Preserved | 52 // R8-R9: Preserved |
54 // R12: Volatile | 53 // R12: Volatile |
55 // R13: Stack pointer | 54 // R13: Stack pointer |
56 // R14: Link register | 55 // R14: Link register |
57 // R15: Program counter | 56 // R15: Program counter |
58 // Stack alignment: 4 bytes always, 4 bytes at public interfaces | 57 // Stack alignment: 4 bytes always, 4 bytes at public interfaces |
59 | 58 |
60 // iOS passes floating point arguments in registers (hardfp) | 59 // iOS passes floating point arguments in registers (hardfp) |
61 | 60 |
62 | |
63 enum Register { | 61 enum Register { |
64 R0 = 0, | 62 R0 = 0, |
65 R1 = 1, | 63 R1 = 1, |
66 R2 = 2, | 64 R2 = 2, |
67 R3 = 3, | 65 R3 = 3, |
68 R4 = 4, | 66 R4 = 4, |
69 R5 = 5, // PP | 67 R5 = 5, // PP |
70 R6 = 6, // CTX | 68 R6 = 6, // CTX |
71 R7 = 7, // iOS FP | 69 R7 = 7, // iOS FP |
72 R8 = 8, | 70 R8 = 8, |
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87 #else | 85 #else |
88 FP = R11, | 86 FP = R11, |
89 NOTFP = R7, | 87 NOTFP = R7, |
90 #endif | 88 #endif |
91 IP = R12, | 89 IP = R12, |
92 SP = R13, | 90 SP = R13, |
93 LR = R14, | 91 LR = R14, |
94 PC = R15, | 92 PC = R15, |
95 }; | 93 }; |
96 | 94 |
97 | |
98 // Values for single-precision floating point registers. | 95 // Values for single-precision floating point registers. |
99 enum SRegister { | 96 enum SRegister { |
100 kNoSRegister = -1, | 97 kNoSRegister = -1, |
101 S0 = 0, | 98 S0 = 0, |
102 S1 = 1, | 99 S1 = 1, |
103 S2 = 2, | 100 S2 = 2, |
104 S3 = 3, | 101 S3 = 3, |
105 S4 = 4, | 102 S4 = 4, |
106 S5 = 5, | 103 S5 = 5, |
107 S6 = 6, | 104 S6 = 6, |
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126 S25 = 25, | 123 S25 = 25, |
127 S26 = 26, | 124 S26 = 26, |
128 S27 = 27, | 125 S27 = 27, |
129 S28 = 28, | 126 S28 = 28, |
130 S29 = 29, | 127 S29 = 29, |
131 S30 = 30, | 128 S30 = 30, |
132 S31 = 31, | 129 S31 = 31, |
133 kNumberOfSRegisters = 32, | 130 kNumberOfSRegisters = 32, |
134 }; | 131 }; |
135 | 132 |
136 | |
137 // Values for double-precision floating point registers. | 133 // Values for double-precision floating point registers. |
138 enum DRegister { | 134 enum DRegister { |
139 kNoDRegister = -1, | 135 kNoDRegister = -1, |
140 D0 = 0, | 136 D0 = 0, |
141 D1 = 1, | 137 D1 = 1, |
142 D2 = 2, | 138 D2 = 2, |
143 D3 = 3, | 139 D3 = 3, |
144 D4 = 4, | 140 D4 = 4, |
145 D5 = 5, | 141 D5 = 5, |
146 D6 = 6, | 142 D6 = 6, |
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189 D27 = 27, | 185 D27 = 27, |
190 D28 = 28, | 186 D28 = 28, |
191 D29 = 29, | 187 D29 = 29, |
192 D30 = 30, | 188 D30 = 30, |
193 D31 = 31, | 189 D31 = 31, |
194 kNumberOfDRegisters = 32, | 190 kNumberOfDRegisters = 32, |
195 #endif | 191 #endif |
196 kNumberOfOverlappingDRegisters = 16, | 192 kNumberOfOverlappingDRegisters = 16, |
197 }; | 193 }; |
198 | 194 |
199 | |
200 enum QRegister { | 195 enum QRegister { |
201 kNoQRegister = -1, | 196 kNoQRegister = -1, |
202 Q0 = 0, | 197 Q0 = 0, |
203 Q1 = 1, | 198 Q1 = 1, |
204 Q2 = 2, | 199 Q2 = 2, |
205 Q3 = 3, | 200 Q3 = 3, |
206 Q4 = 4, | 201 Q4 = 4, |
207 Q5 = 5, | 202 Q5 = 5, |
208 Q6 = 6, | 203 Q6 = 6, |
209 Q7 = 7, | 204 Q7 = 7, |
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223 Q10 = 10, | 218 Q10 = 10, |
224 Q11 = 11, | 219 Q11 = 11, |
225 Q12 = 12, | 220 Q12 = 12, |
226 Q13 = 13, | 221 Q13 = 13, |
227 Q14 = 14, | 222 Q14 = 14, |
228 Q15 = 15, | 223 Q15 = 15, |
229 kNumberOfQRegisters = 16, | 224 kNumberOfQRegisters = 16, |
230 #endif | 225 #endif |
231 }; | 226 }; |
232 | 227 |
233 | |
234 static inline DRegister EvenDRegisterOf(QRegister q) { | 228 static inline DRegister EvenDRegisterOf(QRegister q) { |
235 return static_cast<DRegister>(q * 2); | 229 return static_cast<DRegister>(q * 2); |
236 } | 230 } |
237 | 231 |
238 static inline DRegister OddDRegisterOf(QRegister q) { | 232 static inline DRegister OddDRegisterOf(QRegister q) { |
239 return static_cast<DRegister>((q * 2) + 1); | 233 return static_cast<DRegister>((q * 2) + 1); |
240 } | 234 } |
241 | 235 |
242 | |
243 static inline SRegister EvenSRegisterOf(DRegister d) { | 236 static inline SRegister EvenSRegisterOf(DRegister d) { |
244 #if defined(VFPv3_D32) | 237 #if defined(VFPv3_D32) |
245 // When we have 32 D registers, the S registers only overlap the first 16. | 238 // When we have 32 D registers, the S registers only overlap the first 16. |
246 // That is, there are only 32 S registers. | 239 // That is, there are only 32 S registers. |
247 ASSERT(d < D16); | 240 ASSERT(d < D16); |
248 #endif | 241 #endif |
249 return static_cast<SRegister>(d * 2); | 242 return static_cast<SRegister>(d * 2); |
250 } | 243 } |
251 | 244 |
252 static inline SRegister OddSRegisterOf(DRegister d) { | 245 static inline SRegister OddSRegisterOf(DRegister d) { |
253 #if defined(VFPv3_D32) | 246 #if defined(VFPv3_D32) |
254 ASSERT(d < D16); | 247 ASSERT(d < D16); |
255 #endif | 248 #endif |
256 return static_cast<SRegister>((d * 2) + 1); | 249 return static_cast<SRegister>((d * 2) + 1); |
257 } | 250 } |
258 | 251 |
259 | |
260 // Register aliases for floating point scratch registers. | 252 // Register aliases for floating point scratch registers. |
261 const QRegister QTMP = Q7; // Overlaps with DTMP, STMP. | 253 const QRegister QTMP = Q7; // Overlaps with DTMP, STMP. |
262 const DRegister DTMP = EvenDRegisterOf(QTMP); // Overlaps with STMP. | 254 const DRegister DTMP = EvenDRegisterOf(QTMP); // Overlaps with STMP. |
263 const SRegister STMP DART_USED = EvenSRegisterOf(DTMP); | 255 const SRegister STMP DART_USED = EvenSRegisterOf(DTMP); |
264 | 256 |
265 // Architecture independent aliases. | 257 // Architecture independent aliases. |
266 typedef QRegister FpuRegister; | 258 typedef QRegister FpuRegister; |
267 | 259 |
268 const FpuRegister FpuTMP = QTMP; | 260 const FpuRegister FpuTMP = QTMP; |
269 const int kNumberOfFpuRegisters = kNumberOfQRegisters; | 261 const int kNumberOfFpuRegisters = kNumberOfQRegisters; |
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287 const Register APSR = R15; | 279 const Register APSR = R15; |
288 | 280 |
289 // Exception object is passed in this register to the catch handlers when an | 281 // Exception object is passed in this register to the catch handlers when an |
290 // exception is thrown. | 282 // exception is thrown. |
291 const Register kExceptionObjectReg = R0; | 283 const Register kExceptionObjectReg = R0; |
292 | 284 |
293 // Stack trace object is passed in this register to the catch handlers when | 285 // Stack trace object is passed in this register to the catch handlers when |
294 // an exception is thrown. | 286 // an exception is thrown. |
295 const Register kStackTraceObjectReg = R1; | 287 const Register kStackTraceObjectReg = R1; |
296 | 288 |
297 | |
298 // List of registers used in load/store multiple. | 289 // List of registers used in load/store multiple. |
299 typedef uint16_t RegList; | 290 typedef uint16_t RegList; |
300 const RegList kAllCpuRegistersList = 0xFFFF; | 291 const RegList kAllCpuRegistersList = 0xFFFF; |
301 | 292 |
302 | |
303 // C++ ABI call registers. | 293 // C++ ABI call registers. |
304 const RegList kAbiArgumentCpuRegs = | 294 const RegList kAbiArgumentCpuRegs = |
305 (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3); | 295 (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3); |
306 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS) | 296 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS) |
307 const RegList kAbiPreservedCpuRegs = | 297 const RegList kAbiPreservedCpuRegs = |
308 (1 << R4) | (1 << R5) | (1 << R6) | (1 << R8) | (1 << R10) | (1 << R11); | 298 (1 << R4) | (1 << R5) | (1 << R6) | (1 << R8) | (1 << R10) | (1 << R11); |
309 const int kAbiPreservedCpuRegCount = 6; | 299 const int kAbiPreservedCpuRegCount = 6; |
310 #else | 300 #else |
311 const RegList kAbiPreservedCpuRegs = (1 << R4) | (1 << R5) | (1 << R6) | | 301 const RegList kAbiPreservedCpuRegs = (1 << R4) | (1 << R5) | (1 << R6) | |
312 (1 << R7) | (1 << R8) | (1 << R9) | | 302 (1 << R7) | (1 << R8) | (1 << R9) | |
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327 kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs; | 317 kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs; |
328 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS) | 318 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS) |
329 const int kDartVolatileCpuRegCount = 6; | 319 const int kDartVolatileCpuRegCount = 6; |
330 #else | 320 #else |
331 const int kDartVolatileCpuRegCount = 5; | 321 const int kDartVolatileCpuRegCount = 5; |
332 #endif | 322 #endif |
333 const QRegister kDartFirstVolatileFpuReg = Q0; | 323 const QRegister kDartFirstVolatileFpuReg = Q0; |
334 const QRegister kDartLastVolatileFpuReg = Q3; | 324 const QRegister kDartLastVolatileFpuReg = Q3; |
335 const int kDartVolatileFpuRegCount = 4; | 325 const int kDartVolatileFpuRegCount = 4; |
336 | 326 |
337 | |
338 // Values for the condition field as defined in section A3.2. | 327 // Values for the condition field as defined in section A3.2. |
339 enum Condition { | 328 enum Condition { |
340 kNoCondition = -1, | 329 kNoCondition = -1, |
341 EQ = 0, // equal | 330 EQ = 0, // equal |
342 NE = 1, // not equal | 331 NE = 1, // not equal |
343 CS = 2, // carry set/unsigned higher or same | 332 CS = 2, // carry set/unsigned higher or same |
344 CC = 3, // carry clear/unsigned lower | 333 CC = 3, // carry clear/unsigned lower |
345 MI = 4, // minus/negative | 334 MI = 4, // minus/negative |
346 PL = 5, // plus/positive or zero | 335 PL = 5, // plus/positive or zero |
347 VS = 6, // overflow | 336 VS = 6, // overflow |
348 VC = 7, // no overflow | 337 VC = 7, // no overflow |
349 HI = 8, // unsigned higher | 338 HI = 8, // unsigned higher |
350 LS = 9, // unsigned lower or same | 339 LS = 9, // unsigned lower or same |
351 GE = 10, // signed greater than or equal | 340 GE = 10, // signed greater than or equal |
352 LT = 11, // signed less than | 341 LT = 11, // signed less than |
353 GT = 12, // signed greater than | 342 GT = 12, // signed greater than |
354 LE = 13, // signed less than or equal | 343 LE = 13, // signed less than or equal |
355 AL = 14, // always (unconditional) | 344 AL = 14, // always (unconditional) |
356 kSpecialCondition = 15, // special condition (refer to section A3.2.1) | 345 kSpecialCondition = 15, // special condition (refer to section A3.2.1) |
357 kNumberOfConditions = 16, | 346 kNumberOfConditions = 16, |
358 kInvalidCondition = 16 | 347 kInvalidCondition = 16 |
359 }; | 348 }; |
360 | 349 |
361 | |
362 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) | 350 // Opcodes for Data-processing instructions (instructions with a type 0 and 1) |
363 // as defined in section A3.4 | 351 // as defined in section A3.4 |
364 enum Opcode { | 352 enum Opcode { |
365 kNoOperand = -1, | 353 kNoOperand = -1, |
366 AND = 0, // Logical AND | 354 AND = 0, // Logical AND |
367 EOR = 1, // Logical Exclusive OR | 355 EOR = 1, // Logical Exclusive OR |
368 SUB = 2, // Subtract | 356 SUB = 2, // Subtract |
369 RSB = 3, // Reverse Subtract | 357 RSB = 3, // Reverse Subtract |
370 ADD = 4, // Add | 358 ADD = 4, // Add |
371 ADC = 5, // Add with Carry | 359 ADC = 5, // Add with Carry |
372 SBC = 6, // Subtract with Carry | 360 SBC = 6, // Subtract with Carry |
373 RSC = 7, // Reverse Subtract with Carry | 361 RSC = 7, // Reverse Subtract with Carry |
374 TST = 8, // Test | 362 TST = 8, // Test |
375 TEQ = 9, // Test Equivalence | 363 TEQ = 9, // Test Equivalence |
376 CMP = 10, // Compare | 364 CMP = 10, // Compare |
377 CMN = 11, // Compare Negated | 365 CMN = 11, // Compare Negated |
378 ORR = 12, // Logical (inclusive) OR | 366 ORR = 12, // Logical (inclusive) OR |
379 MOV = 13, // Move | 367 MOV = 13, // Move |
380 BIC = 14, // Bit Clear | 368 BIC = 14, // Bit Clear |
381 MVN = 15, // Move Not | 369 MVN = 15, // Move Not |
382 kMaxOperand = 16 | 370 kMaxOperand = 16 |
383 }; | 371 }; |
384 | 372 |
385 | |
386 // Shifter types for Data-processing operands as defined in section A5.1.2. | 373 // Shifter types for Data-processing operands as defined in section A5.1.2. |
387 enum Shift { | 374 enum Shift { |
388 kNoShift = -1, | 375 kNoShift = -1, |
389 LSL = 0, // Logical shift left | 376 LSL = 0, // Logical shift left |
390 LSR = 1, // Logical shift right | 377 LSR = 1, // Logical shift right |
391 ASR = 2, // Arithmetic shift right | 378 ASR = 2, // Arithmetic shift right |
392 ROR = 3, // Rotate right | 379 ROR = 3, // Rotate right |
393 kMaxShift = 4 | 380 kMaxShift = 4 |
394 }; | 381 }; |
395 | 382 |
396 | |
397 // Constants used for the decoding or encoding of the individual fields of | 383 // Constants used for the decoding or encoding of the individual fields of |
398 // instructions. Based on the "Figure 3-1 ARM instruction set summary". | 384 // instructions. Based on the "Figure 3-1 ARM instruction set summary". |
399 enum InstructionFields { | 385 enum InstructionFields { |
400 kConditionShift = 28, | 386 kConditionShift = 28, |
401 kConditionBits = 4, | 387 kConditionBits = 4, |
402 kTypeShift = 25, | 388 kTypeShift = 25, |
403 kTypeBits = 3, | 389 kTypeBits = 3, |
404 kLinkShift = 24, | 390 kLinkShift = 24, |
405 kLinkBits = 1, | 391 kLinkBits = 1, |
406 kUShift = 23, | 392 kUShift = 23, |
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465 kCoprocShift = 8, | 451 kCoprocShift = 8, |
466 kCoprocBits = 4, | 452 kCoprocBits = 4, |
467 kCRnShift = 16, | 453 kCRnShift = 16, |
468 kCRnBits = 4, | 454 kCRnBits = 4, |
469 kOpc1Shift = 21, | 455 kOpc1Shift = 21, |
470 kOpc1Bits = 3, | 456 kOpc1Bits = 3, |
471 | 457 |
472 kBranchOffsetMask = 0x00ffffff | 458 kBranchOffsetMask = 0x00ffffff |
473 }; | 459 }; |
474 | 460 |
475 | |
476 // The class Instr enables access to individual fields defined in the ARM | 461 // The class Instr enables access to individual fields defined in the ARM |
477 // architecture instruction set encoding as described in figure A3-1. | 462 // architecture instruction set encoding as described in figure A3-1. |
478 // | 463 // |
479 // Example: Test whether the instruction at ptr sets the condition code bits. | 464 // Example: Test whether the instruction at ptr sets the condition code bits. |
480 // | 465 // |
481 // bool InstructionSetsConditionCodes(byte* ptr) { | 466 // bool InstructionSetsConditionCodes(byte* ptr) { |
482 // Instr* instr = Instr::At(ptr); | 467 // Instr* instr = Instr::At(ptr); |
483 // int type = instr->TypeField(); | 468 // int type = instr->TypeField(); |
484 // return ((type == 0) || (type == 1)) && instr->HasS(); | 469 // return ((type == 0) || (type == 1)) && instr->HasS(); |
485 // } | 470 // } |
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522 } | 507 } |
523 | 508 |
524 // Read one particular bit out of the instruction bits. | 509 // Read one particular bit out of the instruction bits. |
525 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } | 510 inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } |
526 | 511 |
527 // Read a bit field out of the instruction bits. | 512 // Read a bit field out of the instruction bits. |
528 inline int Bits(int shift, int count) const { | 513 inline int Bits(int shift, int count) const { |
529 return (InstructionBits() >> shift) & ((1 << count) - 1); | 514 return (InstructionBits() >> shift) & ((1 << count) - 1); |
530 } | 515 } |
531 | 516 |
532 | |
533 // Accessors for the different named fields used in the ARM encoding. | 517 // Accessors for the different named fields used in the ARM encoding. |
534 // The naming of these accessor corresponds to figure A3-1. | 518 // The naming of these accessor corresponds to figure A3-1. |
535 // Generally applicable fields | 519 // Generally applicable fields |
536 inline Condition ConditionField() const { | 520 inline Condition ConditionField() const { |
537 return static_cast<Condition>(Bits(kConditionShift, kConditionBits)); | 521 return static_cast<Condition>(Bits(kConditionShift, kConditionBits)); |
538 } | 522 } |
539 inline int TypeField() const { return Bits(kTypeShift, kTypeBits); } | 523 inline int TypeField() const { return Bits(kTypeShift, kTypeBits); } |
540 | 524 |
541 inline Register RnField() const { | 525 inline Register RnField() const { |
542 return static_cast<Register>(Bits(kRnShift, kRnBits)); | 526 return static_cast<Register>(Bits(kRnShift, kRnBits)); |
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758 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } | 742 static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); } |
759 | 743 |
760 private: | 744 private: |
761 DISALLOW_ALLOCATION(); | 745 DISALLOW_ALLOCATION(); |
762 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); | 746 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); |
763 }; | 747 }; |
764 | 748 |
765 } // namespace dart | 749 } // namespace dart |
766 | 750 |
767 #endif // RUNTIME_VM_CONSTANTS_ARM_H_ | 751 #endif // RUNTIME_VM_CONSTANTS_ARM_H_ |
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