VM: Re-format to use at most one newline between functions

runtime/vm/constants_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef RUNTIME_VM_CONSTANTS_ARM_H_
 #define RUNTIME_VM_CONSTANTS_ARM_H_
 
+#include "platform/assert.h"
 #include "platform/globals.h"
-#include "platform/assert.h"
 
 namespace dart {
 
 // We support both VFPv3-D16 and VFPv3-D32 profiles, but currently only one at
 // a time.
 #if defined(__ARM_ARCH_7A__)
 #define VFPv3_D32
 #elif defined(TARGET_ARCH_ARM) && !defined(HOST_ARCH_ARM)
 // If we're running in the simulator, use all 32.
 #define VFPv3_D32
 #else
 #define VFPv3_D16
 #endif
 #if defined(VFPv3_D16) == defined(VFPv3_D32)
 #error "Exactly one of VFPv3_D16 or VFPv3_D32 can be defined at a time."
 #endif
 
-
 // The Linux/Android ABI and the iOS ABI differ in their choice of frame
 // pointer, their treatment of R9, and the interprocedural stack alignment.
 
 // EABI (Linux, Android)
 // See "Procedure Call Standard for the ARM Architecture".
 // R0-R1:  Argument / result / volatile
 // R2-R3:  Argument / volatile
 // R4-R10: Preserved
 // R11:    Frame pointer
 // R12:    Volatile
@@ skipping 14 matching lines @@
 // R7:    Frame pointer
 // R8-R9: Preserved
 // R12:   Volatile
 // R13:   Stack pointer
 // R14:   Link register
 // R15:   Program counter
 // Stack alignment: 4 bytes always, 4 bytes at public interfaces
 
 // iOS passes floating point arguments in registers (hardfp)
 
-
 enum Register {
   R0 = 0,
   R1 = 1,
   R2 = 2,
   R3 = 3,
   R4 = 4,
   R5 = 5,  // PP
   R6 = 6,  // CTX
   R7 = 7,  // iOS FP
   R8 = 8,
@@ skipping 14 matching lines @@
 #else
   FP = R11,
   NOTFP = R7,
 #endif
   IP = R12,
   SP = R13,
   LR = R14,
   PC = R15,
 };
 
-
 // Values for single-precision floating point registers.
 enum SRegister {
   kNoSRegister = -1,
   S0 = 0,
   S1 = 1,
   S2 = 2,
   S3 = 3,
   S4 = 4,
   S5 = 5,
   S6 = 6,
@@ skipping 18 matching lines @@
   S25 = 25,
   S26 = 26,
   S27 = 27,
   S28 = 28,
   S29 = 29,
   S30 = 30,
   S31 = 31,
   kNumberOfSRegisters = 32,
 };
 
-
 // Values for double-precision floating point registers.
 enum DRegister {
   kNoDRegister = -1,
   D0 = 0,
   D1 = 1,
   D2 = 2,
   D3 = 3,
   D4 = 4,
   D5 = 5,
   D6 = 6,
@@ skipping 42 matching lines @@
   D27 = 27,
   D28 = 28,
   D29 = 29,
   D30 = 30,
   D31 = 31,
   kNumberOfDRegisters = 32,
 #endif
   kNumberOfOverlappingDRegisters = 16,
 };
 
-
 enum QRegister {
   kNoQRegister = -1,
   Q0 = 0,
   Q1 = 1,
   Q2 = 2,
   Q3 = 3,
   Q4 = 4,
   Q5 = 5,
   Q6 = 6,
   Q7 = 7,
@@ skipping 13 matching lines @@
   Q10 = 10,
   Q11 = 11,
   Q12 = 12,
   Q13 = 13,
   Q14 = 14,
   Q15 = 15,
   kNumberOfQRegisters = 16,
 #endif
 };
 
-
 static inline DRegister EvenDRegisterOf(QRegister q) {
   return static_cast<DRegister>(q * 2);
 }
 
 static inline DRegister OddDRegisterOf(QRegister q) {
   return static_cast<DRegister>((q * 2) + 1);
 }
 
-
 static inline SRegister EvenSRegisterOf(DRegister d) {
 #if defined(VFPv3_D32)
   // When we have 32 D registers, the S registers only overlap the first 16.
   // That is, there are only 32 S registers.
   ASSERT(d < D16);
 #endif
   return static_cast<SRegister>(d * 2);
 }
 
 static inline SRegister OddSRegisterOf(DRegister d) {
 #if defined(VFPv3_D32)
   ASSERT(d < D16);
 #endif
   return static_cast<SRegister>((d * 2) + 1);
 }
 
-
 // Register aliases for floating point scratch registers.
 const QRegister QTMP = Q7;                     // Overlaps with DTMP, STMP.
 const DRegister DTMP = EvenDRegisterOf(QTMP);  // Overlaps with STMP.
 const SRegister STMP DART_USED = EvenSRegisterOf(DTMP);
 
 // Architecture independent aliases.
 typedef QRegister FpuRegister;
 
 const FpuRegister FpuTMP = QTMP;
 const int kNumberOfFpuRegisters = kNumberOfQRegisters;
@@ skipping 17 matching lines @@
 const Register APSR = R15;
 
 // Exception object is passed in this register to the catch handlers when an
 // exception is thrown.
 const Register kExceptionObjectReg = R0;
 
 // Stack trace object is passed in this register to the catch handlers when
 // an exception is thrown.
 const Register kStackTraceObjectReg = R1;
 
-
 // List of registers used in load/store multiple.
 typedef uint16_t RegList;
 const RegList kAllCpuRegistersList = 0xFFFF;
 
-
 // C++ ABI call registers.
 const RegList kAbiArgumentCpuRegs =
     (1 << R0) | (1 << R1) | (1 << R2) | (1 << R3);
 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
 const RegList kAbiPreservedCpuRegs =
     (1 << R4) | (1 << R5) | (1 << R6) | (1 << R8) | (1 << R10) | (1 << R11);
 const int kAbiPreservedCpuRegCount = 6;
 #else
 const RegList kAbiPreservedCpuRegs = (1 << R4) | (1 << R5) | (1 << R6) |
                                      (1 << R7) | (1 << R8) | (1 << R9) |
@@ skipping 14 matching lines @@
     kDartAvailableCpuRegs & ~kAbiPreservedCpuRegs;
 #if defined(TARGET_OS_MACOS) || defined(TARGET_OS_MACOS_IOS)
 const int kDartVolatileCpuRegCount = 6;
 #else
 const int kDartVolatileCpuRegCount = 5;
 #endif
 const QRegister kDartFirstVolatileFpuReg = Q0;
 const QRegister kDartLastVolatileFpuReg = Q3;
 const int kDartVolatileFpuRegCount = 4;
 
-
 // Values for the condition field as defined in section A3.2.
 enum Condition {
   kNoCondition = -1,
   EQ = 0,                  // equal
   NE = 1,                  // not equal
   CS = 2,                  // carry set/unsigned higher or same
   CC = 3,                  // carry clear/unsigned lower
   MI = 4,                  // minus/negative
   PL = 5,                  // plus/positive or zero
   VS = 6,                  // overflow
   VC = 7,                  // no overflow
   HI = 8,                  // unsigned higher
   LS = 9,                  // unsigned lower or same
   GE = 10,                 // signed greater than or equal
   LT = 11,                 // signed less than
   GT = 12,                 // signed greater than
   LE = 13,                 // signed less than or equal
   AL = 14,                 // always (unconditional)
   kSpecialCondition = 15,  // special condition (refer to section A3.2.1)
   kNumberOfConditions = 16,
   kInvalidCondition = 16
 };
 
-
 // Opcodes for Data-processing instructions (instructions with a type 0 and 1)
 // as defined in section A3.4
 enum Opcode {
   kNoOperand = -1,
   AND = 0,   // Logical AND
   EOR = 1,   // Logical Exclusive OR
   SUB = 2,   // Subtract
   RSB = 3,   // Reverse Subtract
   ADD = 4,   // Add
   ADC = 5,   // Add with Carry
   SBC = 6,   // Subtract with Carry
   RSC = 7,   // Reverse Subtract with Carry
   TST = 8,   // Test
   TEQ = 9,   // Test Equivalence
   CMP = 10,  // Compare
   CMN = 11,  // Compare Negated
   ORR = 12,  // Logical (inclusive) OR
   MOV = 13,  // Move
   BIC = 14,  // Bit Clear
   MVN = 15,  // Move Not
   kMaxOperand = 16
 };
 
-
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 enum Shift {
   kNoShift = -1,
   LSL = 0,  // Logical shift left
   LSR = 1,  // Logical shift right
   ASR = 2,  // Arithmetic shift right
   ROR = 3,  // Rotate right
   kMaxShift = 4
 };
 
-
 // Constants used for the decoding or encoding of the individual fields of
 // instructions. Based on the "Figure 3-1 ARM instruction set summary".
 enum InstructionFields {
   kConditionShift = 28,
   kConditionBits = 4,
   kTypeShift = 25,
   kTypeBits = 3,
   kLinkShift = 24,
   kLinkBits = 1,
   kUShift = 23,
@@ skipping 58 matching lines @@
   kCoprocShift = 8,
   kCoprocBits = 4,
   kCRnShift = 16,
   kCRnBits = 4,
   kOpc1Shift = 21,
   kOpc1Bits = 3,
 
   kBranchOffsetMask = 0x00ffffff
 };
 
-
 // The class Instr enables access to individual fields defined in the ARM
 // architecture instruction set encoding as described in figure A3-1.
 //
 // Example: Test whether the instruction at ptr sets the condition code bits.
 //
 // bool InstructionSetsConditionCodes(byte* ptr) {
 //   Instr* instr = Instr::At(ptr);
 //   int type = instr->TypeField();
 //   return ((type == 0) || (type == 1)) && instr->HasS();
 // }
@@ skipping 36 matching lines @@
   }
 
   // Read one particular bit out of the instruction bits.
   inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
 
   // Read a bit field out of the instruction bits.
   inline int Bits(int shift, int count) const {
     return (InstructionBits() >> shift) & ((1 << count) - 1);
   }
 
-
   // Accessors for the different named fields used in the ARM encoding.
   // The naming of these accessor corresponds to figure A3-1.
   // Generally applicable fields
   inline Condition ConditionField() const {
     return static_cast<Condition>(Bits(kConditionShift, kConditionBits));
   }
   inline int TypeField() const { return Bits(kTypeShift, kTypeBits); }
 
   inline Register RnField() const {
     return static_cast<Register>(Bits(kRnShift, kRnBits));
@@ skipping 215 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // RUNTIME_VM_CONSTANTS_ARM_H_