Rename ShifterOperand to Operand on ARM.

runtime/vm/instructions_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/constants_arm.h"
 #include "vm/cpu.h"
@@ skipping 122 matching lines @@
   int32_t instr = Instr::At(start)->InstructionBits();
   intptr_t offset = 0;
   if ((instr & 0xffff0000) == 0xe59a0000) {  // ldr reg, [pp, #+offset]
     offset = instr & 0xfff;
     *reg = static_cast<Register>((instr & 0xf000) >> 12);
   } else {
     ASSERT((instr & 0xfff00000) == 0xe5900000);  // ldr reg, [reg, #+offset]
     offset = instr & 0xfff;
     start -= Instr::kInstrSize;
     instr = Instr::At(start)->InstructionBits();
-    if ((instr & 0xffff0000) == 0xe28a0000) {  // add reg, pp, shifter_op
+    if ((instr & 0xffff0000) == 0xe28a0000) {  // add reg, pp, operand
       const intptr_t rot = (instr & 0xf00) >> 7;
       const intptr_t imm8 = instr & 0xff;
       offset += (imm8 >> rot) | (imm8 << (32 - rot));
       *reg = static_cast<Register>((instr & 0xf000) >> 12);
     } else {
       ASSERT((instr & 0xffff0000) == 0xe08a0000);  // add reg, pp, reg
       end = DecodeLoadWordImmediate(end, reg, &offset);
     }
   }
   offset += kHeapObjectTag;
@@ skipping 186 matching lines @@
 
     *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip;
     *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip;
     CPU::FlushICache(pc_, 2 * Instr::kInstrSize);
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM