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Issue 297163012: Rename ShifterOperand to Operand on ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 6 years, 6 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/constants_arm.h" 9 #include "vm/constants_arm.h"
10 #include "vm/cpu.h" 10 #include "vm/cpu.h"
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133 int32_t instr = Instr::At(start)->InstructionBits(); 133 int32_t instr = Instr::At(start)->InstructionBits();
134 intptr_t offset = 0; 134 intptr_t offset = 0;
135 if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset] 135 if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset]
136 offset = instr & 0xfff; 136 offset = instr & 0xfff;
137 *reg = static_cast<Register>((instr & 0xf000) >> 12); 137 *reg = static_cast<Register>((instr & 0xf000) >> 12);
138 } else { 138 } else {
139 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset] 139 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset]
140 offset = instr & 0xfff; 140 offset = instr & 0xfff;
141 start -= Instr::kInstrSize; 141 start -= Instr::kInstrSize;
142 instr = Instr::At(start)->InstructionBits(); 142 instr = Instr::At(start)->InstructionBits();
143 if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, shifter_op 143 if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, operand
144 const intptr_t rot = (instr & 0xf00) >> 7; 144 const intptr_t rot = (instr & 0xf00) >> 7;
145 const intptr_t imm8 = instr & 0xff; 145 const intptr_t imm8 = instr & 0xff;
146 offset += (imm8 >> rot) | (imm8 << (32 - rot)); 146 offset += (imm8 >> rot) | (imm8 << (32 - rot));
147 *reg = static_cast<Register>((instr & 0xf000) >> 12); 147 *reg = static_cast<Register>((instr & 0xf000) >> 12);
148 } else { 148 } else {
149 ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg 149 ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg
150 end = DecodeLoadWordImmediate(end, reg, &offset); 150 end = DecodeLoadWordImmediate(end, reg, &offset);
151 } 151 }
152 } 152 }
153 offset += kHeapObjectTag; 153 offset += kHeapObjectTag;
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340 340
341 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip; 341 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip;
342 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip; 342 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip;
343 CPU::FlushICache(pc_, 2 * Instr::kInstrSize); 343 CPU::FlushICache(pc_, 2 * Instr::kInstrSize);
344 } 344 }
345 } 345 }
346 346
347 } // namespace dart 347 } // namespace dart
348 348
349 #endif // defined TARGET_ARCH_ARM 349 #endif // defined TARGET_ARCH_ARM
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