Rename ShifterOperand to Operand on ARM.

runtime/vm/assembler_arm.h

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM_H_
 #define VM_ASSEMBLER_ARM_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm.h directly; use assembler.h instead.
 #endif
@@ skipping 47 matching lines @@
     position_ = position + kWordSize;
     ASSERT(IsLinked());
   }
 
   friend class Assembler;
   DISALLOW_COPY_AND_ASSIGN(Label);
 };
 
 
 // Encodes Addressing Mode 1 - Data-processing operands.
-// TODO(regis): rename ShifterOperand to Operand.
-class ShifterOperand : public ValueObject {
+class Operand : public ValueObject {
  public:
   // Data-processing operands - Uninitialized.
-  ShifterOperand() : type_(-1), encoding_(-1) { }
+  Operand() : type_(-1), encoding_(-1) { }
 
   // Data-processing operands - Copy constructor.
-  ShifterOperand(const ShifterOperand& other)
+  Operand(const Operand& other)
       : ValueObject(), type_(other.type_), encoding_(other.encoding_) { }
 
   // Data-processing operands - Assignment operator.
-  ShifterOperand& operator=(const ShifterOperand& other) {
+  Operand& operator=(const Operand& other) {
     type_ = other.type_;
     encoding_ = other.encoding_;
     return *this;
   }
 
   // Data-processing operands - Immediate.
-  explicit ShifterOperand(uint32_t immediate) {
+  explicit Operand(uint32_t immediate) {
     ASSERT(immediate < (1 << kImmed8Bits));
     type_ = 1;
     encoding_ = immediate;
   }
 
   // Data-processing operands - Rotated immediate.
-  ShifterOperand(uint32_t rotate, uint32_t immed8) {
+  Operand(uint32_t rotate, uint32_t immed8) {
     ASSERT((rotate < (1 << kRotateBits)) && (immed8 < (1 << kImmed8Bits)));
     type_ = 1;
     encoding_ = (rotate << kRotateShift) | (immed8 << kImmed8Shift);
   }
 
   // Data-processing operands - Register.
-  explicit ShifterOperand(Register rm) {
+  explicit Operand(Register rm) {
     type_ = 0;
     encoding_ = static_cast<uint32_t>(rm);
   }
 
   // Data-processing operands - Logical shift/rotate by immediate.
-  ShifterOperand(Register rm, Shift shift, uint32_t shift_imm) {
+  Operand(Register rm, Shift shift, uint32_t shift_imm) {
     ASSERT(shift_imm < (1 << kShiftImmBits));
     type_ = 0;
     encoding_ = shift_imm << kShiftImmShift |
                 static_cast<uint32_t>(shift) << kShiftShift |
                 static_cast<uint32_t>(rm);
   }
 
   // Data-processing operands - Logical shift/rotate by register.
-  ShifterOperand(Register rm, Shift shift, Register rs) {
+  Operand(Register rm, Shift shift, Register rs) {
     type_ = 0;
     encoding_ = static_cast<uint32_t>(rs) << kShiftRegisterShift |
                 static_cast<uint32_t>(shift) << kShiftShift | (1 << 4) |
                 static_cast<uint32_t>(rm);
   }
 
-  static bool CanHold(uint32_t immediate, ShifterOperand* shifter_op) {
+  static bool CanHold(uint32_t immediate, Operand* o) {
     // Avoid the more expensive test for frequent small immediate values.
     if (immediate < (1 << kImmed8Bits)) {
-      shifter_op->type_ = 1;
-      shifter_op->encoding_ = (0 << kRotateShift) | (immediate << kImmed8Shift);
+      o->type_ = 1;
+      o->encoding_ = (0 << kRotateShift) | (immediate << kImmed8Shift);
       return true;
     }
     // Note that immediate must be unsigned for the test to work correctly.
     for (int rot = 0; rot < 16; rot++) {
       uint32_t imm8 = (immediate << 2*rot) | (immediate >> (32 - 2*rot));
       if (imm8 < (1 << kImmed8Bits)) {
-        shifter_op->type_ = 1;
-        shifter_op->encoding_ = (rot << kRotateShift) | (imm8 << kImmed8Shift);
+        o->type_ = 1;
+        o->encoding_ = (rot << kRotateShift) | (imm8 << kImmed8Shift);
         return true;
       }
     }
     return false;
   }
 
  private:
   bool is_valid() const { return (type_ == 0) || (type_ == 1); }
 
   uint32_t type() const {
@@ skipping 81 matching lines @@
     if (offset < 0) {
       encoding_ = (am ^ (1 << kUShift)) | -offset;  // Flip U to adjust sign.
     } else {
       encoding_ = am | offset;
     }
     encoding_ |= static_cast<uint32_t>(rn) << kRnShift;
   }
 
   Address(Register rn, Register rm,
           Shift shift = LSL, uint32_t shift_imm = 0, Mode am = Offset) {
-    ShifterOperand so(rm, shift, shift_imm);
+    Operand o(rm, shift, shift_imm);
 
     if ((shift == LSL) && (shift_imm == 0)) {
       kind_ = IndexRegister;
     } else {
       kind_ = ScaledIndexRegister;
     }
-    encoding_ = so.encoding() | am | (static_cast<uint32_t>(rn) << kRnShift);
+    encoding_ = o.encoding() | am | (static_cast<uint32_t>(rn) << kRnShift);
   }
 
   static OperandSize OperandSizeFor(intptr_t cid);
 
   static bool CanHoldLoadOffset(OperandSize size,
                                 int32_t offset,
                                 int32_t* offset_mask);
   static bool CanHoldStoreOffset(OperandSize size,
                                  int32_t offset,
                                  int32_t* offset_mask);
@@ skipping 82 matching lines @@
 
   void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
 
   const Code::Comments& GetCodeComments() const;
 
   static const char* RegisterName(Register reg);
 
   static const char* FpuRegisterName(FpuRegister reg);
 
   // Data-processing instructions.
-  void and_(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void and_(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void eor(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void eor(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void sub(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
-  void subs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void sub(Register rd, Register rn, Operand o, Condition cond = AL);
+  void subs(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void rsb(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
-  void rsbs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void rsb(Register rd, Register rn, Operand o, Condition cond = AL);
+  void rsbs(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void add(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void add(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void adds(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void adds(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void adc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void adc(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void adcs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void adcs(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void sbc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void sbc(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void sbcs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void sbcs(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void rsc(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void rsc(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void tst(Register rn, ShifterOperand so, Condition cond = AL);
+  void tst(Register rn, Operand o, Condition cond = AL);
 
-  void teq(Register rn, ShifterOperand so, Condition cond = AL);
+  void teq(Register rn, Operand o, Condition cond = AL);
 
-  void cmp(Register rn, ShifterOperand so, Condition cond = AL);
+  void cmp(Register rn, Operand o, Condition cond = AL);
 
-  void cmn(Register rn, ShifterOperand so, Condition cond = AL);
+  void cmn(Register rn, Operand o, Condition cond = AL);
 
-  void orr(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
-  void orrs(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void orr(Register rd, Register rn, Operand o, Condition cond = AL);
+  void orrs(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void mov(Register rd, ShifterOperand so, Condition cond = AL);
-  void movs(Register rd, ShifterOperand so, Condition cond = AL);
+  void mov(Register rd, Operand o, Condition cond = AL);
+  void movs(Register rd, Operand o, Condition cond = AL);
 
-  void bic(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
-  void bics(Register rd, Register rn, ShifterOperand so, Condition cond = AL);
+  void bic(Register rd, Register rn, Operand o, Condition cond = AL);
+  void bics(Register rd, Register rn, Operand o, Condition cond = AL);
 
-  void mvn(Register rd, ShifterOperand so, Condition cond = AL);
-  void mvns(Register rd, ShifterOperand so, Condition cond = AL);
+  void mvn(Register rd, Operand o, Condition cond = AL);
+  void mvns(Register rd, Operand o, Condition cond = AL);
 
   // Miscellaneous data-processing instructions.
   void clz(Register rd, Register rm, Condition cond = AL);
   void movw(Register rd, uint16_t imm16, Condition cond = AL);
   void movt(Register rd, uint16_t imm16, Condition cond = AL);
 
   // Multiply instructions.
   void mul(Register rd, Register rn, Register rm, Condition cond = AL);
   void muls(Register rd, Register rn, Register rm, Condition cond = AL);
   void mla(Register rd, Register rn, Register rm, Register ra,
@@ skipping 414 matching lines @@
   };
 
   GrowableArray<CodeComment*> comments_;
 
   void EmitType01(Condition cond,
                   int type,
                   Opcode opcode,
                   int set_cc,
                   Register rn,
                   Register rd,
-                  ShifterOperand so);
+                  Operand o);
 
   void EmitType5(Condition cond, int32_t offset, bool link);
 
   void EmitMemOp(Condition cond,
                  bool load,
                  bool byte,
                  Register rd,
                  Address ad);
 
   void EmitMemOpAddressMode3(Condition cond,
                              int32_t mode,
                              Register rd,
                              Address ad);
 
   void EmitMultiMemOp(Condition cond,
                       BlockAddressMode am,
                       bool load,
                       Register base,
                       RegList regs);
 
   void EmitShiftImmediate(Condition cond,
                           Shift opcode,
                           Register rd,
                           Register rm,
-                          ShifterOperand so);
+                          Operand o);
 
   void EmitShiftRegister(Condition cond,
                          Shift opcode,
                          Register rd,
                          Register rm,
-                         ShifterOperand so);
+                         Operand o);
 
   void EmitMulOp(Condition cond,
                  int32_t opcode,
                  Register rd,
                  Register rn,
                  Register rm,
                  Register rs);
 
   void EmitDivOp(Condition cond,
                  int32_t opcode,
@@ skipping 57 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM_H_