Rename ShifterOperand to Operand on ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/cpu.h"
 #include "vm/longjump.h"
@@ skipping 97 matching lines @@
   buffer_.Emit<int32_t>(value);
 }
 
 
 void Assembler::EmitType01(Condition cond,
                            int type,
                            Opcode opcode,
                            int set_cc,
                            Register rn,
                            Register rd,
-                           ShifterOperand so) {
+                           Operand o) {
   ASSERT(rd != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      type << kTypeShift |
                      static_cast<int32_t>(opcode) << kOpcodeShift |
                      set_cc << kSShift |
                      static_cast<int32_t>(rn) << kRnShift |
                      static_cast<int32_t>(rd) << kRdShift |
-                     so.encoding();
+                     o.encoding();
   Emit(encoding);
 }
 
 
 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
   ASSERT(cond != kNoCondition);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      5 << kTypeShift |
                      (link ? 1 : 0) << kLinkShift;
   Emit(Assembler::EncodeBranchOffset(offset, encoding));
@@ skipping 45 matching lines @@
                      (static_cast<int32_t>(base) << kRnShift) |
                      regs;
   Emit(encoding);
 }
 
 
 void Assembler::EmitShiftImmediate(Condition cond,
                                    Shift opcode,
                                    Register rd,
                                    Register rm,
-                                   ShifterOperand so) {
+                                   Operand o) {
   ASSERT(cond != kNoCondition);
-  ASSERT(so.type() == 1);
+  ASSERT(o.type() == 1);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      static_cast<int32_t>(MOV) << kOpcodeShift |
                      static_cast<int32_t>(rd) << kRdShift |
-                     so.encoding() << kShiftImmShift |
+                     o.encoding() << kShiftImmShift |
                      static_cast<int32_t>(opcode) << kShiftShift |
                      static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
 void Assembler::EmitShiftRegister(Condition cond,
                                   Shift opcode,
                                   Register rd,
                                   Register rm,
-                                  ShifterOperand so) {
+                                  Operand o) {
   ASSERT(cond != kNoCondition);
-  ASSERT(so.type() == 0);
+  ASSERT(o.type() == 0);
   int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
                      static_cast<int32_t>(MOV) << kOpcodeShift |
                      static_cast<int32_t>(rd) << kRdShift |
-                     so.encoding() << kShiftRegisterShift |
+                     o.encoding() << kShiftRegisterShift |
                      static_cast<int32_t>(opcode) << kShiftShift |
                      B4 |
                      static_cast<int32_t>(rm);
   Emit(encoding);
 }
 
 
-void Assembler::and_(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), AND, 0, rn, rd, so);
+void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), AND, 0, rn, rd, o);
 }
 
 
-void Assembler::eor(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
+void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
 }
 
 
-void Assembler::sub(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
+void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
 }
 
-void Assembler::rsb(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
+void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), RSB, 0, rn, rd, o);
 }
 
-void Assembler::rsbs(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), RSB, 1, rn, rd, so);
+void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), RSB, 1, rn, rd, o);
 }
 
 
-void Assembler::add(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), ADD, 0, rn, rd, so);
+void Assembler::add(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ADD, 0, rn, rd, o);
 }
 
 
-void Assembler::adds(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), ADD, 1, rn, rd, so);
+void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ADD, 1, rn, rd, o);
 }
 
 
-void Assembler::subs(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), SUB, 1, rn, rd, so);
+void Assembler::subs(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
 }
 
 
-void Assembler::adc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), ADC, 0, rn, rd, so);
+void Assembler::adc(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ADC, 0, rn, rd, o);
 }
 
 
-void Assembler::adcs(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), ADC, 1, rn, rd, so);
+void Assembler::adcs(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ADC, 1, rn, rd, o);
 }
 
 
-void Assembler::sbc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), SBC, 0, rn, rd, so);
+void Assembler::sbc(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), SBC, 0, rn, rd, o);
 }
 
 
-void Assembler::sbcs(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), SBC, 1, rn, rd, so);
+void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
 }
 
 
-void Assembler::rsc(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), RSC, 0, rn, rd, so);
+void Assembler::rsc(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), RSC, 0, rn, rd, o);
 }
 
 
-void Assembler::tst(Register rn, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), TST, 1, rn, R0, so);
+void Assembler::tst(Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), TST, 1, rn, R0, o);
 }
 
 
-void Assembler::teq(Register rn, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), TEQ, 1, rn, R0, so);
+void Assembler::teq(Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), TEQ, 1, rn, R0, o);
 }
 
 
-void Assembler::cmp(Register rn, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), CMP, 1, rn, R0, so);
+void Assembler::cmp(Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
 }
 
 
-void Assembler::cmn(Register rn, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), CMN, 1, rn, R0, so);
+void Assembler::cmn(Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
 }
 
 
-void Assembler::orr(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), ORR, 0, rn, rd, so);
+void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ORR, 0, rn, rd, o);
 }
 
 
-void Assembler::orrs(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), ORR, 1, rn, rd, so);
+void Assembler::orrs(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), ORR, 1, rn, rd, o);
 }
 
 
-void Assembler::mov(Register rd, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), MOV, 0, R0, rd, so);
+void Assembler::mov(Register rd, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), MOV, 0, R0, rd, o);
 }
 
 
-void Assembler::movs(Register rd, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), MOV, 1, R0, rd, so);
+void Assembler::movs(Register rd, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
 }
 
 
-void Assembler::bic(Register rd, Register rn, ShifterOperand so,
-                    Condition cond) {
-  EmitType01(cond, so.type(), BIC, 0, rn, rd, so);
+void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), BIC, 0, rn, rd, o);
 }
 
 
-void Assembler::bics(Register rd, Register rn, ShifterOperand so,
-                     Condition cond) {
-  EmitType01(cond, so.type(), BIC, 1, rn, rd, so);
+void Assembler::bics(Register rd, Register rn, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), BIC, 1, rn, rd, o);
 }
 
 
-void Assembler::mvn(Register rd, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), MVN, 0, R0, rd, so);
+void Assembler::mvn(Register rd, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), MVN, 0, R0, rd, o);
 }
 
 
-void Assembler::mvns(Register rd, ShifterOperand so, Condition cond) {
-  EmitType01(cond, so.type(), MVN, 1, R0, rd, so);
+void Assembler::mvns(Register rd, Operand o, Condition cond) {
+  EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
 }
 
 
 void Assembler::clz(Register rd, Register rm, Condition cond) {
   ASSERT(rd != kNoRegister);
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   ASSERT(rd != PC);
   ASSERT(rm != PC);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
@@ skipping 34 matching lines @@
       (static_cast<int32_t>(cond) << kConditionShift) |
       (static_cast<int32_t>(rn) << kRnShift) |
       (static_cast<int32_t>(rd) << kRdShift) |
       (static_cast<int32_t>(rs) << kRsShift) |
       B7 | B4 |
       (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
 
-void Assembler::mul(Register rd, Register rn,
-                    Register rm, Condition cond) {
+void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
   // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
   EmitMulOp(cond, 0, R0, rd, rn, rm);
 }
 
 
 // Like mul, but sets condition flags.
-void Assembler::muls(Register rd, Register rn,
-                     Register rm, Condition cond) {
+void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
   EmitMulOp(cond, B20, R0, rd, rn, rm);
 }
 
 
 void Assembler::mla(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra + rn * rm.
   if (TargetCPUFeatures::arm_version() == ARMv7) {
     // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
     EmitMulOp(cond, B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
-    add(rd, ra, ShifterOperand(IP), cond);
+    add(rd, ra, Operand(IP), cond);
   }
 }
 
 
 void Assembler::mls(Register rd, Register rn,
                     Register rm, Register ra, Condition cond) {
   // rd <- ra - rn * rm.
   if (TargetCPUFeatures::arm_version() == ARMv7) {
     // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
     EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
   } else {
     mul(IP, rn, rm, cond);
-    sub(rd, ra, ShifterOperand(IP), cond);
+    sub(rd, ra, Operand(IP), cond);
   }
 }
 
 
 void Assembler::smull(Register rd_lo, Register rd_hi,
                       Register rn, Register rm, Condition cond) {
   ASSERT(TargetCPUFeatures::arm_version() == ARMv7);
   // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
   EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
 }
@@ skipping 1031 matching lines @@
   ASSERT(rm != kNoRegister);
   ASSERT(cond != kNoCondition);
   int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
                      B24 | B21 | (0xfff << 8) | B5 | B4 |
                      (static_cast<int32_t>(rm) << kRmShift);
   Emit(encoding);
 }
 
 
 void Assembler::MarkExceptionHandler(Label* label) {
-  EmitType01(AL, 1, TST, 1, PC, R0, ShifterOperand(0));
+  EmitType01(AL, 1, TST, 1, PC, R0, Operand(0));
   Label l;
   b(&l);
   EmitBranch(AL, label, false);
   Bind(&l);
 }
 
 
 void Assembler::Drop(intptr_t stack_elements) {
   ASSERT(stack_elements >= 0);
   if (stack_elements > 0) {
     AddImmediate(SP, SP, stack_elements * kWordSize);
   }
 }
 
 
 // Uses a code sequence that can easily be decoded.
 void Assembler::LoadWordFromPoolOffset(Register rd,
                                        int32_t offset,
                                        Condition cond) {
   ASSERT(rd != PP);
   int32_t offset_mask = 0;
   if (Address::CanHoldLoadOffset(kWord, offset, &offset_mask)) {
     ldr(rd, Address(PP, offset), cond);
   } else {
     int32_t offset_hi = offset & ~offset_mask;  // signed
     uint32_t offset_lo = offset & offset_mask;  // unsigned
     // Inline a simplified version of AddImmediate(rd, PP, offset_hi).
-    ShifterOperand shifter_op;
-    if (ShifterOperand::CanHold(offset_hi, &shifter_op)) {
-      add(rd, PP, shifter_op, cond);
+    Operand o;
+    if (Operand::CanHold(offset_hi, &o)) {
+      add(rd, PP, o, cond);
     } else {
       LoadImmediate(rd, offset_hi, cond);
-      add(rd, PP, ShifterOperand(LR), cond);
+      add(rd, PP, Operand(LR), cond);
     }
     ldr(rd, Address(rd, offset_lo), cond);
   }
 }
 
 
 void Assembler::LoadPoolPointer() {
   const intptr_t object_pool_pc_dist =
      Instructions::HeaderSize() - Instructions::object_pool_offset() +
      CodeSize() + Instr::kPCReadOffset;
@@ skipping 24 matching lines @@
   Push(IP);
 }
 
 
 void Assembler::CompareObject(Register rn, const Object& object) {
   ASSERT(rn != IP);
   if (object.IsSmi()) {
     CompareImmediate(rn, reinterpret_cast<int32_t>(object.raw()));
   } else {
     LoadObject(IP, object);
-    cmp(rn, ShifterOperand(IP));
+    cmp(rn, Operand(IP));
   }
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilterNoSmi(Register object,
                                            Register value,
                                            Label* no_update) {
   COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
                  (kOldObjectAlignmentOffset == 0));
 
   // Write-barrier triggers if the value is in the new space (has bit set) and
   // the object is in the old space (has bit cleared).
   // To check that, we compute value & ~object and skip the write barrier
   // if the bit is not set. We can't destroy the object.
-  bic(IP, value, ShifterOperand(object));
-  tst(IP, ShifterOperand(kNewObjectAlignmentOffset));
+  bic(IP, value, Operand(object));
+  tst(IP, Operand(kNewObjectAlignmentOffset));
   b(no_update, EQ);
 }
 
 
 // Preserves object and value registers.
 void Assembler::StoreIntoObjectFilter(Register object,
                                       Register value,
                                       Label* no_update) {
   // For the value we are only interested in the new/old bit and the tag bit.
   // And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
-  and_(IP, value, ShifterOperand(value, LSL, kObjectAlignmentLog2 - 1));
+  and_(IP, value, Operand(value, LSL, kObjectAlignmentLog2 - 1));
   // And the result with the negated space bit of the object.
-  bic(IP, IP, ShifterOperand(object));
-  tst(IP, ShifterOperand(kNewObjectAlignmentOffset));
+  bic(IP, IP, Operand(object));
+  tst(IP, Operand(kNewObjectAlignmentOffset));
   b(no_update, EQ);
 }
 
 
 void Assembler::StoreIntoObject(Register object,
                                 const Address& dest,
                                 Register value,
                                 bool can_value_be_smi) {
   ASSERT(object != value);
   str(value, dest);
   Label done;
   if (can_value_be_smi) {
     StoreIntoObjectFilter(object, value, &done);
   } else {
     StoreIntoObjectFilterNoSmi(object, value, &done);
   }
   // A store buffer update is required.
   RegList regs = (1 << LR);
   if (value != R0) {
     regs |= (1 << R0);  // Preserve R0.
   }
   PushList(regs);
   if (object != R0) {
-    mov(R0, ShifterOperand(object));
+    mov(R0, Operand(object));
   }
   BranchLink(&StubCode::UpdateStoreBufferLabel());
   PopList(regs);
   Bind(&done);
 }
 
 
 void Assembler::StoreIntoObjectNoBarrier(Register object,
                                          const Address& dest,
                                          Register value) {
@@ skipping 518 matching lines @@
 }
 
 
 void Assembler::PopList(RegList regs, Condition cond) {
   ldm(IA_W, SP, regs, cond);
 }
 
 
 void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
   if (rd != rm) {
-    mov(rd, ShifterOperand(rm), cond);
+    mov(rd, Operand(rm), cond);
   }
 }
 
 
 void Assembler::Lsl(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Do not use Lsl if no shift is wanted.
-  mov(rd, ShifterOperand(rm, LSL, shift_imm), cond);
+  mov(rd, Operand(rm, LSL, shift_imm), cond);
 }
 
 
 void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
-  mov(rd, ShifterOperand(rm, LSL, rs), cond);
+  mov(rd, Operand(rm, LSL, rs), cond);
 }
 
 
 void Assembler::Lsr(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Do not use Lsr if no shift is wanted.
   if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
-  mov(rd, ShifterOperand(rm, LSR, shift_imm), cond);
+  mov(rd, Operand(rm, LSR, shift_imm), cond);
 }
 
 
 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
-  mov(rd, ShifterOperand(rm, LSR, rs), cond);
+  mov(rd, Operand(rm, LSR, rs), cond);
 }
 
 
 void Assembler::Asr(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Do not use Asr if no shift is wanted.
   if (shift_imm == 32) shift_imm = 0;  // Comply to UAL syntax.
-  mov(rd, ShifterOperand(rm, ASR, shift_imm), cond);
+  mov(rd, Operand(rm, ASR, shift_imm), cond);
 }
 
 
 void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
-  mov(rd, ShifterOperand(rm, ASR, rs), cond);
+  mov(rd, Operand(rm, ASR, rs), cond);
 }
 
 
 void Assembler::Ror(Register rd, Register rm, uint32_t shift_imm,
                     Condition cond) {
   ASSERT(shift_imm != 0);  // Use Rrx instruction.
-  mov(rd, ShifterOperand(rm, ROR, shift_imm), cond);
+  mov(rd, Operand(rm, ROR, shift_imm), cond);
 }
 
 
 void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
-  mov(rd, ShifterOperand(rm, ROR, rs), cond);
+  mov(rd, Operand(rm, ROR, rs), cond);
 }
 
 
 void Assembler::Rrx(Register rd, Register rm, Condition cond) {
-  mov(rd, ShifterOperand(rm, ROR, 0), cond);
+  mov(rd, Operand(rm, ROR, 0), cond);
 }
 
 
 void Assembler::SignFill(Register rd, Register rm, Condition cond) {
   Asr(rd, rm, 31, cond);
 }
 
 
 void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
   ASSERT(qm != QTMP);
@@ skipping 97 matching lines @@
 
 void Assembler::LoadPatchableImmediate(
     Register rd, int32_t value, Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
   if ((version == ARMv5TE) || (version == ARMv6)) {
     // This sequence is patched in a few places, and should remain fixed.
     const uint32_t byte0 = (value & 0x000000ff);
     const uint32_t byte1 = (value & 0x0000ff00) >> 8;
     const uint32_t byte2 = (value & 0x00ff0000) >> 16;
     const uint32_t byte3 = (value & 0xff000000) >> 24;
-    mov(rd, ShifterOperand(4, byte3), cond);
-    orr(rd, rd, ShifterOperand(8, byte2), cond);
-    orr(rd, rd, ShifterOperand(12, byte1), cond);
-    orr(rd, rd, ShifterOperand(byte0), cond);
+    mov(rd, Operand(4, byte3), cond);
+    orr(rd, rd, Operand(8, byte2), cond);
+    orr(rd, rd, Operand(12, byte1), cond);
+    orr(rd, rd, Operand(byte0), cond);
   } else {
     ASSERT(version == ARMv7);
     const uint16_t value_low = Utils::Low16Bits(value);
     const uint16_t value_high = Utils::High16Bits(value);
     movw(rd, value_low, cond);
     movt(rd, value_high, cond);
   }
 }
 
 
 void Assembler::LoadDecodableImmediate(
     Register rd, int32_t value, Condition cond) {
   const ARMVersion version = TargetCPUFeatures::arm_version();
   if ((version == ARMv5TE) || (version == ARMv6)) {
     LoadPatchableImmediate(rd, value, cond);
   } else {
     ASSERT(version == ARMv7);
     movw(rd, Utils::Low16Bits(value), cond);
     const uint16_t value_high = Utils::High16Bits(value);
     if (value_high != 0) {
       movt(rd, value_high, cond);
     }
   }
 }
 
 
 void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(value, &shifter_op)) {
-    mov(rd, shifter_op, cond);
-  } else if (ShifterOperand::CanHold(~value, &shifter_op)) {
-    mvn(rd, shifter_op, cond);
+  Operand o;
+  if (Operand::CanHold(value, &o)) {
+    mov(rd, o, cond);
+  } else if (Operand::CanHold(~value, &o)) {
+    mvn(rd, o, cond);
   } else {
     LoadDecodableImmediate(rd, value, cond);
   }
 }
 
 
 void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
   if (!vmovs(sd, value, cond)) {
     LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
     vmovsr(sd, IP, cond);
@@ skipping 244 matching lines @@
 
 void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
   AddImmediate(rd, rd, value, cond);
 }
 
 
 void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
                              Condition cond) {
   if (value == 0) {
     if (rd != rn) {
-      mov(rd, ShifterOperand(rn), cond);
+      mov(rd, Operand(rn), cond);
     }
     return;
   }
   // We prefer to select the shorter code sequence rather than selecting add for
   // positive values and sub for negatives ones, which would slightly improve
   // the readability of generated code for some constants.
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(value, &shifter_op)) {
-    add(rd, rn, shifter_op, cond);
-  } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
-    sub(rd, rn, shifter_op, cond);
+  Operand o;
+  if (Operand::CanHold(value, &o)) {
+    add(rd, rn, o, cond);
+  } else if (Operand::CanHold(-value, &o)) {
+    sub(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
-    if (ShifterOperand::CanHold(~value, &shifter_op)) {
-      mvn(IP, shifter_op, cond);
-      add(rd, rn, ShifterOperand(IP), cond);
-    } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
-      mvn(IP, shifter_op, cond);
-      sub(rd, rn, ShifterOperand(IP), cond);
+    if (Operand::CanHold(~value, &o)) {
+      mvn(IP, o, cond);
+      add(rd, rn, Operand(IP), cond);
+    } else if (Operand::CanHold(~(-value), &o)) {
+      mvn(IP, o, cond);
+      sub(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
-      add(rd, rn, ShifterOperand(IP), cond);
+      add(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(value, &shifter_op)) {
+  Operand o;
+  if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
-    adds(rd, rn, shifter_op, cond);
-  } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
+    adds(rd, rn, o, cond);
+  } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
-    subs(rd, rn, shifter_op, cond);
+    subs(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
-    if (ShifterOperand::CanHold(~value, &shifter_op)) {
-      mvn(IP, shifter_op, cond);
-      adds(rd, rn, ShifterOperand(IP), cond);
-    } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
+    if (Operand::CanHold(~value, &o)) {
+      mvn(IP, o, cond);
+      adds(rd, rn, Operand(IP), cond);
+    } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
-      mvn(IP, shifter_op, cond);
-      subs(rd, rn, ShifterOperand(IP), cond);
+      mvn(IP, o, cond);
+      subs(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
-      adds(rd, rn, ShifterOperand(IP), cond);
+      adds(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
                                     Condition cond) {
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(value, &shifter_op)) {
+  Operand o;
+  if (Operand::CanHold(value, &o)) {
     // Handles value == kMinInt32.
-    subs(rd, rn, shifter_op, cond);
-  } else if (ShifterOperand::CanHold(-value, &shifter_op)) {
+    subs(rd, rn, o, cond);
+  } else if (Operand::CanHold(-value, &o)) {
     ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
-    adds(rd, rn, shifter_op, cond);
+    adds(rd, rn, o, cond);
   } else {
     ASSERT(rn != IP);
-    if (ShifterOperand::CanHold(~value, &shifter_op)) {
-      mvn(IP, shifter_op, cond);
-      subs(rd, rn, ShifterOperand(IP), cond);
-    } else if (ShifterOperand::CanHold(~(-value), &shifter_op)) {
+    if (Operand::CanHold(~value, &o)) {
+      mvn(IP, o, cond);
+      subs(rd, rn, Operand(IP), cond);
+    } else if (Operand::CanHold(~(-value), &o)) {
       ASSERT(value != kMinInt32);  // Would cause erroneous overflow detection.
-      mvn(IP, shifter_op, cond);
-      adds(rd, rn, ShifterOperand(IP), cond);
+      mvn(IP, o, cond);
+      adds(rd, rn, Operand(IP), cond);
     } else {
       LoadDecodableImmediate(IP, value, cond);
-      subs(rd, rn, ShifterOperand(IP), cond);
+      subs(rd, rn, Operand(IP), cond);
     }
   }
 }
 
 
 void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
                              Condition cond) {
-  ShifterOperand op;
-  if (ShifterOperand::CanHold(imm, &op)) {
-    and_(rd, rs, ShifterOperand(op), cond);
+  Operand o;
+  if (Operand::CanHold(imm, &o)) {
+    and_(rd, rs, Operand(o), cond);
   } else {
     LoadImmediate(TMP, imm, cond);
-    and_(rd, rs, ShifterOperand(TMP), cond);
+    and_(rd, rs, Operand(TMP), cond);
   }
 }
 
 
 void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(value, &shifter_op)) {
-    cmp(rn, shifter_op, cond);
+  Operand o;
+  if (Operand::CanHold(value, &o)) {
+    cmp(rn, o, cond);
   } else {
     ASSERT(rn != IP);
     LoadImmediate(IP, value, cond);
-    cmp(rn, ShifterOperand(IP), cond);
+    cmp(rn, Operand(IP), cond);
   }
 }
 
 
 void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
-  ShifterOperand shifter_op;
-  if (ShifterOperand::CanHold(imm, &shifter_op)) {
-    tst(rn, shifter_op, cond);
+  Operand o;
+  if (Operand::CanHold(imm, &o)) {
+    tst(rn, o, cond);
   } else {
     LoadImmediate(IP, imm);
-    tst(rn, ShifterOperand(IP), cond);
+    tst(rn, Operand(IP), cond);
   }
 }
 
 void Assembler::IntegerDivide(Register result, Register left, Register right,
                               DRegister tmpl, DRegister tmpr) {
   ASSERT(tmpl != tmpr);
   if (TargetCPUFeatures::integer_division_supported()) {
     sdiv(result, left, right);
   } else {
     SRegister stmpl = static_cast<SRegister>(2 * tmpl);
@@ skipping 21 matching lines @@
   CompareImmediate(left, 0);
   b(&left_neg, LT);
   b(&done, EQ);
   CompareImmediate(right, 0);
   b(&left_pos_right_neg, LT);
   b(&done, EQ);
 
   // Both positive.
   LoadImmediate(tmp, INT_MAX);
   IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, ShifterOperand(right));
+  cmp(tmp, Operand(right));
   b(overflow, LT);
   b(&done);
 
   // left positive, right non-positive.
   Bind(&left_pos_right_neg);
   LoadImmediate(tmp, INT_MIN);
   IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, ShifterOperand(right));
+  cmp(tmp, Operand(right));
   b(overflow, GT);
   b(&done);
 
   Bind(&left_neg);
   CompareImmediate(right, 0);
   b(&left_neg_right_pos, GT);
   b(&done, EQ);
 
   // both negative.
   LoadImmediate(tmp, INT_MAX);
   IntegerDivide(tmp, tmp, left, dtmp0, dtmp1);
-  cmp(tmp, ShifterOperand(right));
+  cmp(tmp, Operand(right));
   b(overflow, GT);
   b(&done);
 
   // left non-positive, right positive.
   Bind(&left_neg_right_pos);
   LoadImmediate(tmp, INT_MIN);
   IntegerDivide(tmp, tmp, right, dtmp0, dtmp1);
-  cmp(tmp, ShifterOperand(left));
+  cmp(tmp, Operand(left));
   b(overflow, GT);
 
   Bind(&done);
 }
 
 
 static int NumRegsBelowFP(RegList regs) {
   int count = 0;
   for (int i = 0; i < FP; i++) {
     if ((regs & (1 << i)) != 0) {
       count++;
     }
   }
   return count;
 }
 
 
 void Assembler::EnterFrame(RegList regs, intptr_t frame_size) {
   if (prologue_offset_ == -1) {
     prologue_offset_ = CodeSize();
   }
   PushList(regs);
   if ((regs & (1 << FP)) != 0) {
     // Set FP to the saved previous FP.
-    add(FP, SP, ShifterOperand(4 * NumRegsBelowFP(regs)));
+    add(FP, SP, Operand(4 * NumRegsBelowFP(regs)));
   }
   AddImmediate(SP, -frame_size);
 }
 
 
 void Assembler::LeaveFrame(RegList regs) {
   ASSERT((regs & (1 << PC)) == 0);  // Must not pop PC.
   if ((regs & (1 << FP)) != 0) {
     // Use FP to set SP.
-    sub(SP, FP, ShifterOperand(4 * NumRegsBelowFP(regs)));
+    sub(SP, FP, Operand(4 * NumRegsBelowFP(regs)));
   }
   PopList(regs);
 }
 
 
 void Assembler::Ret() {
   bx(LR);
 }
 
 
 void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
   // Reserve space for arguments and align frame before entering
   // the C++ world.
   AddImmediate(SP, -frame_space);
   if (OS::ActivationFrameAlignment() > 1) {
-    bic(SP, SP, ShifterOperand(OS::ActivationFrameAlignment() - 1));
+    bic(SP, SP, Operand(OS::ActivationFrameAlignment() - 1));
   }
 }
 
 
 void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
   // Preserve volatile CPU registers.
   EnterFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR), 0);
 
   // Preserve all volatile FPU registers.
   if (TargetCPUFeatures::vfp_supported()) {
@@ skipping 73 matching lines @@
 
 // On entry to a function compiled for OSR, the caller's frame pointer, the
 // stack locals, and any copied parameters are already in place.  The frame
 // pointer is already set up.  The PC marker is not correct for the
 // optimized function and there may be extra space for spill slots to
 // allocate. We must also set up the pool pointer for the function.
 void Assembler::EnterOsrFrame(intptr_t extra_size) {
   const intptr_t offset = CodeSize();
 
   Comment("EnterOsrFrame");
-  mov(IP, ShifterOperand(PC));
+  mov(IP, Operand(PC));
 
   AddImmediate(IP, -offset);
   str(IP, Address(FP, kPcMarkerSlotFromFp * kWordSize));
 
   // Setup pool pointer for this dart function.
   LoadPoolPointer();
 
   AddImmediate(SP, -extra_size);
 }
 
 
 void Assembler::LeaveDartFrame() {
   LeaveFrame((1 << PP) | (1 << FP) | (1 << LR));
   // Adjust SP for PC pushed in EnterDartFrame.
   AddImmediate(SP, kWordSize);
 }
 
 
 void Assembler::EnterStubFrame(bool load_pp) {
   // Push 0 as saved PC for stub frames.
-  mov(IP, ShifterOperand(LR));
-  mov(LR, ShifterOperand(0));
+  mov(IP, Operand(LR));
+  mov(LR, Operand(0));
   RegList regs = (1 << PP) | (1 << FP) | (1 << IP) | (1 << LR);
   EnterFrame(regs, 0);
   if (load_pp) {
     // Setup pool pointer for this stub.
     LoadPoolPointer();
   }
 }
 
 
 void Assembler::LeaveStubFrame() {
@@ skipping 58 matching lines @@
     const uword size_field_offset = (space == Heap::kNew) ?
       ClassHeapStats::allocated_size_since_gc_new_space_offset() :
       ClassHeapStats::allocated_size_since_gc_old_space_offset();
     LoadImmediate(temp_reg, class_heap_stats_table_address + class_offset);
     const Address& count_address = Address(temp_reg, count_field_offset);
     const Address& size_address = Address(temp_reg, size_field_offset);
     ldr(TMP, count_address);
     AddImmediate(TMP, 1);
     str(TMP, count_address);
     ldr(TMP, size_address);
-    add(TMP, TMP, ShifterOperand(size_reg));
+    add(TMP, TMP, Operand(size_reg));
     str(TMP, size_address);
   } else {
     ASSERT(temp_reg != kNoRegister);
     const uword class_offset = cid * sizeof(ClassHeapStats);  // NOLINT
     const uword count_field_offset = (space == Heap::kNew) ?
       ClassHeapStats::allocated_since_gc_new_space_offset() :
       ClassHeapStats::allocated_since_gc_old_space_offset();
     const uword size_field_offset = (space == Heap::kNew) ?
       ClassHeapStats::allocated_size_since_gc_new_space_offset() :
       ClassHeapStats::allocated_size_since_gc_old_space_offset();
     LoadImmediate(temp_reg, class_table->ClassStatsTableAddress());
     ldr(temp_reg, Address(temp_reg, 0));
     AddImmediate(temp_reg, class_offset);
     ldr(TMP, Address(temp_reg, count_field_offset));
     AddImmediate(TMP, 1);
     str(TMP, Address(temp_reg, count_field_offset));
     ldr(TMP, Address(temp_reg, size_field_offset));
-    add(TMP, TMP, ShifterOperand(size_reg));
+    add(TMP, TMP, Operand(size_reg));
     str(TMP, Address(temp_reg, size_field_offset));
   }
 }
 
 
 void Assembler::TryAllocate(const Class& cls,
                             Label* failure,
                             Register instance_reg,
                             Register temp_reg) {
   ASSERT(failure != NULL);
   if (FLAG_inline_alloc) {
     Heap* heap = Isolate::Current()->heap();
     const intptr_t instance_size = cls.instance_size();
     LoadImmediate(instance_reg, heap->TopAddress());
     ldr(instance_reg, Address(instance_reg, 0));
     AddImmediate(instance_reg, instance_size);
 
     // instance_reg: potential next object start.
     LoadImmediate(IP, heap->EndAddress());
     ldr(IP, Address(IP, 0));
-    cmp(IP, ShifterOperand(instance_reg));
+    cmp(IP, Operand(instance_reg));
     // fail if heap end unsigned less than or equal to instance_reg.
     b(failure, LS);
 
     // Successfully allocated the object, now update top to point to
     // next object start and store the class in the class field of object.
     LoadImmediate(IP, heap->TopAddress());
     str(instance_reg, Address(IP, 0));
 
     ASSERT(instance_size >= kHeapObjectTag);
     AddImmediate(instance_reg, -instance_size + kHeapObjectTag);
@@ skipping 86 matching lines @@
 
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM