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1 // Copyright 2015 The Chromium Authors. All rights reserved. | 1 // Copyright 2015 The Chromium Authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "chrome/browser/metrics/perf/cpu_identity.h" | 5 #include "chrome/browser/metrics/perf/cpu_identity.h" |
6 | 6 |
7 #include <algorithm> // for std::lower_bound() | 7 #include <algorithm> // for std::lower_bound() |
8 #include <string.h> | 8 #include <string.h> |
9 | 9 |
10 #include "base/cpu.h" | 10 #include "base/cpu.h" |
11 #include "base/macros.h" | 11 #include "base/macros.h" |
12 #include "base/strings/string_util.h" | 12 #include "base/strings/string_util.h" |
13 #include "base/strings/stringprintf.h" | 13 #include "base/strings/stringprintf.h" |
14 #include "base/sys_info.h" | 14 #include "base/sys_info.h" |
15 | 15 |
16 namespace internal { | 16 namespace internal { |
17 | 17 |
18 const IntelUarchTableEntry kIntelUarchTable[] = { | 18 const IntelUarchTableEntry kIntelUarchTable[] = { |
19 // These were found on various sources on the Internet. Main ones are: | 19 // These were found on various sources on the Internet. Main ones are: |
20 // http://instlatx64.atw.hu/ for CPUID to model name and | 20 // http://instlatx64.atw.hu/ for CPUID to model name and |
21 // http://www.cpu-world.com for model name to microarchitecture | 21 // http://www.cpu-world.com for model name to microarchitecture |
22 {"06_09", "Banias"}, | 22 {"06_09", "Banias"}, |
23 {"06_0D", "Dothan"}, | 23 {"06_0D", "Dothan"}, |
24 {"06_0F", "Merom"}, | 24 {"06_0F", "Merom"}, |
25 {"06_16", "Merom"}, | 25 {"06_16", "Merom"}, |
26 {"06_17", "Nehalem"}, | 26 {"06_17", "Nehalem"}, |
27 {"06_1A", "Nehalem"}, | 27 {"06_1A", "Nehalem"}, |
28 {"06_1C", "Bonnell"}, // Atom | 28 {"06_1C", "Bonnell"}, // Atom |
29 {"06_1D", "Nehalem"}, | 29 {"06_1D", "Nehalem"}, |
30 {"06_1E", "Nehalem"}, | 30 {"06_1E", "Nehalem"}, |
31 {"06_1F", "Nehalem"}, | 31 {"06_1F", "Nehalem"}, |
32 {"06_25", "Westmere"}, | 32 {"06_25", "Westmere"}, |
33 {"06_26", "Bonnell"}, // Atom | 33 {"06_26", "Bonnell"}, // Atom |
34 {"06_2A", "SandyBridge"}, | 34 {"06_2A", "SandyBridge"}, |
35 {"06_2C", "Westmere"}, | 35 {"06_2C", "Westmere"}, |
36 {"06_2D", "SandyBridge"}, | 36 {"06_2D", "SandyBridge"}, |
37 {"06_2E", "Nehalem"}, | 37 {"06_2E", "Nehalem"}, |
38 {"06_2F", "Westmere"}, | 38 {"06_2F", "Westmere"}, |
39 {"06_36", "Saltwell"}, // Atom | 39 {"06_36", "Saltwell"}, // Atom |
40 {"06_37", "Silvermont"}, | 40 {"06_37", "Silvermont"}, |
41 {"06_3A", "IvyBridge"}, | 41 {"06_3A", "IvyBridge"}, |
42 {"06_3C", "Haswell"}, | 42 {"06_3C", "Haswell"}, |
43 {"06_3D", "Broadwell"}, | 43 {"06_3D", "Broadwell"}, |
44 {"06_3E", "IvyBridge"}, | 44 {"06_3E", "IvyBridge"}, |
45 {"06_3F", "Haswell"}, | 45 {"06_3F", "Haswell"}, |
46 {"06_45", "Haswell"}, | 46 {"06_45", "Haswell"}, |
47 {"06_46", "Haswell"}, | 47 {"06_46", "Haswell"}, |
48 {"06_47", "Broadwell"}, // Broadwell-H | 48 {"06_47", "Broadwell"}, // Broadwell-H |
49 {"06_4C", "Airmont"}, // Braswell | 49 {"06_4C", "Airmont"}, // Braswell |
50 {"06_4D", "Silvermont"}, // Avoton/Rangely | 50 {"06_4D", "Silvermont"}, // Avoton/Rangely |
51 {"06_4E", "Skylake"}, | 51 {"06_4E", "Skylake"}, |
52 {"06_56", "Broadwell"}, // Broadwell-DE | 52 {"06_55", "Skylake"}, // Skylake-X |
53 {"06_5E", "Skylake"}, | 53 {"06_56", "Broadwell"}, // Broadwell-DE |
54 {"0F_03", "Prescott"}, | 54 {"06_5C", "Goldmont"}, |
55 {"0F_04", "Prescott"}, | 55 {"06_5E", "Skylake"}, |
56 {"0F_06", "Presler"}, | 56 {"06_5F", "Goldmont"}, // Denverton |
| 57 {"06_8E", "Kabylake"}, |
| 58 {"06_9E", "Kabylake"}, |
| 59 {"0F_03", "Prescott"}, |
| 60 {"0F_04", "Prescott"}, |
| 61 {"0F_06", "Presler"}, |
57 }; | 62 }; |
58 | 63 |
59 const IntelUarchTableEntry* kIntelUarchTableEnd = | 64 const IntelUarchTableEntry* kIntelUarchTableEnd = |
60 kIntelUarchTable + arraysize(kIntelUarchTable); | 65 kIntelUarchTable + arraysize(kIntelUarchTable); |
61 | 66 |
62 bool IntelUarchTableCmp(const IntelUarchTableEntry& a, | 67 bool IntelUarchTableCmp(const IntelUarchTableEntry& a, |
63 const IntelUarchTableEntry& b) { | 68 const IntelUarchTableEntry& b) { |
64 return strcmp(a.family_model, b.family_model) < 0; | 69 return strcmp(a.family_model, b.family_model) < 0; |
65 } | 70 } |
66 | 71 |
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99 return result; | 104 return result; |
100 } | 105 } |
101 | 106 |
102 std::string SimplifyCPUModelName(const std::string& model_name) { | 107 std::string SimplifyCPUModelName(const std::string& model_name) { |
103 std::string result = model_name; | 108 std::string result = model_name; |
104 std::replace(result.begin(), result.end(), ' ', '-'); | 109 std::replace(result.begin(), result.end(), ' ', '-'); |
105 base::ReplaceSubstringsAfterOffset(&result, 0, "(R)", ""); | 110 base::ReplaceSubstringsAfterOffset(&result, 0, "(R)", ""); |
106 return base::ToLowerASCII(result); | 111 return base::ToLowerASCII(result); |
107 } | 112 } |
108 | 113 |
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