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|   1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// |   1 //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// | 
|   2 // |   2 // | 
|   3 //                        The Subzero Code Generator |   3 //                        The Subzero Code Generator | 
|   4 // |   4 // | 
|   5 // This file is distributed under the University of Illinois Open Source |   5 // This file is distributed under the University of Illinois Open Source | 
|   6 // License. See LICENSE.TXT for details. |   6 // License. See LICENSE.TXT for details. | 
|   7 // |   7 // | 
|   8 //===----------------------------------------------------------------------===// |   8 //===----------------------------------------------------------------------===// | 
|   9 // |   9 // | 
|  10 // This file defines properties of lowered x86-32 instructions in the |  10 // This file defines properties of lowered x86-32 instructions in the | 
|  11 // form of x-macros. |  11 // form of x-macros. | 
|  12 // |  12 // | 
|  13 //===----------------------------------------------------------------------===// |  13 //===----------------------------------------------------------------------===// | 
|  14  |  14  | 
|  15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF |  15 #ifndef SUBZERO_SRC_ICEINSTX8632_DEF | 
|  16 #define SUBZERO_SRC_ICEINSTX8632_DEF |  16 #define SUBZERO_SRC_ICEINSTX8632_DEF | 
|  17  |  17  | 
|  18 #define REGX8632_TABLE                                                  \ |  18 #define REGX8632_TABLE                                                  \ | 
|  19   /* val, init, name, name16, name8, scratch, preserved, stackptr,      \ |  19   /* val, init, name, name16, name8, scratch, preserved, stackptr,      \ | 
|  20      frameptr, isI8, isInt, isFP */                                     \ |  20      frameptr, isI8, isInt, isFP */                                     \ | 
|  21   X(Reg_eax, = 0,             "eax",  "ax", "al", 1, 0, 0, 0, 1, 1, 0)  \ |  21   X(Reg_eax, = 0,             "eax",  "ax", "al", 1, 0, 0, 0, 1, 1, 0)  \ | 
|  22   X(Reg_ecx, = Reg_eax + 1,   "ecx",  "cx", "cl", 1, 0, 0, 0, 1, 1, 0)  \ |  22   X(Reg_ecx, = Reg_eax + 1,   "ecx",  "cx", "cl", 1, 0, 0, 0, 1, 1, 0)  \ | 
|  23   X(Reg_edx, = Reg_eax + 2,   "edx",  "dx", "dl", 1, 0, 0, 0, 1, 1, 0)  \ |  23   X(Reg_edx, = Reg_eax + 2,   "edx",  "dx", "dl", 1, 0, 0, 0, 1, 1, 0)  \ | 
|  24   X(Reg_ebx, = Reg_eax + 3,   "ebx",  "bx", "bl", 0, 1, 0, 0, 1, 1, 0)  \ |  24   X(Reg_ebx, = Reg_eax + 3,   "ebx",  "bx", "bl", 0, 1, 0, 0, 1, 1, 0)  \ | 
|  25   X(Reg_esp, = Reg_eax + 4,   "esp",  "sp",     , 0, 0, 1, 0, 0, 1, 0)  \ |  25   X(Reg_esp, = Reg_eax + 4,   "esp",  "sp", ""  , 0, 0, 1, 0, 0, 1, 0)  \ | 
|  26   X(Reg_ebp, = Reg_eax + 5,   "ebp",  "bp",     , 0, 1, 0, 1, 0, 1, 0)  \ |  26   X(Reg_ebp, = Reg_eax + 5,   "ebp",  "bp", ""  , 0, 1, 0, 1, 0, 1, 0)  \ | 
|  27   X(Reg_esi, = Reg_eax + 6,   "esi",  "si",     , 0, 1, 0, 0, 0, 1, 0)  \ |  27   X(Reg_esi, = Reg_eax + 6,   "esi",  "si", ""  , 0, 1, 0, 0, 0, 1, 0)  \ | 
|  28   X(Reg_edi, = Reg_eax + 7,   "edi",  "di",     , 0, 1, 0, 0, 0, 1, 0)  \ |  28   X(Reg_edi, = Reg_eax + 7,   "edi",  "di", ""  , 0, 1, 0, 0, 0, 1, 0)  \ | 
|  29   X(Reg_ah,   /*none*/,       "???",      , "ah", 0, 0, 0, 0, 1, 0, 0)  \ |  29   X(Reg_ah,  = Reg_edi + 1,   "???",  ""  , "ah", 0, 0, 0, 0, 1, 0, 0)  \ | 
|  30   X(Reg_xmm0, /*none*/,       "xmm0",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  30   X(Reg_xmm0, = Reg_ah + 1,   "xmm0", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  31   X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  31   X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  32   X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  32   X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  33   X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  33   X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  34   X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  34   X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  35   X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  35   X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  36   X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  36   X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  37   X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7",     ,     , 1, 0, 0, 0, 0, 0, 1)  \ |  37   X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", ""  , ""  , 1, 0, 0, 0, 0, 0, 1)  \ | 
|  38 //#define X(val, init, name, name16, name8, scratch, preserved, stackptr, |  38 //#define X(val, init, name, name16, name8, scratch, preserved, stackptr, | 
|  39 //          frameptr, isI8, isInt, isFP) |  39 //          frameptr, isI8, isInt, isFP) | 
|  40  |  40  | 
|  41  |  41  | 
|  42 #define ICEINSTX8632BR_TABLE   \ |  42 #define ICEINSTX8632BR_TABLE   \ | 
|  43   /* enum value, dump, emit */ \ |  43   /* enum value, dump, emit */ \ | 
|  44   X(Br_a,        "a",  "ja")   \ |  44   X(Br_a,        "a",  "ja")   \ | 
|  45   X(Br_ae,       "ae", "jae")  \ |  45   X(Br_ae,       "ae", "jae")  \ | 
|  46   X(Br_b,        "b",  "jb")   \ |  46   X(Br_b,        "b",  "jb")   \ | 
|  47   X(Br_be,       "be", "jbe")  \ |  47   X(Br_be,       "be", "jbe")  \ | 
|  48   X(Br_e,        "e",  "je")   \ |  48   X(Br_e,        "e",  "je")   \ | 
|  49   X(Br_g,        "g",  "jg")   \ |  49   X(Br_g,        "g",  "jg")   \ | 
|  50   X(Br_ge,       "ge", "jge")  \ |  50   X(Br_ge,       "ge", "jge")  \ | 
|  51   X(Br_l,        "l",  "jl")   \ |  51   X(Br_l,        "l",  "jl")   \ | 
|  52   X(Br_le,       "le", "jle")  \ |  52   X(Br_le,       "le", "jle")  \ | 
|  53   X(Br_ne,       "ne", "jne")  \ |  53   X(Br_ne,       "ne", "jne")  \ | 
|  54   X(Br_np,       "np", "jnp")  \ |  54   X(Br_np,       "np", "jnp")  \ | 
|  55   X(Br_p,        "p",  "jp")   \ |  55   X(Br_p,        "p",  "jp")   \ | 
|  56 //#define X(tag, dump, emit) |  56 //#define X(tag, dump, emit) | 
|  57  |  57  | 
|  58 #define ICETYPEX8632_TABLE                \ |  58 #define ICETYPEX8632_TABLE                \ | 
|  59   /* tag,         cvt, sdss, width */     \ |  59   /* tag,         cvt, sdss, width */     \ | 
|  60   X(IceType_void, "?",     , "???")       \ |  60   X(IceType_void, "?", ""  , "???")       \ | 
|  61   X(IceType_i1,   "i",     , "byte ptr")  \ |  61   X(IceType_i1,   "i", ""  , "byte ptr")  \ | 
|  62   X(IceType_i8,   "i",     , "byte ptr")  \ |  62   X(IceType_i8,   "i", ""  , "byte ptr")  \ | 
|  63   X(IceType_i16,  "i",     , "word ptr")  \ |  63   X(IceType_i16,  "i", ""  , "word ptr")  \ | 
|  64   X(IceType_i32,  "i",     , "dword ptr") \ |  64   X(IceType_i32,  "i", ""  , "dword ptr") \ | 
|  65   X(IceType_i64,  "i",     , "qword ptr") \ |  65   X(IceType_i64,  "i", ""  , "qword ptr") \ | 
|  66   X(IceType_f32,  "s", "ss", "dword ptr") \ |  66   X(IceType_f32,  "s", "ss", "dword ptr") \ | 
|  67   X(IceType_f64,  "d", "sd", "qword ptr") \ |  67   X(IceType_f64,  "d", "sd", "qword ptr") \ | 
|  68   X(IceType_NUM,  "?",     , "???")       \ |  | 
|  69 //#define X(tag, cvt, sdss, width) |  68 //#define X(tag, cvt, sdss, width) | 
|  70  |  69  | 
|  71 #endif // SUBZERO_SRC_ICEINSTX8632_DEF |  70 #endif // SUBZERO_SRC_ICEINSTX8632_DEF | 
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