MIPS: Avoid flushing the icache unnecessarily when updating target addresses in code.

MIPS: Avoid flushing the icache unnecessarily when updating target addresses in code.

Port r21380 (ef20a0a)

Original commit message:
This CL updates RelocInfo update operations and set_target_address_at to enable
skipping of the icache flush if it going to be batched up later.
Code::CopyFrom and Code::Relocate are modified to avoid individual icache
flushes since the whole code area will be flushed after the reloc info is
updated.

These changes reduce a regression when enabling the OOL constant pool on Arm,
since this change can cause MovT/MovW instructions for relocatable targets
if the constant pool is full.

Scores for Mandreel latency on a Nexus 5:
- OOL CP disabled: 3533
- OOL CP enabled, without this CL: 1825
- OOL CP enabled, with change: 3015

BUG=

[Paul Lind, 2014-05-20 14:47:03]

lgtm

[Paul Lind, 2014-05-20 14:49:39]

Committed as r21390.