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1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2014, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ | 5 #ifndef RUNTIME_VM_ASSEMBLER_ARM64_H_ |
6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ | 6 #define RUNTIME_VM_ASSEMBLER_ARM64_H_ |
7 | 7 |
8 #ifndef RUNTIME_VM_ASSEMBLER_H_ | 8 #ifndef RUNTIME_VM_ASSEMBLER_H_ |
9 #error Do not include assembler_arm64.h directly; use assembler.h instead. | 9 #error Do not include assembler_arm64.h directly; use assembler.h instead. |
10 #endif | 10 #endif |
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735 (a.type() == Address::PairPreIndex)); | 735 (a.type() == Address::PairPreIndex)); |
736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); | 736 EmitLoadStoreRegPair(LDP, rt, rt2, a, sz); |
737 } | 737 } |
738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { | 738 void stp(Register rt, Register rt2, Address a, OperandSize sz = kDoubleWord) { |
739 ASSERT((a.type() == Address::PairOffset) || | 739 ASSERT((a.type() == Address::PairOffset) || |
740 (a.type() == Address::PairPostIndex) || | 740 (a.type() == Address::PairPostIndex) || |
741 (a.type() == Address::PairPreIndex)); | 741 (a.type() == Address::PairPreIndex)); |
742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); | 742 EmitLoadStoreRegPair(STP, rt, rt2, a, sz); |
743 } | 743 } |
744 | 744 |
745 void ldxr(Register rt, Register rn, OperandSize size = kDoubleWord) { | 745 void ldxr(Register rt, Register rn) { |
746 // rt = value | 746 // rt = value |
747 // rn = address | 747 // rn = address |
748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, size); | 748 EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord); |
749 } | 749 } |
750 void stxr(Register rs, | 750 void stxr(Register rs, Register rt, Register rn) { |
751 Register rt, | |
752 Register rn, | |
753 OperandSize size = kDoubleWord) { | |
754 // rs = status (1 = failure, 0 = success) | 751 // rs = status (1 = failure, 0 = success) |
755 // rt = value | 752 // rt = value |
756 // rn = address | 753 // rn = address |
757 EmitLoadStoreExclusive(STXR, rs, rn, rt, size); | 754 EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord); |
758 } | 755 } |
759 void clrex() { | 756 void clrex() { |
760 const int32_t encoding = static_cast<int32_t>(CLREX); | 757 const int32_t encoding = static_cast<int32_t>(CLREX); |
761 Emit(encoding); | 758 Emit(encoding); |
762 } | 759 } |
763 | 760 |
764 // Conditional select. | 761 // Conditional select. |
765 void csel(Register rd, Register rn, Register rm, Condition cond) { | 762 void csel(Register rd, Register rn, Register rm, Condition cond) { |
766 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); | 763 EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord); |
767 } | 764 } |
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1697 (static_cast<int32_t>(hw_idx) << kHWShift) | | 1694 (static_cast<int32_t>(hw_idx) << kHWShift) | |
1698 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); | 1695 (static_cast<int32_t>(imm.value() & 0xffff) << kImm16Shift); |
1699 Emit(encoding); | 1696 Emit(encoding); |
1700 } | 1697 } |
1701 | 1698 |
1702 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, | 1699 void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, |
1703 Register rs, | 1700 Register rs, |
1704 Register rn, | 1701 Register rn, |
1705 Register rt, | 1702 Register rt, |
1706 OperandSize sz = kDoubleWord) { | 1703 OperandSize sz = kDoubleWord) { |
1707 ASSERT(sz == kDoubleWord || sz == kWord); | 1704 ASSERT(sz == kDoubleWord); |
1708 const int32_t size = B31 | (sz == kDoubleWord ? B30 : 0); | 1705 const int32_t size = B31 | B30; |
1709 | 1706 |
1710 ASSERT((rs != kNoRegister) && (rs != ZR)); | 1707 ASSERT((rs != kNoRegister) && (rs != ZR)); |
1711 ASSERT((rn != kNoRegister) && (rn != ZR)); | 1708 ASSERT((rn != kNoRegister) && (rn != ZR)); |
1712 ASSERT((rt != kNoRegister) && (rt != ZR)); | 1709 ASSERT((rt != kNoRegister) && (rt != ZR)); |
1713 | 1710 |
1714 const int32_t encoding = | 1711 const int32_t encoding = |
1715 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | | 1712 op | size | (static_cast<int32_t>(ConcreteRegister(rs)) << kRsShift) | |
1716 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | | 1713 (static_cast<int32_t>(ConcreteRegister(rn)) << kRnShift) | |
1717 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); | 1714 (static_cast<int32_t>(ConcreteRegister(rt)) << kRtShift); |
1718 | 1715 |
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1937 Register value, | 1934 Register value, |
1938 Label* no_update); | 1935 Label* no_update); |
1939 | 1936 |
1940 DISALLOW_ALLOCATION(); | 1937 DISALLOW_ALLOCATION(); |
1941 DISALLOW_COPY_AND_ASSIGN(Assembler); | 1938 DISALLOW_COPY_AND_ASSIGN(Assembler); |
1942 }; | 1939 }; |
1943 | 1940 |
1944 } // namespace dart | 1941 } // namespace dart |
1945 | 1942 |
1946 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ | 1943 #endif // RUNTIME_VM_ASSEMBLER_ARM64_H_ |
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